JP3022620B2 - DC-DC converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

 [Object of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-DC converter for reducing switching loss, and more particularly to a DC-D converter for reducing the loss by combining two types of resonance circuits.
It relates to a C converter.

[0002]

2. Description of the Related Art In recent years, as switching elements used in DC-DC converters having high switching frequencies have appeared, small-sized components such as transformers, choke coils, and smoothing capacitors occupying a large volume in DC-DC converters. Therefore, miniaturization of a DC-DC converter is expected as a result.

However, the switching loss caused by the overlap of the current and the voltage at the time of turning on and turning off when the switching element performs the switching operation is increasing with an increase in the frequency, and as described above, the components are downsized. Nevertheless, at present, miniaturization as a whole is hindered by heat dissipation measures against heat generation due to switching loss.

[0004] Further, with the increase in the frequency of DC-DC converters, insulated gate field effect transistors (hereinafter referred to as MOSFETs) have been generally used as switching elements. However, MOSFETs have parasitic capacitance inside. If the switching operation is performed while a voltage is applied, a short circuit of the parasitic capacitance occurs, causing loss and noise. Therefore, noise countermeasures are required.

FIG. 4 shows an example of a conventional DC-DC converter, and shows a configuration of a single-type forward DC-DC converter. On the primary side of the transformer T, a DC source ES, a primary winding L1, and a MOSFET Q1 as a switching element are connected in series, and on the secondary side of the transformer T, a rectifier diode D4 is connected to a secondary winding L2. A rectifying / smoothing circuit REC including a wheel diode D5, a choke coil L3, and a smoothing capacitor C3 is connected. D1 connected in parallel to the MOSFET Q1 is a parasitic diode, and C1 is a parasitic capacitance.

[0006] Such a DC-DC converter is an MO.
When the SFET Q1 is turned on, a current flows through the primary winding L1 on the input side, and thereby the secondary winding L2 on the output side.
And a rectifier / smoothing circuit REC converts the voltage into a direct current, which is output from a terminal TO-TO '.

FIG. 5 is a waveform diagram for explaining the operation of the DC-DC converter. VG1 is the gate voltage of the MOSFET Q1, VQ1 is the drain-source voltage, and IQ1 is 1.
It shows a drain current (a drain-source current) flowing through the MOSFET Q1 via the next winding L1. The horizontal axis shows a common time axis. In this waveform diagram, Q1
In the period from time t1 to time t2 when is turned on and the period from time t3 to time t4 when Q1 is turned off, VQ1 and IQ1 are not zero but overlap with a certain value. Therefore, switching loss (power loss) occurs when the MOSFET Q1 is turned on and off.

Therefore, in order to reduce the switching loss, a technique for performing zero voltage switching using a resonance phenomenon has been developed. In this technique, a resonance circuit is configured by combining a resonance coil or a primary winding of a transformer and a capacitor.

[0009]

However, in the conventional technique utilizing the resonance phenomenon due to voltage as described above, the voltage applied to the switching element becomes higher than the circuit voltage, so that an element having a high breakdown voltage is required as the switching element. There is a problem. For example, recently, MOSFETs are generally used as switching elements. However, since MOSFETs with high breakdown voltage have high on-resistance, losses when the switching elements are conducting become large, and as a result, switching losses cannot be reduced so much. become. In addition, since the resonance condition is determined by the fixed inductance and the capacitance of the capacitor, the switching operation cannot be controlled by the on / off ratio.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and enables zero voltage switching without applying a high voltage to a switching element. It is another object of the present invention to provide a DC-DC converter capable of reducing switching loss and enabling control by an ON / OFF ratio.

[Structure of the Invention]

[0012]

According to the present invention, a DC source, a primary winding and a main switching element are connected in series to a primary side of a transformer, and a secondary side of the transformer is connected to a primary side of the transformer. In a DC-DC converter to which a rectifying / smoothing circuit is connected, a sub-switching element for applying a reset voltage to a transformer connected in parallel to a main switching element for controlling a resonance condition, a first capacitor for providing one resonance condition, and a resonance condition And a second capacitor connected in series with the sub-switching element to provide another resonance condition, and a saturable reactor connected to the secondary side of the transformer for stabilizing the resonance condition. The first capacitor and the primary winding form a short-period resonance circuit, and the second capacitor and the primary winding form a long-period resonance circuit. Configured, on of the main switching element and the sub-switching element, it is characterized in that the operation of the two resonant circuits in accordance with the off is migratable controlled together.

[0013]

The resonance phenomenon is ensured by providing a period in which the main switching element and the sub-switching element are simultaneously turned off and alternately turned on and off. Further, by providing this off period, it is possible to perform zero voltage switching by suppressing the ON of one of the switching elements until the resonance waveform reaches zero voltage. Further, the second capacitor is connected to the first capacitor.
By setting the capacitance to be sufficiently larger than that of the capacitor, the voltage applied when the main switching element is turned off by the sub-switching element can be flattened to a practically usable level. Also, the switching loss can be reduced. Also, control based on the on / off ratio is possible.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a DC-DC converter according to the present invention.
S, a primary winding L1, and a main switching element for controlling resonance conditions, for example, an N-channel insulated gate field effect transistor (hereinafter referred to as MOSFET) Q1 are connected in series. D1 is a parasitic diode of the MOSFET Q1, and C1 is a parasitic capacitance.

MOSFET as a main switching element
Q1 is a sub-switching element for controlling a voltage state applied to the element as described later, for example, an N-channel insulated gate field effect transistor (MOSFET) Q2,
Are connected in parallel with each other. MOSFET Q2 which is a sub-switching element
Is connected in series with a second capacitor Cc. These first and second capacitors Cc and Cr are used to generate resonance conditions of different circuit voltages, respectively, and they are set in a relationship such that the capacitance value of Cc is sufficiently larger than (Cr × 10). .

On the secondary side of the transformer T, a rectifying / smoothing circuit including a saturable reactor SR, a rectifying diode D4, a flywheel diode D5, a choke coil L3, and a smoothing capacitor C3 for stabilizing resonance conditions in a secondary winding L2. REC is connected. A gap is provided in the transformer T as necessary to secure the value of L1, which is one of the resonance conditions.

By setting the first and second capacitors Cr and Cc in the above-described relationship, a first resonance circuit having a short cycle is constituted by the first capacitor Cr and the primary winding L1. Further, the second capacitor Cc and the primary winding L1 form a second resonance circuit having a long cycle. These first
The second resonance circuit is controlled so that its operation can be shifted to each other according to the on / off state of the MOSFETs Q1 and Q2.

As shown in FIG. 2, the MOSFETs Q1 and Q2 are turned on and off alternately in a cycle T having periods ΔT1 and ΔT2 which are simultaneously off and a period To which is on. Assuming that the ON time ratio (To / T) is d, Q2 is configured to be controlled by the ON time ratio of {1−d− (ΔT1 + ΔT2) / T}. Thus, resonance development can be ensured by providing a period in which Q1 and Q2 are simultaneously turned off and alternately turned on and off. The main switching element and the sub-switching element that are turned on / off in this manner are not limited to MOSFETs, but can be similarly configured with other elements such as SITs, IGBTs, and bipolar transistors.

Next, the operation of this embodiment will be described with reference to the waveform diagram of FIG. In FIG. 3, VG1 is a MOSFET Q
1, VG2 is the gate voltage of MOSFET Q2, VQ1 is the drain voltage (drain-source voltage) of Q1, IQ1 is the drain current (drain-source current) flowing through Q1, and IL is the primary winding L1. The current flowing, ICr is the current flowing through the first capacitor Cr, IC
c is the current flowing through the second capacitor Cc, VCc is the second current
VQ2 indicates the drain voltage (drain-source voltage) of Q2, and IQ2 indicates the drain current (drain-source current) flowing through Q2. The horizontal axis shows a common time axis.

First, during the ON period of Q1 from time t1 to time t2, the primary winding L of the transformer T is switched from the DC source ES.
When the voltage is applied to 1, the energy is transmitted to the secondary winding L2 via the transformer T, and at the same time, 1
The exciting current of the next winding L1 increases. Transformer T 2
The DC voltage output from the output terminal TO-TO 'on the next side is stabilized by controlling the on-time ratio (To / T).

When Q1 turns off at time t2, the primary winding L
The exciting current IL flowing through 1 cannot suddenly become zero due to the presence of the inductance, and becomes the charging current ICr for charging the first capacitor Cr. At the same time, the drain voltage VQ1 of Q1, which is connected in parallel with the first capacitor Cr, gradually increases as shown by the waveform A. At this time, the rise value of the voltage is determined by the first resonance circuit including the second capacitor Cr and the primary winding L1. Here, the drain current IQ1 of Q1 becomes zero immediately at the time of turning off Q1 at time t2 due to the presence of the bypass circuit including the first capacitor Cr. This prevents the drain current IQ1 and the drain voltage VQ1 from overlapping at the time of turning off Q1, so that no switching loss occurs.

At time t2, the current ICc and the voltage VCc
Is unchanged from before. Since the charging of Cr works to discharge the parasitic capacitance C2 at the same time, the drain voltage V
Q2 tends to decrease and becomes zero at time t3.

The drain voltage VQ1 of Q1 (ie, the first
At the time when the voltage of the second capacitor Cc exceeds the sum of the voltage of the second capacitor Cc previously charged in the previous cycle and the forward voltage drop of the diode D3,
The resonance development changes to a form in which the second capacitor Cc is added. Here, the second capacitor Cc and the first capacitor C
By setting the magnitude relationship of the capacitance value with r as described above, the resonance shifts from the first resonance circuit using Cr and L1 to the operation of the second resonance circuit using Cc and L1. . In this case, the diode D3 becomes the first
After the resonance voltage due to the capacitor Cr reaches a certain value,
It works to switch from the first resonance to the second resonance. Note that the parasitic diode D2 may be used instead.

Between times t3 and t4, the exciting current IL of the primary winding L1, whose Q1 has been increased during the ON period, decreases and continues through D3 until it becomes zero, and then reverses. Most of this current is the charging current for Cc, but the charging voltage VCc hardly changes apparently because the capacity of Cc is large. Therefore, the drain voltage VQ1 of Q1 does not change like the waveform B, but has a flat voltage waveform.
This indicates that an extra voltage stress on the switching element, which is one disadvantage of the voltage resonance circuit, can be suppressed. This also shows that, taking into account the characteristics of MOSFETs that are usually easy to manufacture low on-resistance elements, the adoption of this low on-resistance element, that is, a low withstand voltage element, can reduce the switching loss at the time of switch-on. ing. As described above, the switching loss can be reduced by combining the first and second resonance circuits having different resonance conditions and using the partial voltage resonance that effectively uses only necessary parts.

Further, as is clear from the figure, when Q2 is turned on at a timing (between t3 and t4) immediately before the second capacitor Cc is changed from charging to discharging, a switching operation at zero voltage is performed. −d− (ΔT1 + ΔT
2) It is possible to control with a time ratio of / T｝.

This is a necessary condition to be realized at a fixed period (ie, a fixed frequency) in performing the output stabilization control by controlling the ON time ratio of Q1 operating as a main switching element in a combination of two resonances. Becomes These combinations show that other drawbacks of the voltage resonant circuit can be overcome, such as difficult and complicated control and inability to control at a fixed frequency.

Further, the control based on the on-time ratio,
It has an important meaning for the reset voltage of the transformer T, and shows that even if the on-time ratio is changed in a wide range in a fixed cycle, it can be applied to a wide range of input power without demagnetizing the transformer T. ing. Also, the transformers T can be easily connected in parallel.

During the ON period of Q2 from time t3 to time t5, the drain voltage VQ1 of Q1 keeps a flat state with the waveform B as described above, and the drain current IQ1 keeps zero. The current IL is equal to the value of the second capacitor Cc.
At the peak (time t4) of the resonance waveform of the second resonance circuit composed of the first winding L1 and the primary winding L1, the current becomes zero, the current ICc also changes, and the current direction thereafter reverses. That is, it becomes a discharge current from Cc and becomes an exciting current in the opposite direction for the primary winding L1. However, during this ON period, as described above, the value of the second capacitor Cc is sufficiently larger than Cr, so that the terminal voltage VCc only slightly changes. Also, during this period, the drain voltage V of Q2
Q2 remains at zero.

When Q2 is turned off at time t5, the exciting current IL in the reverse direction of the primary winding L1 due to Cc flowing through Q2.
When Q2 is turned off, the current does not suddenly become zero due to the presence of the inductance, but becomes a current for discharging the first capacitor Cr, and continues to decrease. At this time, the first capacitor Cr and the primary winding L having a short cycle are obtained from the second resonance circuit including the second capacitor Cc having a long cycle and the primary winding L1.
Then, the operation shifts to the operation of the first resonance circuit composed of the first and the second resonance circuits.
Here, when Q1 and Q2 are composed of MOSFETs as in the present embodiment, when one of the parasitic capacitances C1 and C2 is charged, the other is discharged to the other, and the equivalent circuit has a large capacitance as shown in FIG. Are connected in series via the connected Cc. Therefore, in operation, the first capacitor Cr is the parasitic capacitance C1.
If it is treated as the sum of the sum of the value and the externally added capacitor, it can be regarded as a completely equivalent phenomenon. Accordingly, zero voltage switching can be realized as in the case of turning off Q1.

Due to the resonance phenomenon of the first resonance circuit having a short period shifted when Q2 is turned off, the primary winding L1 has Q1
, A voltage in the same direction as the ON period is induced, and at the same time, the first capacitor Cr starts discharging like ICr. Therefore, at time t6, the drain voltage VQ1 of Q1 drops to zero as shown by the waveform C. At this time, by performing the switching operation by Q1, zero voltage switching can be realized. That is, since the drain current IQ1 and the drain voltage VQ1 do not overlap when Q1 is turned on, no switching loss occurs and no noise occurs.

Here, the voltage of the primary winding L1 is changed from zero to normal by resonance development (the voltage polarity during the ON period of Q1 is changed to normal,
Similarly, between times t6 and t7 when the voltage polarity during the ON period of Q2 is inverted), the secondary winding L2 of the transformer T is also normally rotated, and the resonance energy is transmitted to the secondary side. A non-zero state occurs. Where the secondary coil L
By connecting the saturable reactor SR to 2, it is possible to make the secondary side high impedance between times t6 and t7 and prevent each element of the secondary side from being included in the resonance condition, The resonance condition can be stabilized. Thus, when the DC-DC converter is used for the power supply device, zero-voltage switching can be performed more reliably in any use state, thereby reducing switching loss.

Here, as the saturable reactor SR, one having such a characteristic that it has a high inductance between the times t6 and t7 and then saturates to a low impedance is used. This is a necessary condition for reliably creating a resonance condition by the inductance of the primary winding L1. That is, since the inductance uses the primary winding itself of the transformer T, it is necessary to prevent the resonance condition from being inaccurate due to the influence of the secondary side current (load current). . This saturable reactor SR is
If the above condition is satisfied, a magnetic amplifier that detects the output voltage and controls the reset amount may be used as needed.

When MOSFETs are used as Q1 and Q2, even if the parasitic capacitance is charged, the internal short-circuit loss due to the charge can be eliminated. Note that the first capacitor Cr can be replaced with the parasitic capacitance C1 of Q1, and in this case, Cr = C1. If a capacitor C4 is used separately, in this case, Cr = C1 + C
It becomes 4.

Q1 and Q2 are ON / OFF controlled by a control circuit (not shown). Assuming that the ON time ratio of Q1 is d as described above, Q2 is {1-d- (ΔT1 + ΔT2) / T}.
Is controlled so that the on-time ratio becomes as follows. This control circuit detects the DC voltage output from the secondary terminal TO-TO 'of the transformer T, compares it with the reference voltage, and outputs a fixed-period pulse width modulated signal in accordance with the comparison result. It can be constituted by a general regulator IC or the like.

As the main switching element and the sub-switching element, the examples using the MOSFETs Q1 and Q2 have been described. However, the present invention is not limited to these, and other elements can be used as described in the text.

[0037]

As described above, according to the present invention, the first
And the second resonance circuit is combined to control the operation of each resonance circuit so as to be able to shift to each other according to the ON / OFF of the main switching element and the sub-switching element, thereby enabling zero voltage switching, By using a switching element having a low on-resistance, switching loss can be reduced even during conduction, and control by an on / off ratio can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a DC-DC converter of the present invention.

FIG. 2 is a waveform diagram illustrating a control principle of a main switching element and a sub-switching element used in the converter according to the embodiment.

FIG. 3 is a waveform diagram illustrating the operation of the present embodiment.

FIG. 4 is a circuit diagram showing a conventional converter.

FIG. 5 is a waveform chart for explaining the operation of the conventional example.

[Explanation of symbols]

 Q1 Switching element (insulated gate type FET) Q2 Sub switching element (insulated gate type FET) ES DC source L1 Primary winding Cr First capacitor Cc Second capacitor D3 Diode SR Saturable reactor

Claims (3)

(57) [Claims] 1. A DC-DC converter in which a DC source, a primary winding, and a main switching element are connected in series to a primary side of a transformer and a rectifier / smoothing circuit is connected to a secondary side of the transformer. A sub-switching element for providing a reset voltage to a transformer connected in parallel to the main switching element for controlling the condition, a first capacitor for providing one resonance condition, and a diode for switching the resonance condition; A second capacitor for providing two resonance conditions, and a saturable reactor connected to the secondary side of the transformer for stabilizing the resonance condition, wherein the first capacitor and the primary winding have a short-period resonance. A main switching element and a sub-switching element, each of which comprises a long-period resonance circuit composed of the second capacitor and the primary winding; A DC-DC converter characterized in that the operations of two types of resonance circuits are controlled so as to be able to shift to each other in accordance with the on / off state of the circuit. 2. The periods ΔT1 and ΔT2 in which the main switching element and the sub-switching element are simultaneously turned off.
When the ON time ratio of the main switching element is d and the ON time ratio of the main switching element is d, the sub switching element is controlled by the ON time ratio of {1-d- (ΔT1 + ΔT2) / T}. The DC-DC converter according to claim 1. 3. The capacity of the second capacitor is set to the first capacitor.
2. A value sufficiently larger than the capacity of the capacitor of claim 1.
A DC-DC converter as described.