JPH05102984A - Loop shape i/o data transmission equipment - Google Patents

Abstract

PURPOSE:To perform data transmission without re-registering information for the address and specification data of every slave station when they are registered in advance or the change of the address and the change and deletion of specification are performed by automatically recognizing the connecting state of the slave station. CONSTITUTION:This device is composed of a command coincidence detection memory circuit 14 which comprises a transmission signal of synchronous information, address information, and data information and command information to issue an instruction so as to check the information with respect to the slave station, and also, generates a signal in accordance with the command information, and a byte change-over switch circuit 11 which substitues input data 1 for the information with respect to the slave station by the signal outputted from the command coincidence detection memory circuit 14. Thereby, the purpose can be attained since each slave station transmits respective address and the information with respect to the connecting state of the slave station to a master station.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loop I / O data transmission device used in an automatic machine or the like.

[0002]

2. Description of the Related Art In recent years, the use of microprocessors has improved the functionality of automatic machines, and along with this, the number of sensors and actuators reaching hundreds to thousands has become uncommon.

As a result, the amount of wiring for transmitting signals between the sensors and actuators and the controller that controls them increases, resulting in a decrease in reliability and an increase in wiring man-hours, and troubles. Problems have arisen, such as difficulty in responding when they occur.

In order to solve such a problem, the present inventor has proposed in Japanese Patent Application No. 61-165830 filed previously.
Remote I / O near each sensor / actuator
We proposed a loop-shaped data transmission device in which a control unit called a "control unit" was placed and the units were connected by a transmission line using an optical fiber.

FIG. 10 is a schematic configuration diagram of the loop data transmission device. In the figure, 1 is a sensor, 2 is an actuator, 3 is an input unit, 4 is an output unit, and 3 and 4 are hereinafter referred to as slave stations. A controller 5 controls all of these slave stations, and is called a master station for the slave stations. 6 is an optical fiber.

FIG. 11 is a block diagram showing the configuration of each slave station. In the figure, reference numeral 7 is a synchronous carrier timing signal generating circuit, which generates a carrier timing signal b synchronized with the transmission speed of the received signal a. Reference numeral 8 denotes an address coincidence detection circuit which detects and stores that the address information of the signal a being received coincides with the set address. Reference numeral 9 denotes a parallel-serial converter that converts the parallel input data 1 into a serial signal c using the carrier timing signal b output from the synchronous carrier timing signal generation circuit 7 as a clock input. Reference numeral 10 is a parallel-serial converter 9 for converting the received signal a.
The serial signal delay circuit delays the serial signal c output from the same until the same timing. Reference numeral 11 denotes a transmission changeover switch, which is normally connected to the i side. If the address match detection signal d is output at the time when the reception is started and the address information passes, the transmission changeover switch 11 is connected to the h side, and thereafter the transmission signal is changed over to the serial signal c. If the address coincidence signal d is not output, the switching is not performed, and the reception signal a delayed through the signal delay circuit 10 is retransmitted as it is. Reference numeral 12 is a serial / parallel converter for converting serial / parallel conversion of the data information in the received signal a. 1
An output latch circuit 3 latches the output when the addresses match.

FIG. 12 shows a transmission format of this loop data transmission device. The transmission format consists of synchronization information for generating the synchronization carrier timing signal b, address information for distinguishing the slave station to be accessed, and data information.

The operation of the loop-shaped data transmission device configured as described above will be described below with reference to FIG.

In the figure, when the signal a is received, the synchronous carrier timing signal generation circuit 7 generates the carrier timing signal b which is synchronized with the transmission speed of the received signal a.

Here, if the address information of the signal a being received and the set address match, the address match detection circuit 8 outputs the address match signal d and the transmission changeover switch 11 is changed over from the i side to the h side. .. After that, the transmission signal g is replaced with the input data c converted into a serial signal by the parallel / serial converter. In addition, when switching transmission,
Since the received signal a is delayed by adding the carrier signal b, which is the same as the clock input signal of the parallel / serial converter 9, to the clock input of the serial signal delay circuit 10 so that the received signal a has the same timing as the serial signal c, transmission switching is performed. Waveform distortion is extremely small.

On the other hand, the parallel output of the data information of the received signal a is performed as follows. The received signal a and the carrier timing signal b are the serial input and clock input of the serial / parallel converter 12, respectively, and these serial data information are converted into parallel data. When the addresses match, the data converted in parallel by the output latch circuit 13 can be latched, and the latched parallel signal can be obtained as the output data k.

Next, the case where the addresses do not match will be described. When the addresses do not match, the transmission changeover switch 11 remains on the i side. Since the received signal a is the data input of the serial signal delay circuit and the carrier timing signal b is input as the clock input, the output signal i of the serial signal delay circuit 10 is exactly the same as the received signal a. At this time, the parallel data is neither input nor output.

[0013]

In the above-mentioned conventional loop data transmission apparatus, the address and type data of each slave station are registered in advance, and data is transmitted from the master station to the slave station based on these data information. In order to transmit the information, in the process of creating equipment such as automatic machines, when trials are repeated to obtain appropriate specifications, these information are manually re-registered in order to change the address, change the type and delete the slave station. In addition, there is a problem that the same procedure as described above has to be performed in order to grasp the connection state of input / output of each bit in each slave station.

The present invention solves the above-mentioned problems of the prior art by pre-registering the address and type data of each slave station, or re-registering these information when the address is changed, the type is changed, or deleted. It is an object of the present invention to provide a loop I / O data transmission device capable of automatically grasping the connection state of a slave station and transmitting data.

[0015]

In order to achieve the above object, a loop data transmission apparatus of the present invention commands a transmission signal to check not only synchronization information, address information and data information but also information about a slave station. It consists of command information and
Further, it is provided with a command match detection circuit for generating a signal according to the command information and a byte changeover switch circuit for replacing the information about the slave station with the input data by the signal output from the command match detection circuit.

[0016] Specifically, as information regarding the slave station, 8bi
The type of t input module and the input / output connection status of each bit such as whether or not the input / output device is connected to each bit in each slave station.

[0017]

With such a configuration, each slave station transmits information about its address and its connection state to the master station only by transmitting command information from the master station, and this information can be registered in advance. In addition, it is not necessary to re-register when changing or deleting, and information about the slave station can be easily and quickly grasped.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A loop data transmission device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a slave station of the loop data transmission apparatus of the embodiment.

In the figure, reference numeral 7 is a synchronous carrier timing signal generating circuit for generating a carrier timing signal b synchronized with the transmission speed of the received signal a. An address coincidence detection circuit 8 detects and stores that the address information of the signal being received coincides with the set address. Reference numeral 9 denotes a parallel-serial converter that converts the parallel input data into a serial signal c by using the carrier timing signal b output from the synchronous carrier timing signal generation circuit 7 as a clock input. A serial signal delay circuit 10 delays the received signal a until the same timing as the serial signal c output from the parallel / serial converter 9. Reference numeral 11 denotes a transmission changeover switch, which is normally connected to the i side. Address match detection signal d when reception is started and address information passes
If the signal is output, the transmission changeover switch 11 is connected to the h side, and thereafter the transmission signal is changed over to the serial signal c. If the address coincidence storage signal d is not output, the switching is not performed, and the reception signal delayed through the signal delay circuit 10 is retransmitted as it is. Reference numeral 12 is a serial / parallel converter for converting serial / parallel data information in the received signal.
An output latch circuit 13 latches the output when the addresses match.

The above construction is similar to that of the conventional example,
The different points are described below. FIG. 2 is a transmission format diagram of a transmission signal in this embodiment. The transmission format is composed of synchronization information for generating a synchronization carrier signal, address information for distinguishing a slave station to be accessed, command information issued for obtaining connection information of the slave station, and data information.

Further, in FIG. 1, reference numeral 14 is a command coincidence detecting circuit which issues a signal in accordance with the command information, and 15 is an encoder which codes the type of the input / output unit which is a slave station. Reference numeral 16 is a byte changeover switch circuit which replaces the information on the connection state of the slave station with the input data 1 by the signal output from the command coincidence detection circuit. Reference numeral 25 is a bit connection detection circuit that detects the input / output connection for each bit of the slave station and outputs the data m relating to the connection information.

The operation of the loop-shaped data transmission device configured as above will be described with reference to the drawings.

In the figure, when the signal a is received, the carrier timing signal b which is synchronized with the transmission speed of the received signal a is generated from the synchronous carrier timing signal generation circuit 7.

If the address information of the signal being received and the set address match, the address match detection circuit 8 outputs the address match storage signal d and the transmission changeover switch 11
Is switched from the i side to the h side. After that, the transmission signal g is replaced with the input data c converted into a serial signal by the parallel / serial converter.

Here, if the command information being received is "0", the transmission signal g is the input data c as described above, but if the command information is "1", the command match detection storage circuit 14 The command match detection signal j is output from
Input data 1 by the byte changeover switch circuit 16
Instead of, the type code output through the encoder 15 is replaced with the input data c converted into a serial signal by the parallel / serial converter 9. Therefore, the address and type data of each slave station are transmitted to the master station.

Now, a loop data transmission apparatus as shown in FIG. 3 is assumed as a concrete configuration of this embodiment. in advance,
The type code of the slave station is set as shown in FIG.

In the case of FIG. 3, the slave station 17 has the address 0,
Data such as type 3, slave station 18 has address 2 and type 3, slave station 19 has address 8, type 2, slave station 20 has address C, type 7, slave station 21 has address 9 and type 3 is stored in the data buffer 23. Will be done. Based on the stored information, the CPU 24 generates an input / output map as shown in FIG. After the input / output map is generated, the master station 22 returns the command information in the transmission signal to "0", and the CPU 3 performs the control suitable for each input / output module.

Next, when the command information being received is "2", the command match detection signal j'is output from the command match detection circuit 14, and the byte changeover switch circuit 1
6, the bit connection detection circuit 25 for detecting the input / output connection for each bit of the slave station instead of the input data l.
The connection information data m obtained by
Is replaced by the input data c converted into a serial signal by. Therefore, the connection information for each bit of each slave station is transmitted to the master station (the detection of this bit connection information will be described in detail later).

On the other hand, the parallel output of the data information of the received signal a is performed as follows. That is, the received signal a and the carrier signal b are the serial input and the clock input of the serial / parallel converter 12, respectively, and the serial data information is converted into parallel data. If the addresses match, the output latch circuit 13 latches the data converted in parallel, and the latched parallel signal can be obtained as the output data k.

Next, when the addresses do not match, as in the conventional example, the transmission changeover switch circuit 11 remains on the i side. Since the received signal a is the data input of the serial signal delay circuit 10 and the carrier timing signal b is input as the clock input, the output of the serial signal delay circuit 10 is exactly the same as the received signal a. At this time, neither parallel data is input nor output.

The specific configuration of the bit connection detection circuit 25 described above will be described below. FIG. 6 shows the first embodiment. In this embodiment, a connector 26 is provided for each bit of the Di input module attached to the slave station, and a switch mechanism 28 that is turned on when a wire 27 is connected to these connectors 26 is provided. The switch mechanism 28 corresponding to is input to the gate circuit 29 in advance,
When the command information becomes "2", the byte changeover switch circuit 16 operates by the signal j'from the command coincidence detection circuit 14.

Next, FIG. 7 shows a second circuit of the bit connection detection circuit 25.
An example of is shown. In the figure, 30 is a power supply circuit of a Do output module attached to a slave station, 31 is a current / voltage conversion amplifier that converts a driving current into a voltage, 32 is a reference value amplifier that generates a reference value of the driving current, and 33 is The output of the current / voltage conversion amplifier 31 and the reference value amplifier 32
When the drive current exceeds the reference value, O
It is a comparison amplifier which becomes N.

Reference numeral 34 is a sequence circuit for sequentially turning on the output for each bit, and 35 is this sequence circuit 34.
A latch circuit for storing the ON / OFF output of the comparison amplifier 33 for each bit in synchronism with the above, and a gate circuit 36 for controlling the output of the latch circuit 35.

The operation of the bit connection detection circuit having the above configuration will be described below. When the command information becomes “2”, the sequence circuit 34 sequentially outputs the output for each bit.
Set to N. For example, as shown in FIG.
When the Do output is connected to the 6th bit and the 7th bit, the drive current from the power supply circuit 30 changes and the output of the comparison amplifier 33 turns on only when the output of these bits is turned on ( (Figure 9). Therefore, in the latch circuit 35, 4bi
Latch data in which only the tth, 6th, and 7th bits are "1".

When the sequence circuit 34 is turned on, the bit connection information can be detected without operating the Do output destination if the rush current is allowed to flow for a short time.

The bit connection information obtained from the bit connection detection circuit 25 is transmitted to the master station and stored in the data buffer 23. Based on these pieces of information, the CPU 24 adds bit-by-bit connection information to the input / output map. After generating the input / output map, the master station returns the bit of the command information to "0", and the CPU 24 controls each input / output.

[0038]

As described above, the loop I / O of the present invention is provided.
The data transmission device is configured such that each slave station transmits the slave station address and type data, or connection information for each bit, in response to a request using command information in the transmission signal transmitted from the master station. By doing so, it is not necessary to pre-register these pieces of information or re-register when changing, and the master station can grasp the input / output information of each slave station.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a slave station of a loop I / O data transmission apparatus according to an embodiment of the present invention.

FIG. 2 is a transmission format diagram of a transmission signal of the embodiment.

FIG. 3 is a block diagram showing the overall configuration of a loop I / O data transmission device of the same embodiment.

FIG. 4 is a diagram showing a type setting example of a slave station module of the same embodiment.

FIG. 5 is a diagram showing an input / output map of a slave station of the embodiment.

FIG. 6 is a configuration diagram of a first embodiment of a bit connection detection circuit.

FIG. 7 is a configuration diagram of a second embodiment of a bit connection detection circuit.

FIG. 8 is a diagram showing a bit connection state.

FIG. 9 is an output diagram of the comparison output amplifier in the case of FIG.

FIG. 10 is a schematic configuration diagram of a conventional loop data transmission device.

FIG. 11 is a block diagram of a slave station of a conventional loop data transmission device.

FIG. 12 is a format diagram of a transmission signal of a conventional loop data transmission device.

[Explanation of symbols]

 7 Synchronous carrier timing signal generation circuit 8 Address match detection circuit 9 Parallel / serial converter 11 Transmission changeover switch circuit 14 Command match detection circuit 16 byte changeover switch circuit 25 bit connection detection circuit a Received signal b Carrier timing signal d Address match detection signal j, j'command match detection signal

Claims (3)

[Claims] 1. A transmission signal transmitted from the master station, which comprises a plurality of slave stations, which are an input unit and an output unit, and a master station which controls these slave stations via a transmission signal, connected in a loop. Consists of synchronization information, address information, command information relating to an instruction for checking information about the slave station, and data information for control, and whether the slave station has the same address information as the preset address. An address match detection circuit that outputs an address match signal when it detects and matches, a command match detection circuit that outputs a signal according to the command information, and the child according to the signal output from the command match detection circuit. A byte switching switch that selectively outputs from the data related to the station type and the input data from the device connected to the slave station and outputs it. Switch circuit, a synchronous carrier timing signal generating circuit for generating a carrier timing signal synchronized with the transmission speed of the transmission signal, and the byte switching switch as a timing for taking in the carrier timing signal output from the carrier timing signal generating circuit. A parallel / serial converter that converts a parallel signal output from the circuit into a serial signal, and data information in the transmission signal that is converted by the parallel / serial converter by the address match signal output from the address match detection circuit. And a transmission changeover switch circuit for replacing the serial signal. 2. A transmission signal transmitted from the master station by connecting a plurality of slave stations, which are an input unit and an output unit, and a master station, which controls these slave stations via a transmission signal, in a loop shape. Is composed of synchronization information, address information, command information related to an instruction for checking information about the slave station, and data information for control, and whether or not the slave station matches the address information with a preset address. , An address match detection circuit that outputs an address match signal when they match, a bit connection detection circuit that detects the bit-by-bit input / output connection of the slave station and outputs data related to the bit connection, and the command information A command match detection circuit that outputs a signal corresponding to the command connection detection circuit, and a bit connection detection circuit that responds to the signal output from the command match detection circuit. A byte switching switch circuit for selectively switching between output data relating to bit connection and input data from a device connected to a slave station, and generating a carrier timing signal synchronized with the transmission speed of the transmission signal. A synchronous carrier timing signal generation circuit, and a parallel / serial converter that converts a parallel signal output from the byte changeover switch circuit into a serial signal, using the carrier timing signal output from the carrier timing signal generation circuit as a capture timing, A loop shape comprising a transmission changeover switch circuit for replacing the data information in the transmission signal with the serial signal converted by the parallel / serial converter by the address match signal output from the address match detection circuit. I / O data transmission device. 3. A transmission signal transmitted from the master station by connecting a plurality of slave stations, which are an input unit and an output unit, and a master station, which controls these slave stations via a transmission signal, in a loop shape. Is composed of synchronization information, address information, command information related to an instruction for checking information about the slave station, and data information for control, and whether or not the slave station matches the address information with a preset address. , An address match detection circuit that outputs an address match signal when they match, a bit connection detection circuit that detects the bit-by-bit input / output connection of the slave station and outputs data related to the bit connection, and the command information And a command match detection circuit that outputs a signal according to the command match detection circuit according to the signal output from the command match detection circuit. Data, a byte connection switch circuit for selectively outputting the bit connection data output from the bit connection detection circuit and input data from a device connected to the slave station, and a transmission speed of the transmission signal. A synchronous carrier timing signal generating circuit for generating a carrier timing signal synchronized with the carrier timing signal generating circuit, and a carrier timing signal output from the carrier timing signal generating circuit as a fetch timing, and a parallel signal output from the byte changeover switch circuit into a serial signal. A parallel / serial converter for conversion, and a transmission changeover switch circuit for replacing the data information in the transmission signal with the serial signal converted by the parallel / serial converter by the address match signal output from the address match detection circuit. Lou equipped with Jo I / O data transmission device.