JP2570936B2 - Digital data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data transfer device.

[0002]

2. Description of the Related Art In transferring digital data between various devices that handle digital data, an information signal indicating that digital data can be transferred from a receiving side to a transmitting side is sent, and the transmitting side is accordingly sent. In general, digital data is transferred to the receiving side.

[0003]

By the way, as described above, the information signal indicating that digital data can be transferred from the receiving side to the transmitting side is sent, and the digital data is transferred from the transmitting side to the receiving side accordingly. Instead of transmitting the digital data being transferred and the transmission data latch clock signal generated for each predetermined data amount of the digital data from the transmission side to the reception side at a predetermined transfer rate, The receiving side transfers the received digital data from the data latch circuit to the parallel-to-serial signal conversion circuit at the timing of the serial load clock signal, takes out the digital data from the parallel-to-serial signal conversion circuit, and transmits and receives the digital data. Digital data transfer device, that is, one side from the transmitting side without checking the state of the receiving side A digital data transfer device in which digital data transfer is performed has been considered, but in such a digital data transfer device, digital data received on the receiving side is transferred from a data latch circuit to a parallel / serial signal conversion circuit. The problem is that an error occurs in digital data when a state occurs in which the digital data transferred from the transmission side is taken into the data latch circuit by the data latch clock signal at the timing of shifting with the timing of the serial load clock signal. And a solution was sought.

[0004]

According to the present invention, a digital data to be transferred and a transmission data latch clock signal generated for each predetermined data amount of the digital data are transferred in a predetermined manner. The data is transmitted from the transmitting side to the receiving side at a speed, and the receiving side transfers the received digital data from the data latch circuit to the parallel-to-serial signal conversion circuit at the timing of the serial load clock signal, and extracts the digital data from the parallel-to-serial signal conversion circuit as digital data. In a digital data transfer device configured to transmit and receive data, a time position of a transmission data latch clock signal transmitted from a transmission side to a reception side and a time position of a serial load clock signal generated on the reception side are described. A time position detecting means for detecting a coincidence state, and digital data transmitted from the transmitting side to the receiving side. Signal switching means for switching between delayed digital data in a state where a predetermined time delay is given and digital data in a state where the time delay is not given so that the digital data can be supplied to a receiving side; The delayed digital data is selected by the output signal from the detecting means and supplied to the receiving side, and the time corresponding to the time delay is longer than the transmission data latch clock signal transmitted from the transmitting side. Means for providing a data latch clock signal to the data latch circuit with only a time delay, a digital data to be transferred, and a predetermined data amount of the digital data. The transmission data latch clock signal generated every time is transmitted from the transmission side to the reception side at a predetermined transfer rate. The digital data is transmitted as a real signal, and the received digital data is transferred from the data latch circuit to the parallel-to-serial signal conversion circuit at the timing of the serial load clock signal, taken out as digital data from the parallel-to-serial signal conversion circuit, and digital data is transmitted and received. In the digital data transfer apparatus, the coincidence state between the time position of the transmission data latch clock signal transmitted from the transmission side to the reception side and the time position of the serial load clock signal generated on the reception side is detected. The time position detecting means, the delayed digital data in a state where a predetermined time delay is given to the digital data transmitted from the transmitting side to the receiving side by the output signal from the time position detecting means, and the time delay It is possible to switch between digital data that is not given and supply it to the receiving side. Digital data switching means, and means for providing to the data latch circuit a data latch clock signal that has been delayed by a time corresponding to the time delay from the transmission data latch clock signal transmitted from the transmission side. And a digital data transfer device comprising:

[0005]

The digital data to be transferred and the transmission data latch clock signal generated for each predetermined data amount of the digital data are transmitted from the transmission side to the reception side at a predetermined transfer rate. Transmit. Generates delayed digital data in a state where a predetermined time delay is given to the digital data transmitted from the transmitting side to the receiving side, and receives the digital data in a state in which the time delay is not applied by switching the digital data with a signal switching means. Be able to supply to the side. On the receiving side, the time position of the transmission data latch clock signal transmitted from the transmitting side and the time position of the serial load clock signal generated on the receiving side are detected by a time position detecting means for detecting a coincidence state between the two. When the coincidence of the time position is detected, the delay digital data is selected and supplied to the data latch circuit on the receiving side so that the time delay is longer than the transmission data latch clock signal transmitted from the transmitting side. Is applied to the data latch circuit. The received digital data is transferred from the data latch circuit to the parallel / serial signal conversion circuit at the timing of the serial load clock signal, and is taken out as digital data from the parallel / serial signal conversion circuit.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a digital data transfer apparatus according to the present invention. FIG.
2 is a block diagram showing a schematic configuration of the digital data transfer device of the present invention, FIG. 3 is a waveform diagram for explaining the operation of the digital data transfer device of the present invention shown in FIG. 1, and FIG. FIG. 4 is a waveform chart for explaining the operation of the digital data transfer device of the present invention shown in FIG. In the digital data transfer apparatus of the present invention shown in FIGS. 1 and 2, 1 indicates equipment on the transmitting side, and 2 indicates equipment on the receiving side. Transmission digital data {see FIGS. 3 (a) and 4 (a)} to be transmitted from the transmission-side equipment 1 is transmitted to the reception side via the transmission line 3 as a serial signal. , The serial clock signal {of FIG.
4 (b) and FIG. 4 (b)} are transmitted over the transmission line 4, and the transmission data latch clock signal {FIG.
(C) and (c) of FIG. 4} are transmitted to the receiving side by the transmission line 5. In the equipment 2 on the receiving side, 2A is a data processing unit, and 2B is a control unit.

First, in the digital signal transfer device shown in FIG. 1, digital data (transmitted digital data) transmitted to the receiving side via the transmission line 3 is supplied to a fixed contact a of the signal changeover switch 7 and Delay circuit 6
After a predetermined time delay, the signal is supplied to the fixed contact b of the signal changeover switch 7. As the delay circuit 6 shown in FIG. 1, for example, a shift register that performs a shift operation using a serial clock signal transmitted from the transmission side via the transmission line 4 as a shift pulse may be used. The digital data transmitted from the movable contact v of the signal changeover switch 7 is supplied to the serial-parallel signal conversion circuit 9. The serial-parallel signal conversion circuit 9 is also transmitted from the transmission side by, for example, the transmission line 4. A shift register that performs a shift operation using a serial clock signal as a shift pulse may be used. In the following description, it is assumed that both the delay circuit 6 and the serial-parallel signal conversion circuit 9 are 8-bit shift registers.

The digital data of a predetermined number of bits (8 bits in the digital data illustrated in FIG. 3) output from the serial-parallel signal conversion circuit 9 is transmitted to a data latch circuit 12 connected by a transmission line 10. On the other hand, when the data latch clock signal {see FIG. 3F} is supplied from the control unit 2B of the equipment 2 on the receiving side by the transmission line 11, the data is latched by the data latch circuit 12. The digital data latched by the data latch circuit 12 is transmitted to a parallel-to-serial signal conversion circuit 14 connected to the output side of the data latch circuit 12 by a transmission line 13 and transmitted to a data processing unit of a reception-side facility. When the serial load clock signal {see FIG. 3 (g)} is supplied from 2A via the transmission line 15, it is taken into the parallel / serial signal conversion circuit 14. The digital data captured by the parallel-to-serial signal conversion circuit 14 as described above is converted into a parallel-to-serial signal conversion circuit by the reception-side serial clock signal supplied via the transmission line 16 from the data processing unit 2A of the reception-side equipment. The data is transmitted from the transmission line 14 to the data processing unit 2A of the equipment on the receiving side via the transmission line 17.

In the digital data transfer apparatus shown in FIG. 1, the transfer rate of digital data transmitted from the equipment 1 on the transmission side to the reception side is predetermined. For each predetermined data amount (8 bits in the illustrated example) of digital data transmitted from the equipment 1 on the transmission side to the reception side, the transmission side transmits the transmission line 5 to the reception side for transmission to the reception side in FIG. The transmission data latch clock signal having a predetermined period is transmitted as shown in FIG. On the other hand, in the equipment 2 on the receiving side, the data latch circuit 12 is transmitted from the control unit 2B thereof through the transmission line 11.
, A data latch clock signal {see FIG. 3 (f)} is supplied thereto, and the data control unit 2B sends a serial load clock signal to the parallel / serial signal conversion circuit 14 via the transmission line 15. {See FIG. 3 (g)}, the data latch clock signal {see FIG. 3 (f)} and the serial load clock signal {FIG. Of the transmission data latch clock transmitted from the transmission side to the reception side for each predetermined amount of digital data transmitted from the transmission side equipment 1 to the reception side. It has the same period as the period of the signal. The serial clock signal transmitted from the transmission-side equipment 1 to the transmission line 4 and the reception-side signal transmitted from the data processing unit 2A of the reception-side equipment 2 to the parallel-to-serial signal conversion circuit 14 via the transmission line 16 When the cycle of the serial clock signal is Tt and the cycle of the reception-side serial clock signal is Tr, the cycle of the two signals is set so that Tr ≦ Tt. It is necessary.

In the digital data transfer circuit shown in FIG. 1, the relationship between the cycle of various signals transmitted from the equipment 1 on the transmission side to the reception side and the cycle of various signals generated in the equipment 2 on the reception side Is predetermined as described above,
The various signals transmitted from the transmission-side equipment 1 to the reception side and the various signals generated by the reception-side equipment 2 are signals generated independently of each other. The phase relationship between various signals transmitted from the first facility 1 to the receiving side and various signals generated by the second facility on the receiving side depends on the timing of turning on the power at the first facility on the transmitting side and the timing at the first facility on the receiving side. It is determined by the power-on timing, and is not always kept in a fixed relation.

For this purpose, the transmission data latch clock signal shown in FIG. 3C transmitted from the transmission-side equipment 1 shown at the time position of time t1 in FIG. The receiving-side serial load clock signal of FIG. 3 (g) transmitted from the processing unit 2A is shown in FIG.
It can happen that they occur simultaneously as exemplified in FIG. Then, the transmission data latch clock signal of FIG. 3C transmitted from the equipment 1 on the transmission side,
In the case where the receiving-side serial load clock signal of FIG. 3G transmitted from the data processing unit of the receiving-side facility 2 is simultaneously generated as shown at time t1 in FIG. As described above, the data processing unit 2A in the equipment 2 on the receiving side cannot take in digital data from the parallel / serial signal conversion circuit 14 in a good state, as described above.

Therefore, in the digital data transfer apparatus shown in FIG. 1, in order to prevent the above-mentioned problem from occurring, the control unit 2B of the equipment 2 on the receiving side transmits the data transmitted from the equipment 1 on the transmitting side. 3 (c) coincides with the time position of the receiving-side serial load clock signal of FIG. 3 (g) transmitted from the data processing unit 2A in the equipment 2 on the receiving side. A state is detected by a time position detecting means, and a digital signal switching signal generated when the time position matching state of the two signals is detected by the time position detecting means is transmitted to a switching control signal via a line 8. Is supplied to the signal changeover switch 7 so that the transmission digital data transmitted from the transmission side by the transmission line 3 is generated by delaying the transmission digital data by the delay circuit 6. The selected digital data is selected by the signal changeover switch 7 and supplied to the data latch circuit 12 on the receiving side via the serial / parallel signal conversion circuit 9 so that the transmission data transmitted from the transmitting side is transmitted. The data latch circuit 12 is provided with a data latch clock signal which is delayed by a time corresponding to the above-mentioned time delay from the latch clock signal to the data latch circuit 12 and the received digital data is transmitted from the data latch circuit 12 to the parallel / serial signal conversion circuit 14. In this case, the data is transferred at the timing of the serial load clock signal, and the digital data is taken in from the parallel / serial signal conversion circuit 14 to the data processing unit 2A in the equipment 2 on the receiving side so that the above-described problem does not occur. It is.

FIG. 3 is a waveform diagram showing the operation of each unit of the digital data transfer apparatus shown in FIG. 1. The transmission digital data transmitted from the transmission side to the reception side via the transmission line 3 is 8 bits. This is for digital data having a bit (1 byte) configuration. Further, in the example shown in FIG. 3, the transmission digital data is such that after transmitting digital data of 1 byte configuration in a period of 8 sampling periods, there is a non-signal period in a period of 8 sampling periods. 4 shows a case where digital data is transmitted in an embodiment. In the embodiment of the present invention, it is not necessary to provide a non-signal period between transmission digital data. Now, in the digital data transfer device shown in FIG. 1, the control unit 2B of the equipment 2 on the receiving side sets the time of the transmission data latch clock signal of FIG. As a result of detecting the coincidence state between the position and the time position of the receiving side serial load clock signal transmitted from the data processing unit 2A in the equipment 2 on the receiving side by the time position detecting means,
If the two signals are not generated at the same time position, the data processing unit 2A in the equipment 2 on the receiving side sends the signal to the line 8
The digital signal switching signal supplied to the signal changeover switch 7 through the switch switches the movable contact v of the changeover switch 7 to the fixed contact side a, and transmits the transmission digital data transmitted by the transmission line 3 from the transmission side. It is applied to a serial / parallel signal conversion circuit 9 comprising an 8-bit shift register.

In the digital data transfer apparatus shown in FIG. 1, the control unit 2B of the equipment 2 on the receiving side includes:
The time position of the transmission data latch clock signal shown in FIG. 3C transmitted from the equipment 1 on the transmission side and the serial number on the reception side shown in FIG. 3G transmitted from the data processing unit 2A in the equipment 2 on the reception side. As a result of detecting the coincidence state between the load clock signal and the time position by the time position detecting means, if the two signals are generated at the same time position, the line is sent from the data processing unit 2A in the equipment 2 on the receiving side. The digital signal switching signal supplied to the signal changeover switch 7 via the switch 8 changes the movable contact v of the changeover switch 7 to the fixed contact side b side, and the transmission digital data transmitted by the transmission line 3 from the transmission side. Is supplied to a serial-parallel signal conversion circuit 9 by the delay digital data obtained by delaying the digital data.

As described above, the movable contact v of the changeover switch 7
Are switched to the fixed contact a side depending on the time position of the transmission data latch clock signal shown in FIG. 3C transmitted from the equipment 1 on the transmitting side and the data processing unit 2A in the equipment 2 on the receiving side. This is the case where the time position of the received serial load clock signal on the receiving side does not match the time position. In this case, the serial / parallel signal conversion comprising an 8-bit shift register via the movable contact v of the changeover switch 7 is performed. When the 8-bit digital data is completely supplied to the circuit 9, the data latch clock signal generated by the control unit 2B of the equipment 2 on the receiving side, that is, the data latch clock signal transmitted from the transmitting side to the receiving side via the transmission line 5 is transmitted. The control unit 2 of the equipment 2 on the receiving side based on the incoming transmission data latch clock signal.
When the data latch clock signal generated at B is supplied to the data latch circuit 12 via the line 11,
The data latch clock signal is used for the data latch circuit 1
2, the 8-bit signal of the serial-parallel signal conversion circuit 9 is latched by the data latch circuit 12 via the transmission line 10.

The state in which the movable contact v of the changeover switch 7 is switched to the fixed contact b side as described above corresponds to the transmission data latch clock signal shown in FIG. And the time position of the receiving-side serial load clock signal transmitted from the data processing unit 2A in the equipment 2 on the receiving side coincides with each other. Delayed digital data obtained by delaying the transmitted transmission digital data by a delay circuit 6 composed of an 8-bit shift register is supplied to a serial / parallel signal conversion circuit 9 via the movable contact v of the changeover switch 7 described above. In this case, when the 8-bit digital data has been supplied to the serial-parallel signal conversion circuit 9 composed of an 8-bit shift register, the data latch clock signal generated by the control unit 2B of the equipment 2 on the receiving side is completed. That is, the transmission data latch clock signal transmitted from the transmission side to the reception side via the transmission line 5 is converted into a time corresponding to the delay time of the delay circuit 6 by the control unit 2B of the equipment 2 on the reception side. The data latch clock signal in a state delayed by only the data latch circuit 12 is supplied to the data latch circuit 12 via the line 11, so that when the data latch clock signal is supplied to the data latch circuit 12, the serial-parallel signal conversion is performed. The 8-bit signal of the circuit 9 is latched by the data latch circuit 12 via the transmission line 10. This state is shown by the portion at time t2 in FIG.

In the above example, the time delay given to the transmission digital data by the delay circuit 6 is a time value in which the digital data having the same number of bits as the 8 bits of the serial-parallel signal conversion circuit 9 are arranged on the time axis, that is, Although the sampling period is assumed to be eight, the time delay provided to the transmission digital data by the delay circuit 6 may be one or more sampling periods. As is clear from the above description, in the digital data transfer device shown in FIG. 1, the transmission device 1 shown in FIG.
3. The time position of the transmission data latch clock signal of FIG.
(G) As a result of the time position detecting means detecting the coincidence state of the reception side serial load clock signal with the time position, if the two signals are generated at the same time position, the delay circuit 6 By providing transmission digital data with a delay to the receiving side,
The digital data received on the receiving side is stored in the data latch circuit 1
Since the digital data transferred from the transmission side can be prevented from being taken into the data latch circuit 12 by the data latch clock signal at the timing of transferring the data from the transmitter 2 to the parallel / serial signal conversion circuit 14 at the timing of the serial load clock signal, it can be avoided. It is clear that the conventional problems can be solved.

Next, the digital signal transfer device shown in FIG. 2 will be described. In the digital signal transfer device shown in FIG. 2, digital data (transmitted digital data) transmitted to the receiving side via the transmission line 3 is supplied to a serial / parallel signal conversion circuit 18. As the serial-parallel signal conversion circuit 18, for example, a shift register that performs a shift operation using a serial clock signal transmitted from the transmission side via the transmission line 4 as a shift pulse may be used. The parallel output signal output from the serial / parallel signal conversion circuit 18 is transmitted via the transmission line 21 to the data switching circuit 2.
3, and the digital data of the serial signal that has passed through the serial / parallel signal conversion circuit 18 is supplied to a serial / parallel signal conversion circuit 20 via a transmission line 19. As the serial-parallel signal conversion circuit 20 described above, for example, a shift register that performs a shift operation using a serial clock signal transmitted from the transmission side via the transmission line 4 as a shift pulse may be used. The parallel output signal output from the serial / parallel signal conversion circuit 20 is supplied to the data switching circuit 23 via the transmission line 22.

Digital data of a predetermined number of bits (8 bits in the digital data illustrated in FIG. 4) output from the serial-parallel signal conversion circuit 18 is supplied via a transmission line 21 and is also serial-parallel. A predetermined number of bits (8 bits in the digital data illustrated in FIG. 4) output from the signal conversion circuit 20 are transmitted to the transmission line 22.
The data switching circuit 23 supplied via the transmission line 21 from the serial-parallel signal conversion circuit 18 according to the digital data switching signal supplied via the line 24 from the control unit 2B in the equipment 2 on the receiving side. Either digital data supplied through the transmission line 10 or digital data supplied through the transmission line 22 from the serial / parallel signal conversion circuit 20 to the data latch circuit 12 via the transmission line 10. A signal switching operation for supplying the signal is performed.

Data latch circuit 1 to which digital data is supplied from data switching circuit 23 via transmission line 10
2, the data latch clock signal {in FIG.
(f) is latched at the time when {} is supplied. The digital data latched by the data latch circuit 12 is transmitted to a parallel-to-serial signal conversion circuit 14 connected to the output side of the data latch circuit 12 by a transmission line 13 and transmitted to a data processing unit of a reception-side facility. When the receiving side serial load clock signal {see FIG. 4 (g)} is supplied from 2A via the transmission line 15, it is taken into the parallel / serial signal conversion circuit 14. The digital data captured by the parallel-to-serial signal conversion circuit 14 as described above is converted into a parallel-to-serial signal conversion circuit by the reception-side serial clock signal supplied via the transmission line 16 from the data processing unit 2A of the reception-side equipment. The data is transmitted from the transmission line 14 to the data processing unit 2A of the equipment on the receiving side via the transmission line 17.

In the digital data transfer apparatus shown in FIG. 2, the transfer rate of digital data transmitted from the equipment 1 on the transmission side to the reception side is determined in advance. 4C from the transmission side to the reception side by the transmission line 5 for each predetermined data amount (8 bits in the illustrated example) of the digital data transmitted from the equipment 1 on the transmission side to the reception side. The transmission data latch clock signal having a predetermined period is transmitted as shown in FIG. On the other hand, in the equipment 2 on the receiving side, the data latch circuit 12 is transmitted from the control unit 2B thereof through the transmission line 11.
, A data latch clock signal {see FIG. 4 (f)} is supplied thereto, and the data control unit 2B supplies a serial load clock signal to the parallel / serial signal conversion circuit 14 via the transmission line 15. {See FIG. 4 (g)}, the data latch clock signal {see FIG. 4 (f)} and the serial load clock signal {FIG. Of the transmission data latch clock transmitted from the transmission side to the reception side for each predetermined amount of digital data transmitted from the transmission side equipment 1 to the reception side. It has the same period as the period of the signal. The serial clock signal transmitted from the transmission-side equipment 1 to the transmission line 4 and the reception-side signal transmitted from the data processing unit 2A of the reception-side equipment 2 to the parallel-to-serial signal conversion circuit 14 via the transmission line 16 When the cycle of the serial clock signal is Tt and the cycle of the reception-side serial clock signal is Tr, the cycle of the two signals is set so that Tr ≦ Tt. It is necessary.

In the digital data transfer circuit shown in FIG. 2, similarly to the case of the digital data transfer circuit described with reference to FIG. 1, the period of various signals transmitted from the equipment 1 on the transmission side to the reception side is determined. The relationship between the cycle of various signals generated in the equipment 2 on the receiving side is predetermined as described above, but the various signals transmitted from the equipment 1 on the transmitting side to the receiving side, Since the various signals generated by the equipment 2 on the receiving side are signals generated independently of each other, the various signals transmitted from the equipment 1 on the transmitting side to the receiving side and the equipment on the receiving side The phase relationship between the various signals generated in 2 is determined by the power-on timing in the equipment 1 on the transmitting side and the power-on timing in the equipment on the receiving side, and is always kept in a constant relation. What you are doing .

For this purpose, the transmission data latch clock signal shown in FIG. 4C transmitted from the transmission side equipment 1 shown at the time position of time t1 in FIG. The receiving side serial load clock signal shown in (g) of FIG. 4 and transmitted from the data processing unit 2A in the facility 2 may be simultaneously generated as illustrated in FIG. It can happen. And
The transmission data latch clock signal of FIG. 4C transmitted from the transmission-side equipment 1 and the reception-side serial load clock signal of FIG. 4G transmitted from the data processing unit of the reception-side equipment 2 Are simultaneously occurring as shown at time t1 in FIG. 4, the data processing unit 2A in the equipment 2 on the receiving side sets the parallel-serial signal conversion circuit 1
4, the above-mentioned problem occurs that digital data cannot be taken in a good state.

Therefore, in the digital data transfer apparatus shown in FIG. 2, in order to prevent the above-mentioned problem from occurring, the control unit 2B of the equipment 2 on the reception side transmits the data transmitted from the equipment 1 on the transmission side. 4 (c) coincides with the time position of the receiving side serial load clock signal of FIG. 4 (g) transmitted from the data processing unit 2A of the equipment 2 on the receiving side. The state is detected by the time position detecting means, and the reception side equipment 2 is operated in accordance with the signal output from the time position detecting means in accordance with the state of whether or not the time positions of the two signals match with each other. The digital data switching signal generated by the control unit 2B is used as a switching control signal via a line 24 as a data switching circuit 23.
The digital data to be supplied from the data switching circuit 23 to the data latch circuit 12 via the transmission line 10 is transmitted from the serial / parallel signal conversion circuit 18 to the transmission line 2.
1 or to the digital data supplied to the data switching circuit 23 via the transmission line 21 from the serial / parallel signal conversion circuit 18 described above. On the other hand, the data is switched from the serial / parallel signal conversion circuit 20 that outputs the delayed digital data with a time delay to the digital data supplied to the data switching circuit 23 via the transmission line 22. .

The transmission digital data transmitted from the transmission side via the transmission line 3 is converted into a parallel signal by the serial / parallel signal conversion circuit 18 and is converted into a parallel signal by the serial / parallel signal conversion circuit 18. The data switching circuit 23 switches and selects the delayed digital data converted to a parallel signal by the serial-parallel signal conversion circuit 20 having a longer time delay than the converted digital data, and the data latch on the receiving side. The data latch clock signal is supplied to the circuit 12 and the data latch clock signal, which is given a time delay corresponding to the above-mentioned time delay from the transmission data latch clock signal transmitted from the transmission side, is applied to the data latch circuit 12. The received digital data is serial-lowered from the data latch circuit 12 to the parallel / serial signal conversion circuit 14. Transfer at the timing of the clock signal,
By taking in digital data from the parallel-to-serial signal conversion circuit 14 into the data processing unit 2A in the equipment 2 on the receiving side, the above-described problem does not occur.

FIG. 4 is a waveform diagram showing the operation of each unit of the digital data transfer apparatus shown in FIG. 2. The transmission digital data transmitted from the transmission side to the reception side via the transmission line 3 is 8 bits. This is for digital data having a bit (1 byte) configuration. In addition, in the example shown in FIG. 4, the transmission digital data is such that after transmitting digital data of 1 byte configuration in a period of 8 sampling periods, there is a non-signal period in a period of 8 sampling periods. 4 shows a case where digital data is transmitted in an embodiment. In the embodiment of the present invention, it is not necessary to provide a non-signal period between transmission digital data. Now, in the digital data transfer device shown in FIG. 2, the control unit 2B of the equipment 2 on the receiving side sets the time of the transmission data latch clock signal of FIG. As a result of detecting the coincidence state between the position and the time position of the receiving side serial load clock signal transmitted from the data processing unit 2A in the equipment 2 on the receiving side by the time position detecting means,
If the two signals do not occur at the same time position, the data processing unit 2A in the equipment 2 on the receiving side sends the signal to the line 2
4, the switching operation of the data switching circuit 23 by the digital data switching signal supplied to the data switching circuit 23 via the line 4 causes the digital data supplied to the data switching circuit 23 from the serial / parallel signal conversion circuit 18 via the transmission line 21. Is supplied to the data latch circuit 12 via the transmission line 10. In this case, the data latch clock signal generated by the control unit 2B of the equipment 2 on the receiving side based on the transmission data latch clock signal transmitted from the transmitting side to the receiving side via the transmission line 5 When the data latch clock signal is supplied to the data latch circuit 12, the data is output from the serial-parallel signal conversion circuit 18 and is transmitted to the data latch circuit 12 via the transmission line 21. 8 provided to the switching circuit 23
Bit digital data is latched by the data latch circuit 12 via the transmission line 10.

In the digital data transfer apparatus shown in FIG. 2, the control unit 2B of the equipment 2 on the receiving side includes:
The time position of the transmission data latch clock signal shown in (c) of FIG. 4 transmitted from the equipment 1 on the transmitting side and the serial number on the receiving side shown in (g) of FIG. As a result of detecting the coincidence state between the load clock signal and the time position by the time position detecting means, if the two signals are generated at the same time position, the line is sent from the data processing unit 2A in the equipment 2 on the receiving side. The switching operation of the data switching circuit 23 based on the digital data switching signal supplied to the data switching circuit 23 via the transmission line 24 causes the digital data supplied from the serial / parallel signal conversion circuit 20 to the data switching circuit 23 via the transmission line 22 to be transmitted. Is transmission line 1
0 to the data latch circuit 12. In this case, the transmission data latch clock signal transmitted from the transmission side to the reception side via the transmission line 5 is
The data latch clock signal in a state delayed by a time corresponding to the delay time generated in the digital data by the serial / parallel signal conversion circuit 18 in the control unit 2B of the equipment 2 on the receiving side is supplied via the line 11 to the data latch circuit. When the data latch clock signal is supplied to the data latch circuit 12, the data latch clock signal is output from the serial / parallel signal conversion circuit 20 and supplied to the data switching circuit 23 via the transmission line 21. The 8-bit digital data is latched by the data latch circuit 12 via the transmission line 10.

As is clear from the above description, FIG.
In the digital data transfer apparatus shown in FIG. 4, as in the case of the digital data transfer apparatus described with reference to FIG. 1, the transmission data shown in FIG. The time position detecting means detects a coincidence state between the time position of the latch clock signal and the time position of the receiving side serial load clock signal of FIG. 4 (g) sent from the data processing unit 2A of the equipment 2 on the receiving side. As a result, when both signals are generated at the same time position, transmission digital data with a time delay given by passing through the serial / parallel signal conversion circuit 18 is supplied to the receiving side. At the timing when the digital data received on the receiving side is transferred from the data latch circuit 12 to the parallel / serial signal conversion circuit 14 at the timing of the serial load clock signal. Digital data transferred from is as it can be avoided state as captured in the data latch circuit 12 by the data latch clock signal, it can solve the conventional problems are apparent.

[0029]

As apparent from the above description, in the digital data transfer apparatus of the present invention, the digital data to be transferred and the digital data are generated for each predetermined data amount. When the transmitted data latch clock signal is transmitted from the transmission side to the reception side at a predetermined transfer rate, a predetermined time delay is given to digital data transmitted from the transmission side to the reception side. State digital data is generated, and the digital data without the time delay is switched by signal switching means so that the digital data can be supplied to the receiving side. On the receiving side, the transmission transmitted from the transmitting side is performed. Time position detection for detecting the coincidence between the time position of the data latch clock signal and the time position of the serial load clock signal generated on the receiving side By the step, if a match of the time position of the two described above is detected, to be supplied to the data latch circuit on the receiving side selects a delay digital data,
A data latch clock signal that has been subjected to a time delay corresponding to the above time delay from the transmission data latch clock signal transmitted from the transmission side is applied to the data latch circuit, and the received digital data is transmitted to the serial load clock. Since the data is transferred from the data latch circuit to the parallel-serial signal conversion circuit at the timing of the signal and is taken out as digital data from the parallel-serial signal conversion circuit, the digital data transfer device of the present invention transmits the digital data from the equipment on the transmission side. As a result of detecting the coincidence state between the time position of the transmitted data latch clock signal and the time position of the receiving side serial load clock signal transmitted from the data processing unit in the receiving side equipment by the time position detecting means, Given both signals occurring at the same time position, a predetermined time delay is given Since the transmission digital data is supplied to the reception side, the digital data received at the reception side is transferred from the data latch circuit to the parallel / serial signal conversion circuit at the timing of the serial load clock signal at the timing of being transferred from the transmission side. This prevents a state in which digital data is taken into the data latch circuit by the data latch clock signal, and according to the present invention, conventional problems can be solved satisfactorily.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a digital data transfer device of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of a digital data transfer device according to the present invention.

FIG. 3 is a waveform chart for explaining the operation of the digital data transfer device of the present invention shown in FIG.

FIG. 4 is a waveform chart for explaining the operation of the digital data transfer device of the present invention shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transmission-side equipment, 2 ... Reception-side equipment, 2A ... Data processing part, 2B ... Control part, 6 ... Delay circuit, 7 ... Signal changeover switch, 9, 18-20 ... Serial-parallel signal conversion circuit, 12 ... Data latch circuit, 14: parallel / serial signal conversion circuit, 23: data switching circuit,

Claims (2)

(57) [Claims] 1. A method according to claim 1, wherein the digital data to be transferred and a transmission data latch clock signal generated for each predetermined amount of the digital data are transmitted from a transmission side to a reception side at a predetermined transfer rate. The receiving side transfers the received digital data from the data latch circuit to the parallel-to-serial signal conversion circuit at the timing of the serial load clock signal, extracts the digital data from the parallel-to-serial signal conversion circuit, and transmits and receives the digital data. In the digital data transfer apparatus described above, a time position for detecting a coincidence state between the time position of the transmission data latch clock signal transmitted from the transmission side to the reception side and the time position of the serial load clock signal generated on the reception side. A predetermined time delay is given to the digital data transmitted from the transmitting side to the receiving side by the detecting means. Signal switching means for switching between the delayed digital data in the given state and the digital data in the state where the time delay is not given so that the digital data can be supplied to the receiving side, and the output signal from the time position detecting means. The delayed digital data is selected and supplied to the receiving side, and a time delay corresponding to the time delay is applied to the transmission data latch clock signal transmitted from the transmitting side. Means for providing a data latch clock signal to a data latch circuit. 2. The method according to claim 1, wherein the digital data to be transferred and a transmission data latch clock signal generated for each predetermined amount of the digital data are transmitted from a transmission side to a reception side at a predetermined transfer rate. The receiving side transfers the received digital data from the data latch circuit to the parallel-to-serial signal conversion circuit at the timing of the serial load clock signal, extracts the digital data from the parallel-to-serial signal conversion circuit, and sends and receives digital data. In the digital data transfer device configured to perform the operation, a coincidence state between the time position of the transmission data latch clock signal transmitted from the transmission side to the reception side and the time position of the serial load clock signal generated on the reception side is detected. Time position detecting means, and an output signal from the time position detecting means The digital data transmitted from the transmitting side to the receiving side can be switched between the delayed digital data in a state where a predetermined time delay is given and the digital data in a state where the time delay is not given to be supplied to the receiving side. Digital data switching means for providing a data latch clock signal to the data latch circuit, the data latch clock signal being delayed by a time corresponding to the time delay from the transmission data latch clock signal transmitted from the transmission side. Digital data transfer device comprising: