JPH05102737A - Multiplier circuit - Google Patents

Abstract

PURPOSE:To reduce a bypass between input terminals by inserting a base ground transistor(TR) between amplifier sections of 1st and 2nd input signals to prevent the deterioration in the common mode rejection ratio at a high frequency side due to a parasitic capacitance of the TR. CONSTITUTION:First and 2nd common base TRs 13, 14 are inserted between a common emitter terminal of 1st and 2nd differential amplifier circuits TRs 1, 2 and TRs 3, 4 and the output terminal pair of plural 3rd differential amplifier circuit TRs 5-8. The emitter area of the TRs 13, 14 is set smaller than the maximum emitter area of the TR used for the TRs 5-8. Thus, the impedance when viewing the output terminal pair of the TRs 5-8 from the common emitter terminal of the TRs 1, 2 and the TRs 3, 4 is set larger than that without the TRs 13, 14. Thus, the part of the TRs 5-8 receives a DC offset, then even when the emitter area is increased, the reduction in the common mode rejection ratio of the TRs 1, 2 and the TRs 3, 4 due to a large parasitic capacitance of the TRs is prevented, and a bypass signal from terminal pairs L01, L02 to the input terminals M01, M02 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is constructed by using a differential amplifier circuit and includes a frequency converter, a synchronous detector, an amplitude phase modulator,
The present invention relates to a multiplication circuit used for a demodulator, a variable gain amplifier, etc.

[0002]

2. Description of the Related Art FIG. 17 shows a multiplication circuit which is conventionally well used. In FIG. 17, two input terminal pairs LO1 and L
Two input signals to be multiplied are input to O2 and MO1 and MO2. The first input signal input to the pair of input terminals LO1 and LO2 is amplified by the first differential amplifier circuit including the transistors Q1 and Q2 and the second differential amplifier circuit including the transistors Q3 and Q4. The respective output terminal pairs of the first and second differential amplifier circuits are connected so that the outputs of both differential amplifier circuits with respect to the first input signal cancel each other out. On the other hand, the second input signal input to the pair of input terminals MO1 and MO2 is amplified by the third differential amplifier circuit including the transistors Q5 and Q6 and converted into a change in the collector current of the transistors Q5 and Q6.

Since the collectors of the transistors Q5 and Q6 are connected to the common emitter terminals of the first and second differential amplifier circuits, the gains of the first and second differential amplifier circuits are the transistors Q5 and Q5. Proportional to the collector current of. As a result, a voltage proportional to the product of the voltages of the first and second input signals, that is, a multiplication calculation force is obtained between the common output terminal pair OP1 and OP2 of the first and second differential amplifier circuits.

In such a multiplication circuit, there is a problem that the output signal waveform is distorted when the voltage amplitude of the input signal becomes large due to the non-linearity of the differential amplifier circuit. In order to solve this problem, as disclosed in U.S. Pat. No. 4,965,528, two sets of differential amplifier circuits are combined as a third differential amplifier circuit, and an appropriate DC offset is given to each. Therefore, a technique for expanding the linear range has been proposed. The DC offset of the differential amplifier circuit can be set by the emitter area ratio of the differential transistor pair forming the differential amplifier circuit.

As a third differential amplifier circuit, it has been proposed to combine three or more sets of differential amplifier circuits to further expand the linear range. The method of assigning a DC offset to the differential amplifier circuit and weighting the current of each differential amplifier circuit in this case is described in Material Number ECT-90-20 of the Institute of Electrical Engineers of Japan, Electronic Circuit Research Group.

However, this method requires a transistor having a larger emitter area as the number of the third differential amplifier circuits increases, so that the parasitic capacitance of the transistor increases,
Difficult to use at high frequencies. For example, if the emitter area ratio of the differential transistor pair forming the third differential amplifier circuit is 1: 4, the sum of the parasitic capacitances between the collector and ground of the differential transistor pair is compared with that in the case of FIG. Since it is about 5 times, the CMRR (common mode rejection ratio) of the first and second differential amplifier circuits decreases as the frequency of the first input signal increases. Further, the sneak of the signal from the input terminal pair LO1, LO2 to the input terminal pair MO1, MO2 through the parasitic capacitance between the collector and the base becomes large.

The decrease in CMRR is caused by, for example, when a multiplying circuit is used as a frequency converter or a modulator of a transmitter and a local oscillation signal is given as a first input signal and a transmission signal is given as a second input signal. It becomes a factor to increase the carrier leak to the side. When the signal sneaking from the input terminal pair LO1, LO2 to the input terminal pair MO1, MO2 increases, for example, when a multiplication circuit is used for the frequency converter of the receiver, the local oscillation signal input to LO1, LO2 becomes MO.
As a result, the unnecessary radiation emitted from the antenna from 1, MO2 through the high frequency amplifier or the like is increased.

Further, the technique of widening the linear range according to the prior art can be applied only to the side of the third differential amplifier circuit to which the second input signal is input, and the first and second differential amplifier circuits. Since the expansion of the linear range of 1 is not achieved, there is a problem that the first input signal component is easily distorted.

On the other hand, when the frequencies of the first and second input signals and the frequency of the desired output signal are relatively far apart as in the frequency converter and demodulator, the multiplication circuit of FIG. A multiplication circuit having the configuration of FIG. 18, which is half, is often used. In FIG. 18, two input signals to be multiplied are input to the input terminal pair LO1 and LO2 and the input terminal Rf. The first input signal input to the pair of input terminals LO1 and LO2 is amplified by the differential amplifier circuit including the transistors Q11 and Q12. On the other hand, the second input signal input to the input terminal Rf is the transistor Q of the differential amplifier circuit.
It is amplified by the grounded-emitter transistor Q13 whose collector is connected to the common emitter terminals of 11 and Q12. Output terminal OP provided in the load circuit of the differential amplifier circuit
From this, the multiplication calculation force can be obtained.

The multiplication circuit of FIG. 18 has a problem that the noise figure is not sufficient when it is used as a frequency converter or a demodulator of a receiver. The noise generated in this multiplication circuit is mainly the thermal noise of the parasitic resistance of the base of the grounded-emitter transistor Q13. In order to reduce the thermal noise, the emitter area of the grounded-emitter transistor Q13 may be increased (thus the base area may be increased).

However, when the emitter area of the transistor Q13 is increased, the CMRR of the differential amplifier circuit is lowered and the input terminal pair LO1, LO2 is moved from the input terminal pair LO1 to the input terminal Rf, as in the linearized multiplication circuit of FIG. There arises a problem of increased signal wraparound. Particularly, in the direct conversion type receiver, since the reception frequency and the local oscillation frequency are almost the same, the input terminal pair LO1, LO2
When the local oscillation signal is input to the input terminal and the reception signal is input to the input terminal Rf, the local oscillation signal leaks through the input terminal Rf, which is a serious problem.

[0012]

As described above, in the conventional multiplication circuit shown in FIG. 17 in which the linear range is expanded, the common mode elimination of the differential amplifier circuit is performed in the high frequency region due to the increase of the parasitic capacitance of the transistor. As the ratio decreases, the signal wraparound between two input terminal pairs increases, and the linear range is expanded only for one input signal, and the distortion applied to the other input signal is sufficient. There was a problem that I was not suppressed.

Further, even in the simplified multiplication circuit as shown in FIG. 18, if a grounded-emitter transistor having a large emitter area is used in order to improve the noise figure,
Similarly, there are problems that the common mode rejection ratio in the high frequency region of the differential amplifier circuit is lowered and that the sneak of the signal between the input terminals is increased.

An object of the present invention is to provide a multiplication circuit which can prevent the common mode rejection ratio on the high frequency side from being lowered by the parasitic capacitance of the transistor and can reduce the sneak between the input terminals. Another object of the present invention is to provide a multiplication circuit that can expand the linear range of the differential amplifier circuit for both input signals and achieve low distortion.

[0015]

In order to solve the above-mentioned problems, the present invention basically comprises inserting a grounded base transistor between a first input signal amplifying section and a second input signal amplifying section. And

That is, for example, in a multiplication circuit for linearization, the first and second amplification circuits amplify the first input signal.
A grounded base transistor is inserted between the common emitter terminal of the differential amplifier circuit and the output terminal pair of the plurality of third differential amplifier circuits for amplifying the second input signal. More specifically, the first and second differential amplifier circuits having the first input signal as an input and having an output terminal pair and a common emitter terminal, and output terminals of the first and second differential amplifier circuits An output that connects the pair so that the outputs of the first and second differential amplifier circuits with respect to the first input signal cancel each other and extracts the difference between the outputs of the first and second differential amplifier circuits as an output signal. Means, first and second base-grounded transistors whose bases are AC grounded and whose collectors are connected to respective common emitter terminals of the first and second differential amplifier circuits, and a second input signal. It has a plurality of third differential amplifier circuits, which are input and have their respective output terminal pairs commonly connected to the emitters of the first and second grounded-base transistors and to which a predetermined DC offset is applied.

A plurality of first differential amplifier circuits and a plurality of second differential amplifier circuits may be provided, in which case a plurality of first and second grounded base transistors are also provided. This makes it possible to adopt a configuration in which a DC offset is also applied to the first and second differential amplifier circuits.

Further, according to the present invention, in the multiplication circuit for amplifying the first input signal by the differential amplifier circuit and the second input signal by the common-emitter transistor, the common emitter terminal and the common-emitter transistor of the differential amplifier circuit are provided. Insert a grounded base transistor between the collectors of. More specifically, the first input signal is an input, a differential amplifier circuit having an output terminal pair and a common emitter terminal, and a load connected to at least one output terminal of the output terminal pair of the differential amplifier circuit. A circuit, a grounded-emitter transistor having a second input signal as an input to the base, a base grounded in an alternating manner, a collector connected to a common emitter terminal of the differential amplifier circuit, and an emitter connected to the grounded-emitter transistor. A grounded base transistor having a smaller emitter area than the grounded emitter transistor connected to the collector.

[0019]

When the first and second grounded base transistors are inserted between the common emitter terminals of the first and second differential amplifier circuits and the output terminal pairs of the plurality of third differential amplifier circuits, these By making the emitter area of the base-grounded transistor of the third differential amplifier circuit smaller than the maximum emitter area of the transistor used in the third differential amplifier circuit, the third difference from the common emitter terminal of the first and second differential amplifier circuits. The impedance seen from the output terminal pair side of the dynamic amplifier circuit becomes larger than that without these base-grounded transistors.

As a result, even if the emitter area of some of the transistors of the third differential amplifier circuit is increased in order to give a DC offset, the first and second differential amplifier circuits have large parasitic capacitances of the transistors. Of the common mode rejection ratio is prevented, and the sneak of the signal from the first input terminal pair side to the second input terminal pair side is reduced.

Further, by providing a plurality of first and second grounded base transistors and a plurality of first and second differential amplifier circuits, respectively, the first and second differential amplifier circuits are provided. If the DC offset is also applied, the linear range is expanded not only for the first input signal but also for the second input signal, and the distortion of the entire multiplication circuit is further reduced.

If a grounded base transistor is inserted between the common emitter terminal of the differential amplifier circuit for amplifying the first input signal and the collector of the grounded emitter transistor for amplifying the second input signal, the grounded emitter transistor becomes a grounded emitter transistor. Even if a transistor having a large area is used for the purpose of reducing the parasitic resistance of the base, a reduction in the common mode rejection ratio of the differential amplifier circuit is prevented by the same principle as described above, and the first input terminal pair side is used. The sneak of the signal to the second input terminal side is reduced. Although the parasitic resistance of the base of the grounded-base transistor is large, the thermal noise due to this parasitic resistance hardly appears in the output due to the negative feedback effect due to the output impedance of the grounded-emitter transistor, so it is possible to increase the area of the grounded-emitter transistor. The noise figure of the circuit is improved.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a circuit of a multiplication circuit according to a first embodiment of the present invention. In FIG. 1, two input terminal pairs LO1,
Two input signals to be multiplied are input to LO2 and MO1 and MO2. The first input signal input to the input terminal pair LO1, LO2 is amplified by the first differential amplifier circuit including the transistors 1 and 2 and the second differential amplifier circuit including the transistors 3 and 4. The output terminal pair of the first differential amplifier circuit (collectors of the transistors 1 and 2) and the second
The output terminal pair of the differential amplifier circuit (collector of the transistors 3 and 4) is connected to one end of the load resistors 9 and 10 so that the outputs of both differential amplifier circuits with respect to the first input signal cancel each other. , Output terminal pair OP1, OP of the multiplication circuit
Connected to 2.

That is, in the first differential amplifier circuit, the collector of the transistor 1 whose base is connected to the input terminal LO1 is connected to the load resistor 9 and the output terminal OP1, and the base connected to the input terminal LO2 is While the collector of the connected transistor 2 is connected to the load resistor 10 and the output terminal OP2, in the second differential amplifier circuit, conversely, the transistor 3 whose base is connected to the input terminal LO1 is used. Is connected to the load resistor 10 and the output terminal OP2, and the input terminal LO2
The collector of the transistor 4 whose base is connected to is connected to the load resistor 9 and the output terminal OP1. The other ends of the load resistors 9 and 10 are connected to the power supply Vcc.

The bases of the common emitter terminals of the transistors 1 and 2 in the first differential amplifier circuit and the common emitter terminals of the transistors 3 and 4 in the second differential amplifier circuit are AC-grounded. And the collectors of the second grounded-base transistors 13 and 14 are connected.

On the other hand, the second input signal input to the pair of input terminals MO1 and MO2 is amplified by the two third differential amplifier circuits composed of the transistors 5, 7 and the transistors 6, 8. The common emitter terminal of each of the third differential amplifier circuits is connected to the constant current sources 11 and 12.

The output terminal pair of the third differential amplifier circuit is commonly connected to the emitters of the base-grounded transistors 13 and 14. That is, the collectors of the transistors 5 and 6 are commonly connected to the emitter of the first grounded base transistor 13, and the collectors of the transistors 7 and 8 are commonly connected to the second grounded base transistor 14.

The two transistors respectively constituting the third differential amplifier circuit have a predetermined emitter area ratio, and in this example, the transistors 6, 8 are opposed to the transistors 6, 8.
7 has an emitter area of about 4 times. By setting the emitter area ratio as described above, the two third differential amplifier circuits are given DC offsets to the second input signals from the input terminal pairs MO1 and MO2, respectively. By combining the outputs of the differential amplifier circuit, the linear range of the third differential amplifier circuit is expanded. The principle of expanding the linear range by the DC offset is well known, and a detailed description thereof will be omitted here.

First and second amplifying first input signals
Of the differential amplifier circuit, the common emitter terminal is coupled to the output terminal pair of the third differential amplifier circuit through the base-grounded transistors 13 and 14, so that the gain of the differential amplifier circuit amplifies the second input signal. 3 is proportional to the collector current of the differential amplifier circuit. Therefore, since an output signal having a voltage amplitude proportional to the product of the first and second input signals is obtained from between the output terminal pair OP1 and OP2, the circuit of FIG. 1 operates as a multiplication circuit.

Here, grounded base transistors 13 and 1
The emitter area of No. 4 is smaller than the maximum emitter area of the transistor in the third differential amplifier circuit (emitter area of the transistors 6 and 7), and its parasitic capacitance is also small. The grounded base transistors 13 and 14 have the third emitter area
If the emitter areas of the transistors 6 and 7 are about 5 times the emitter areas of the transistors 5 and 8, the parasitic capacitance is about 1/5. Therefore, in the high frequency region, the conventional linear range in which the common-emitter terminals of the first and second differential amplifier circuits and the collector of the third differential amplifier circuit are directly connected without the grounded base transistors 13 and 14 is expanded. Compared with the above, the impedance seen from the common emitter terminal of the first and second differential amplifier circuits to the third differential amplifier circuit side is higher. Therefore, the CMRR (common mode rejection ratio) of the first and second differential amplifier circuits at high frequencies becomes high.

The result of confirming this effect by computer simulation is shown in FIG. In this kind of multiplication circuit,
Since one input terminal of the differential amplifier circuit is normally grounded in an alternating current and used, the input terminal LO1 in the multiplication circuit in FIG.
A sine wave input is applied to the input terminal LO2 and the frequency characteristic of the carrier leak at the output terminal OP1 when the input terminal LO2 is grounded in an alternating current is obtained and shown in FIG. In FIG. 2, a curve A is a carrier leak of the multiplication circuit of FIG. 1, a curve B is a carrier leak of the multiplication circuit of FIG. 1 in which the grounded base transistors 13 and 14 are removed, and a curve C is the conventional basic leakage shown in FIG. Each shows the carrier leak of the multiplication circuit.

When a signal having only a differential component is input between the pair of input terminals LO1 and LO2, the carrier leak is -100 dB.
Since it was below, it is considered that the curve in FIG. 2 represents the carrier leak due to the in-phase component. As shown by the curve A, the multiplication circuit of FIG.
Compared to the case without 3 and 14, the carrier leak is small in the entire frequency range, and the carrier leak is about 30 dB at a low frequency in particular, and about 8 dB compared to the multiplication circuit of FIG.
Since the number is small, the effect of improving the CMRR according to the present invention is clear.

Therefore, when this multiplication circuit is used as a frequency converter or modulator of a transmitter and a local oscillation signal is given as the first input signal and a transmission signal is given as the second input signal,
Carrier leak to the transmission output side can be reduced.

The grounded base transistors 13 and 14 are also provided.
Since the amount of change in collector voltage transmitted to the emitter side is also small, the voltage change in the collectors of the transistors 5 and 6 is small, and the carrier leak from the input terminal LO1 to the input terminal MO1 side is correspondingly small.

Therefore, by using this multiplication circuit in the frequency converter of the receiver, the local oscillation signal from the local oscillator is input between the input terminal pair LO1, LO2, and the input terminal pair MO1, M2.
When the received signal is input between O2, the local oscillation signal is MO
1, the amount leaked from MO2 and radiated as unnecessary radiation from the antenna through the high frequency amplifier or the like can be reduced.

FIG. 3 shows the result of confirming this effect by computer simulation. The input terminal pair L
It is a frequency characteristic of carrier leak to the input terminal MO1 side when an input similar to that of FIG. 2 is applied between O1 and LO2. In FIG. 2, a curve D is a carrier leak of the multiplication circuit of FIG. 1, and a curve E is a grounded base transistor 1 of FIG.
Carrier leak of multiplying circuit with 3 and 14 removed, curve F
Shows carrier leakage of the conventional basic multiplication circuit shown in FIG. According to the curve D, the carrier leak is lower than the curves E and F in the entire frequency range.
Particularly, at a low frequency, the carrier leak of the multiplication circuit of FIG. 1 is 40 dB less than that of the basic multiplication circuit of FIG. 3, and the effect of reducing the carrier leakage according to the present invention is clear.

Next, another embodiment of the present invention will be described. FIG. 4 shows a multiplication circuit according to the second embodiment, and the linear range is further expanded by combining four third differential amplifier circuits. Transistors 21 and 25, 22 and 2
Each of the differential transistor pairs 6, 23 and 27, 24 and 28 and the constant current sources 31 to 34 respectively connected to the emitter common terminals of these differential transistor pairs form four third differential amplifier circuits. It is configured. Here, the emitter area ratio of the transistors 21, 28, the transistors 22, 27, and the transistors 23 to 26 is, for example, 13: 2: 1.
By selecting, the DC offset is given to each differential amplifier circuit. Weighting is performed by selecting the current ratio of the constant current sources 31 to 34 as shown in the figure.

The number of the third differential amplifier circuits may be three, or five or more, and the number may be selected according to the required linear range. As seen in the example of FIG. 4, as the number of differential amplifier circuits is increased, a transistor having a larger emitter area is required, and the parasitic capacitance is also increased accordingly. The improvement effect becomes more remarkable.

FIG. 5 shows a multiplication circuit according to the third embodiment, in which two first and second differential amplifier circuits are provided and two first and second base common transistors are also provided. It is provided. That is, the differential transistor pair 4
1, 43 and the differential transistor pair 42, 44 constitute a first differential amplifier circuit, and the differential transistor pair 45, 47 and the differential transistor pair 46, 48 constitute a second differential amplifier circuit. ing. The emitter area ratio of the transistors 41, 44, 45, 48 and the transistors 42, 43, 46, 47 is selected to be, for example, 4: 1, so that the first and second
A DC offset is added to the differential amplifier circuit.

The two common emitter terminals of the first differential amplifier circuit are connected to the collectors of the first grounded common transistors 58 and 59, and the two common emitter terminals of the second differential amplifier circuit are the second base. It is connected to the collectors of the ground transistors 60 and 61. On the other hand, transistors 49-
54 and the constant current sources 55 to 57 form three third differential amplifier circuits. The first base-grounded transistor 5 is connected to one terminal (common collector terminal of the transistors 49 to 51) of the common output terminal pair of the third differential amplifier circuit.
The emitters of 8 and 59 are commonly connected, and the second base-grounded transistors 60 and 6 are connected to the other terminal (common collector terminal of the transistors 52 to 54) of the common output terminal pair.
One emitter is commonly connected.

As described above, in this embodiment, the first and second
By providing multiple base-grounded transistors of
A plurality of first and second differential amplifier circuits are provided,
Since a DC offset can be applied, the linear range can be expanded even for the first input signal applied to the input terminal pair LO1, LO2. Therefore, the multiplication circuit of this embodiment is suitable for applications where both input signals are information signals and linearity is required for both inputs over a wide frequency range.

FIG. 6 shows a multiplication circuit according to the fourth embodiment, which includes three first and second differential amplifier circuits each including transistors 71 to 82 and three third and third differential amplifier circuits, respectively. Fourth grounded base transistors 91-93 and 94-96 are provided. The third differential amplifier circuit is composed of transistors 83 to 88 and constant current sources 97 to 99.

In this embodiment, for example, the transistors 71, 76, 77 in the first and second differential amplifier circuits are
82 and the transistors 72 to 75, 78 to 81 have an emitter area ratio of 8: 1, and the grounded base transistor 91,
93, 94, 96 and base-grounded transistors 92, 95
By setting the emitter area ratio of the above to 3: 2, the first and second differential amplifier circuits have a DC offset, and the collector current proportional to the emitter area flows through the common-base transistor, so that The distribution ratio of the emitter current can be weighted in the second differential amplifier circuit.

In the third differential amplifier circuit, the emitter area ratio of the transistors 83 and 88 and the transistors 84 to 87 is selected to be 8: 1, and the constant current source 9 is used.
A DC offset is given and weighted by selecting a current ratio of 7 to 99 as shown in the figure.

When the weighting method according to this embodiment is used, it is possible to configure the entire multiplication circuit with only one of the npn type transistor and the pnp type transistor. In general, an npn transistor has a better frequency characteristic than an pnp transistor in an integrated circuit. Therefore, it is advantageous to improve the frequency characteristic of the multiplication circuit by being able to configure only the npn transistor as in this embodiment.

FIG. 7 shows a multiplication circuit according to the fifth embodiment. Common terminals of the emitters of the first and second differential amplifier circuits shown in FIG.
1-96, grounded base transistors 105-110 having a small emitter area are inserted. Therefore, according to this embodiment, in addition to the advantages of the embodiment of FIG. 6, the effect that the deterioration of CMRR due to the inclusion of the transistors having a large emitter area and a large parasitic capacitance in the weighted base ground transistors 91 to 96 can be suppressed. can get. In this embodiment, the third differential amplifier circuit is composed of transistors 101 to 104 and constant current sources 111 and 112.
The emitter area ratio with 2,103 is, for example, 4: 1,
The current ratio of the constant current sources 111 and 112 is selected to the value shown in the figure.

8 to 12 show a multiplication circuit according to an embodiment obtained by modifying the above-mentioned first to fifth embodiments. The input terminal pair LO1, LO2, the input terminal pair LO3, LO4 and the input terminal pair MO1 are shown. , MO2 are given an appropriate DC bias potential together with the input signal, and the base terminals VB1, VB2, VB3, VB4 of the base-grounded transistors are given an appropriate DC bias potential and are also grounded in AC. Needless to say, even in this case, the same operation as in the previous embodiment can be obtained.

In the above embodiment, both the first input signal and the second input signal are input to the differential amplifier circuit.
The first input signal may be input to the differential amplifier circuit and the second input signal may be input to the grounded-emitter amplifier circuit. An example will be described below.

FIG. 14 shows a multiplication circuit according to the sixth embodiment. A first input signal is input to the input terminal pair LO1, LO2, and a second input signal is input to the other input terminal Rf. Is entered. The first input signal input to the input terminal pair LO1 and LO2 is amplified by the differential amplifier circuit including the transistors 201 and 202. The output terminal pair (collectors of the transistors 201 and 202) of this differential amplifier circuit is connected to the power supply Vcc via the load circuit 203. The load circuit 203 is a transistor 2 in this example.
The current mirror circuit is composed of 04 and 205, and the collector of the transistor 205 is connected to the output terminal OP.

On the other hand, the second input signal input to the input terminal Rf is amplified by the grounded-emitter transistor 207. The base of the transistor 207 is connected to the input terminal Rf, and the emitter is grounded.

Transistor 20 in the differential amplifier circuit
The collector of the grounded-base transistor 206 is connected to the common emitter terminals of 1, 202, and the emitter of the transistor 206 is connected to the collector of the grounded-emitter transistor 207. Further, the base terminal VB of the grounded base transistor 206 is given an appropriate DC bias potential and is grounded in an AC manner.

Since the common emitter terminal of the differential amplifier circuit for amplifying the first input signal is coupled to the collector of the common-emitter transistor 207 for amplifying the second input signal via the common-base transistor 206, The gain of the differential amplifier circuit is proportional to the collector current of the transistor 207. Therefore, since an output signal proportional to the product of the first and second input signals is obtained from the output terminal OP,
Circuit operates as a multiplication circuit.

When this multiplication circuit is used as a frequency converter or a demodulator of a receiver for receiving and demodulating a weak signal, a base parasitic resistance of the grounded-emitter transistor 207 is generated in order to minimize the noise figure. It is necessary to reduce thermal noise. Therefore, as the grounded-emitter transistor 207, a transistor having a small base parasitic resistance, that is, a relatively large emitter area is used. On the other hand, as the grounded base transistor 206, a transistor whose emitter area is smaller than that of the grounded emitter transistor 207 is used. For example, transistors 206 and 2
The emitter area ratio with 07 is chosen to be 1: 4.

Therefore, since the parasitic capacitance of the transistor 206 is smaller than that of the transistor 207, the grounded-emitter transistor 2 is connected from the common emitter terminal of the differential amplifier circuit.
The impedance viewed from the collector side of 07 is the conventional multiplication circuit without the grounded base transistor 206 (see, for example, FIG.
It is higher than 8). This reduces the CMRR due to the use of a transistor having a large emitter area as the grounded-emitter transistor 207, and reduces the input terminal pair L.
The sneak of the input signal to O1 and LO2 to the input terminal Rf side is reduced.

FIG. 14 shows a multiplication circuit according to the seventh embodiment, which is provided with three differential amplifier circuits for amplifying the first input signal and three grounded base transistors. That is, the first differential transistor pair 301, 304,
The second differential transistor pair 302, 305 and the third differential transistor pair 303, 306 respectively form a differential amplifier circuit. The output terminal pair of each of these differential amplifier circuits is connected to a common load circuit 307. The load circuit 307 is provided with an output terminal OP.

The common emitter terminals of the three differential amplifier circuits are respectively grounded base transistors 308,
Connected to the collectors of 309 and 310, transistor 3
The emitter of 08 is connected to the collector of the grounded-emitter transistor 311. The common base terminal VB of the grounded base transistors 308, 309 and 310 is given an appropriate DC bias potential and is also grounded in AC.

In this embodiment, the transistors 301 and 306 and the transistors 302 and 3 which form the differential amplifier circuit.
The emitter area ratio with 03, 304, 305 is, for example, 4:
1, and by setting the emitter area ratio of the transistors 308, 309, and 310 to, for example, 3: 2: 3, a DC offset is given to the differential amplifier circuit and a current flowing through each common emitter terminal of the differential amplifier circuit. The distribution ratio of is weighted. As a result, the input terminal pair LO1, LO2
Linearization is achieved for the first input signal input to. Therefore, this multiplication circuit is used, for example, as a frequency converter (mixer) of the receiver, and the input terminal pair LO1, LO2 is used.
When a local oscillation signal is input to the input terminal and a high frequency input signal is input to the input terminal Rf, harmonics of the local oscillation signal can be reduced. As a result, it is possible to reduce the amount of the product of the interfering wave or noise included in the high frequency input signal and the local oscillation signal, which is superimposed on the desired output frequency and output.

FIG. 15 shows a multiplication circuit according to the eighth embodiment, in which each emitter common terminal of the differential amplifier circuit shown in FIG. 14 and weighted base-grounded transistors 308-310.
(Second grounded base transistor) and a grounded base transistor 312 to 314 having a small emitter area
(First grounded base transistor) is inserted. Common base terminal VB1 of transistors 308-310 and common base terminal VB2 of transistors 312-314
Are both given an appropriate DC bias potential and are grounded AC.

Therefore, according to this embodiment, in addition to the advantages of the embodiment of FIG. 14, the deterioration of CMRR due to the inclusion of the transistors with large emitter areas and large parasitic capacitances in the weighted base ground transistors 308 to 310 is added. This can be suppressed by the grounded base transistors 312 to 314, and an effect that the amount of the signal input to the input terminal pair LO1, LO2 sneaking into the input terminal Rf side can be reduced can be obtained.

FIG. 16 shows a multiplication circuit according to the ninth embodiment, which is a preferred example of the multiplication circuit used as a quadrature demodulator in a direct conversion receiver. This multiplying circuit is a combination of two multiplying circuits shown in FIG. 13 as a unit multiplying circuit, and these two unit multiplying circuits share one common-emitter transistor.

In FIG. 16, input terminal pairs LO1, LO2 and LO are respectively provided for two unit multiplication circuits.
3, LO4 are provided. In the case of the quadrature demodulator, the signals input to the input terminal pair LO1 and LO2 and the signals input to the input terminal pair LO3 and LO4 are 90 degrees from each other.
° This is a local oscillation signal with a phase shift. A signal to be demodulated, that is, a modulated signal is input to the other input terminal Rf.

The signal input to the pair of input terminals LO1 and LO2 is amplified by the differential amplifier circuit including the transistors 401 and 402, and is output from the load circuit 405 to the output terminal OP.
It is output to 11. The signal input to the input terminal pair LO3, LO4 is amplified by the differential amplifier circuit including the transistors 403, 404 and output from the load circuit 406 to the output terminal OP12. On the other hand, the second input signal input to the input terminal Rf is amplified by the common-emitter transistor 409. This transistor 409
Has a base connected to the input terminal Rf and an emitter grounded.

The common emitter terminals of the transistors 401 and 402 and the common emitter terminals of the transistors 403 and 404 are connected to the collectors of the base-grounded transistors 407 and 408, respectively, and the transistors 407 and 40 are connected.
The eight emitters are commonly connected to the collector of the grounded-emitter transistor 407. The common base terminal VB of the base-grounded transistors 407 and 408 is supplied with an appropriate DC bias potential and is grounded AC.

The common emitter terminals of the two differential amplifier circuits for amplifying the local oscillation signals which are 90 ° out of phase with each other have common emitter terminals for amplifying the modulated signal via the grounded base transistors 407 and 408, respectively. Since it is coupled to the collector of transistor 409,
From the output terminals OP11 and OP12, demodulation outputs having 90 ° different phases, that is, quadrature demodulation outputs are obtained.

In this embodiment, the grounded-base transistors 407 and 408 reduce the influence of the parasitic capacitance of the grounded-emitter transistor 409 whose emitter area is increased to reduce the parasitic resistance, and the output current (collector) of the grounded-emitter transistor 409. Current) is distributed to two differential amplifier circuits.

It is important for the quadrature demodulator to reduce the phase error and the conversion gain error. In a conventional general quadrature demodulator, a modulated signal to be demodulated is divided into two, and then input to two independent multiplication circuits to which local oscillation signals whose phases are shifted by 90 ° are supplied. On the other hand, in the quadrature demodulator using the multiplication circuit of FIG.
The modulated signal is input to the base of the common-emitter transistor 409 common to the two multiplying circuits, and simultaneously with distribution, multiplication with the local oscillation signal (quadrature demodulation) is performed. Therefore, the quadrature demodulator using the multiplication circuit of FIG. 16 has a smaller number of elements through which the modulated signal passes, as compared with the above-described conventional quadrature demodulator, and thus the error factors are reduced accordingly, and the phase The error and the conversion gain error can be reduced.

In the embodiment shown in FIG. 16, the multiplication circuit shown in FIG. 13 is used as the basic two sets of unit multiplication circuits, but the multiplication circuit shown in FIG. 14 or 15 may be used. It is also possible to combine three or more unit multiplication circuits by sharing the common-emitter transistor.

[0068]

According to the present invention, the common-mode rejection ratio at a high frequency is reduced, the signal wraparound between the input terminals to which two signals to be multiplied are input is small, and the linear range is wide and the distortion is small. A small multiplying circuit can be provided.

Therefore, if this multiplication circuit is used in a transmitter, for example, a transmission output with less carrier leak and less distortion can be obtained. Further, when this multiplication circuit is used for a receiver, low noise and a wide dynamic range and unnecessary radiation due to leakage of a local oscillation signal into an antenna system can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a multiplication circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing frequency characteristics of carrier leak at an output terminal of the multiplication circuit of FIG.

3 is a diagram showing frequency characteristics of carrier leak at the input terminal of the multiplication circuit of FIG.

FIG. 4 is a circuit diagram of a multiplication circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a multiplication circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a multiplication circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of a multiplication circuit according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a modification of the first embodiment.

FIG. 9 is a circuit diagram showing a modification of the second embodiment.

FIG. 10 is a circuit diagram showing a modification of the third embodiment.

FIG. 11 is a circuit diagram showing a modification of the fourth embodiment.

FIG. 12 is a circuit diagram showing a modification of the fifth embodiment.

FIG. 13 is a circuit diagram of a multiplication circuit according to a sixth embodiment of the present invention.

FIG. 14 is a circuit diagram of a multiplication circuit according to a seventh embodiment of the present invention.

FIG. 15 is a circuit diagram of a multiplication circuit according to an eighth embodiment of the present invention.

FIG. 16 is a circuit diagram of a multiplication circuit according to a ninth embodiment of the present invention.

FIG. 17 is a circuit diagram of a conventional multiplication circuit.

FIG. 18 is a circuit diagram of a conventional multiplication circuit.

[Explanation of symbols]

LO1, LO2 ... 1st input terminal pair MO1, MO2 ... 2nd input terminal pair Rf ... 2nd input terminal OP1, OP2 ... Output terminal pair OP ... Output terminal 1, 2, 41-44, 71-76 ... Transistors of first differential amplifier circuit 3, 4, 45 to 48, 77 to 82 ... Transistors of second differential amplifier circuit 9, 10 ... Load resistors 5 to 8, 21 to 28, 49 to 54, 83 to 88,101
To 104 ... Transistors of the third differential amplifier circuit 13, 58, 59, 105 to 107 ... First base ground transistor 14, 60, 61, 108 to 110 ... Second base ground transistor 91 to 93 ... Third Base-grounded transistors 94 to 96 ... Fourth base-grounded transistors 201 to 202, 301 to 306, 401 to 404 ... Transistors 206, 308 to 310, 312 to 314, 407 to 4 of the differential amplifier circuit
08 ... Common grounded transistor 207, 311, 409 ... Commonly grounded emitter transistor 203, 307, 405, 406 ... Load circuit

Claims (9)

[Claims] 1. A first and second differential amplifier circuit, which receives a first input signal and has an output terminal pair and a common emitter terminal, respectively, and an output terminal pair of the first and second differential amplifier circuits. Is connected so that the outputs of the first and second differential amplifier circuits with respect to the first input signal cancel each other, and the output means for extracting the difference between the outputs of the first and second differential amplifier circuits as an output signal And the base is AC grounded and the collectors are the first and second
First and second common-base transistors connected to respective common emitter terminals of the differential amplifier circuit, and a second input signal as an input, and respective output terminal pairs having first and second common-base transistors And a plurality of third differential amplifier circuits to which a predetermined DC offset is applied, the third differential amplifier circuits being commonly connected to the emitters of. 2. A plurality of first and second differential amplifier circuits, each having a first input signal as an input and having a pair of output terminals and a common emitter terminal and provided with a predetermined DC offset, and a first difference. The output terminal pair of the dynamic amplifier circuit and the output terminal pair of the second differential amplifier circuit cancel the output of the first differential amplifier circuit and the output of the second differential amplifier circuit with respect to the first input signal. And the output means for extracting the difference between the outputs of the first and second differential amplifier circuits as an output signal, and the plurality of first differential amplifier circuits whose bases are AC-grounded and whose collectors are grounded. Connected to the common emitter terminal of
A plurality of first grounded-base transistors whose emitters are commonly connected, a base which is grounded in an alternating manner, and a collector which is connected to respective common emitter terminals of a plurality of second differential amplifier circuits,
A plurality of second common-grounded transistors whose emitters are commonly connected, and a second input signal as an input, and common output terminals of the first and second common-grounded transistors are commonly connected to their respective output terminal pairs. And a plurality of third differential amplifier circuits to which a predetermined DC offset is applied. 3. The multiplication according to claim 1, wherein the first and second grounded base transistors have an emitter area smaller than the maximum emitter area of the transistor used in the third differential amplifier circuit. circuit. 4. A plurality of first and second differential amplifier circuits, each having a first input signal as an input and having a pair of output terminals and a common emitter terminal and provided with a predetermined DC offset, and a first difference. The output terminal pair of the dynamic amplifier circuit and the output terminal pair of the second differential amplifier circuit cancel the output of the first differential amplifier circuit and the output of the second differential amplifier circuit with respect to the first input signal. And the output means for extracting the difference between the outputs of the first and second differential amplifier circuits as an output signal, and the plurality of first differential amplifier circuits whose bases are AC-grounded and whose collectors are grounded. Connected to the common emitter terminal of
A plurality of first grounded-base transistors having a predetermined emitter area ratio with emitters commonly connected, a base grounded in an alternating current, and a collector connected to respective common emitter terminals of a plurality of second differential amplifier circuits. Was
A plurality of second grounded-base transistors having a predetermined emitter area ratio, whose emitters are commonly connected, and a second input signal, which are input to common emitter terminals of the first and second common-grounded transistors, respectively. And a plurality of third differential amplifier circuits to which a pair of output terminals are commonly connected and to which a predetermined DC offset is applied. 5. A plurality of first and second differential amplifier circuits, each having a first input signal as an input and having a pair of output terminals and a common emitter terminal and provided with a predetermined DC offset, and a first difference. The output terminal pair of the dynamic amplifier circuit and the output terminal pair of the second differential amplifier circuit cancel the output of the first differential amplifier circuit and the output of the second differential amplifier circuit with respect to the first input signal. And the output means for extracting the difference between the outputs of the first and second differential amplifier circuits as an output signal, and the plurality of first differential amplifier circuits whose bases are AC-grounded and whose collectors are grounded. A plurality of first grounded base transistors connected to the common emitter terminals of the plurality of first bases, and a plurality of first bases of which bases are AC-grounded and collectors of which are connected to respective common emitter terminals of the plurality of second differential amplifier circuits. 2 base connections A transistor, a plurality of third grounded base transistors having a predetermined emitter area ratio, a base of which is AC grounded, a collector of which is connected to respective emitters of the first grounded base transistor, and which of which emitters are commonly connected; A plurality of fourth grounded-base transistors having a predetermined emitter area ratio, the bases of which are AC grounded, the collectors of which are connected to the respective emitters of the second grounded-ground transistors, and the emitters of which are commonly connected; A plurality of third differential amplifier circuits each having an input signal as an input, having respective output terminal pairs commonly connected to respective common emitter terminals of the first and second common-base transistors, and having a predetermined DC offset And a multiplying circuit. 6. A differential amplifier circuit having a first input signal as an input and having an output terminal pair and a common emitter terminal, and a load circuit connected to at least one output terminal of the output terminal pair of the differential amplifier circuit. A grounded-emitter transistor having a second input signal as an input to the base; a base grounded in an alternating manner; a collector connected to a common emitter terminal of the differential amplifier circuit; A grounded-base transistor having a smaller emitter area than the grounded-emitter transistor connected to. 7. A plurality of differential amplifier circuits to which a first input signal is input and which are provided with a predetermined DC offset having an output terminal pair and a common emitter terminal, and at least an output terminal pair of the differential amplifier circuit. A load circuit connected to one output terminal, a grounded-emitter transistor having a second input signal as an input to the base, a base grounded in an alternating manner, and a collector common to each of the plurality of differential amplifier circuits. And a plurality of grounded base transistors having a predetermined emitter area ratio, the emitters being connected to the emitter terminals and the emitters being connected to the collectors of the grounded emitter transistors. 8. A plurality of differential amplifier circuits which receive a first input signal and which are provided with a predetermined DC offset and which have an output terminal pair and a common emitter terminal, and at least an output terminal pair of the differential amplifier circuit. A load circuit connected to one output terminal, a grounded-emitter transistor having a second input signal as an input to the base, a base grounded in an alternating current, and an emitter commonly connected to the collector of the grounded-emitter transistor. A plurality of first grounded grounded transistors having a predetermined emitter area ratio, a base is grounded in an alternating manner, a collector is connected to a common emitter terminal of each of the plurality of differential amplifier circuits, and an emitter is The emitter area connected to each collector of the first common-base transistor is the smallest of the first common-base transistors. A plurality of second equal to or less than that of the transistor of the miter area
And a base-grounded transistor of 1. 9. The multiplying circuit according to claim 6, 7 or 8 is provided as a unit multiplying circuit, and a plurality of unit multiplying circuits are provided, and the grounded emitter transistor is shared by the plurality of unit multiplying circuits. Multiplying circuit.