JP3102187B2 - Quadrature modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature modulator used for digital mobile communication.

[0002]

2. Description of the Related Art In recent years, quadrature modulators have a built-in 90 ° divider with the progress of digitalization of mobile communication, and have been developed to realize good modulation characteristics such as wideband frequency characteristics.
Computerization is progressing.

Hereinafter, a conventional quadrature modulator will be described. FIG. 10 is a block connection diagram showing a configuration of a conventional quadrature modulator. In FIG. 10, 1 is a carrier input terminal,
2 is a modulation output terminal, 3 is an in-phase signal input terminal of a modulation base band signal, 4 is a quadrature signal input terminal of the modulation base band signal, 5 is a 90 ° distributor for dividing a carrier into two, and 6 is an in-phase signal. A double balance mixer (DBM) 7 for orthogonal signals is a double balance mixer (DBM) for quadrature signals, and 8 is a differential buffer amplifier.

[0004] The operation of the quadrature modulator configured as described above will be described below. First, the carrier input from the carrier input terminal 1 is divided into two signals having a phase difference of 90 ° by the 90 ° distributor 5 and the DBM for the in-phase signal is used.
6 and the distributed signal DBM7. The two signals distributed at 90 ° are respectively multiplied by the DBMs 6 and 7 with the modulated baseband signals input from the in-phase signal input terminal 3 and the quadrature signal input terminal 4. The in-phase and quadrature modulated signals multiplied by the carrier are directly synthesized, and the image components are canceled at this time. Image
The suppression ratio of the di component greatly depends on the amplitude and phase error of the 90 ° divider, and the 90 ° divider having the same output level and good orthogonality is an important element. The combined two outputs are input to the differential buffer amplifier 8. At this time, since the carrier components and the even-order distortion components of the two outputs are in phase, these components are canceled out and suppressed. . In this way, a signal obtained by modulating the carrier according to the modulation baseband signal is obtained at the output, and the signal is extracted from the output terminal 2.

[0005]

However, in the above configuration, if the 90 ° divider is constituted by a calculus circuit composed of a resistor and a capacitor, there is no problem in terms of current consumption. There is a problem that an amplitude difference occurs between the component and the orthogonal component.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and has a small amplitude and phase error and a small current consumption of 90 ° with respect to variations in the semiconductor manufacturing process and frequency changes.
An object of the present invention is to provide a quadrature modulator including a distributor.

[0007]

In order to achieve this object, a quadrature modulator according to the present invention has a 90.degree.
Amplifies and saturates the output of the divider and the 90 ° divider
An output saturation circuit, in-phase with the output of the output saturation circuit and
First and second multiplications with orthogonal modulation baseband signals
2 double balanced mixers and the first and second double
The output of the balance mixer is synthesized, and the carrier component and its
An output buffer amplifier for suppressing harmonic components;
0 ° divider has calculus with resistance and capacitance of MIM structure
It is composed of circuits and helps reduce the level of the carrier signal
Power supply voltage to reduce the capacitance between
And the output saturation circuit includes a single-phase input differential amplifier.
One stage, then at least one stage for the two-phase input differential amplifier
The output buffer amplifier is connected to a differential amplifier and a 2-input
A two-input, one-output buffer amplifier.
The op-amp is connected to both the inverted outputs of the preceding differential amplifier as input and
To obtain a combined output, wherein the output saturation circuit and the output buffer
The amplifier has a built-in low-pass filter function inside
It is characterized by the following .

[0008]

[Function] By using the output saturation circuit , one half is obtained.
Alternatively, the amplitude error of the in-phase component and the quadrature component due to a change in the resistance and capacitance values caused by variations in the semiconductor manufacturing process can be reduced with less current consumption than a 90 ° divider configured using a quarter frequency divider. Can be compressed,
Since a sufficient image suppression ratio can be secured, a quadrature modulator with good modulation accuracy can be realized. Also, with respect to an amplitude error caused by a change in frequency, an effect of similarly compressing an amplitude error between an in-phase component and a quadrature component can be obtained, so that a wide operating frequency band can be secured, and a wideband quadrature modulator can be used. It is feasible. With this configuration, 90 ° distributor
Reduces the inter-sub capacitance by applying the power supply voltage.
And the voltage of the stray capacitance
The voltage can be suppressed, and the voltage required for operation is sufficient.
Can be secured. The output buffer amplifier is differentially increased.
By constructing a buffer and a two-input one-output buffer amplifier,
In the differential amplifier, the carrier component serving as the in-phase input is used.
Suppress minute and even order distortion components and remove unnecessary signals
And a two-input / one-output buffer amplifier,
The two outputs of the differential amplifier
With less distortion compared to a normal emitter follower
A large output signal is obtained. The output saturation circuit and output
Built-in low-pass filter function inside power buffer amplifier
By adding a small capacity, the desired characteristics can be
Low-pass filter with
Can be planned .

[0009]

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a quadrature modulator according to a first embodiment of the present invention, and FIG. 2 is a 90 ° distributor and output saturation, which are main parts of the quadrature modulator according to the first embodiment of the present invention. FIG. 3 shows a detailed circuit as an embodiment of the circuit, and FIG. 3 shows a detailed circuit as an embodiment of the two-system output buffer amplifier.

In FIG. 1, reference numeral 11 denotes a carrier input terminal;
Reference numeral 12 denotes a modulation output terminal, 13 denotes an in-phase signal input terminal of a modulation base band signal, 14 denotes a quadrature signal input terminal of a modulation base band signal, 15 denotes a 90 ° divider for dividing a carrier into two, and 16 and 17 denote outputs. Reference numeral 18 denotes a double balance mixer for in-phase signals (DBM), reference numeral 19 denotes a double balance mixer for quadrature signals (DBM), and reference numeral 20 denotes a differential buffer amplifier.

FIG. 2 shows the details of the distributor 15 and the output saturation circuit 16 which are the main parts of FIG. 1, and more specifically, is constituted by a calculus circuit composed of a resistor and a capacitor having an MIM structure.
FIG. 3 shows a detailed circuit as an embodiment of an 0 ° distributor 15 and an output saturation circuit 16 composed of one stage of a single-phase input differential amplifier and one stage of a two-phase input differential amplifier thereafter.
The output saturation circuit 17 is omitted because it is the same as the output saturation circuit 16.

In FIG. 2, reference numeral 21 denotes a power supply voltage terminal;
Is a bias terminal, 23 and 24 are output terminals of the output saturation circuit 16, 25 and 26 are resistors constituting a calculus circuit,
28 is a MIM capacitor constituting a calculus circuit, 29 and 30 are DC blocking MIM capacitors, 31 to 33 are MIM capacitors between sub-subs, and 34 are bias resistors for reducing the MIM capacitors 27 between sub-subs. Reference numerals 35 to 37 denote resistors and capacitors for determining the base bias of the transistors 38 and 39 constituting the single-phase input differential amplifier.
Is a load resistance of the single-phase input differential amplifier, 42 is a constant current source of the single-phase input differential amplifier, 43 and 44 are transistors constituting the two-phase input differential amplifier, and 45 and 46 are two-phase input differential amplifiers. A load resistor 47 is a resistor connected to the emitters of the transistors 43 and 44, and 48 and 49 are constant current sources of a two-phase input differential amplifier.

FIG. 3 shows a detailed circuit as an embodiment of the two-system output buffer amplifier 20, which is a main part of FIG.

In FIG. 3, reference numerals 50 and 51 denote transistors constituting a two-phase input differential amplifier, 52 and 53 denote load resistances of the two-phase input differential amplifier, and 54 denote transistors 50 and 51.
, 55 and 56 are constant current sources of the two-phase input differential amplifier.

The operation of the quadrature modulator configured as shown in FIGS. 1, 2 and 3 will be described below.

First, the carrier inputted from the carrier input terminal 11 is supplied to the 90 ° distributor 15 to have a phase difference of 90 °.
Distributed to signals. The carrier signals distributed with a phase difference of 90 ° are amplified by output saturation circuits 16 and 17 until the output is saturated, and shaped into a rectangular wave having a constant amplitude. The carrier signal shaped into a rectangular wave and having a constant amplitude is multiplied by the modulated baseband signals input from the in-phase signal input terminal 13 and the quadrature signal input terminal 14 in the double balance mixers 18 and 19. The in-phase and quadrature modulated signals multiplied by the carrier are directly synthesized, and the image components are canceled at this time. The combined two outputs are input to the differential buffer amplifier 20, but the carrier component and
Harmonic components generated in the output saturation circuit become in-phase inputs and are suppressed here. Thus,
At the output, two output signals modulated in accordance with the modulation baseband signal are obtained, and are taken out from the output terminal 12.

Next, the resistance and MI, which are the main parts of the quadrature modulator, are shown.
The operation of the 90 ° distributor 15 constituted by a calculus circuit having a capacity of M structure and the output saturation circuit 16 constituted by one stage of a single-phase input differential amplifier and one stage of a two-phase input differential amplifier will be described. The 90 ° distributor 15 includes resistors 25 and 26
And a calculus circuit composed of the capacitors 27 and 28 having the MIM structure so as to ensure symmetry. Although the power supply voltage is applied via the resistor 34 in order to reduce the capacitance 31 between sub-subs, which promotes the reduction of the carrier signal level, no current is consumed. The output saturation circuit 16
(4) It plays a role of compressing the amplitude error between the in-phase component and the quadrature component due to the variation of the resistance value and the capacitance value caused by the variation of the semiconductor manufacturing process generated by the distributor 15 and the frequency change. Transistors 38 and 39 , load resistor 40,
An input signal is amplified and saturated by a first-stage high-gain single-phase input differential amplifier comprising a constant current source 42 and the like, and the following components comprising transistors 43 and 44 , load resistors 45 and 46 , constant current sources 48 and 49, etc. The waveform is shaped by the two-phase input differential amplifier of the stage to have a constant amplitude. As described above, since the amplitude error between the in-phase component and the quadrature component can be compressed, a sufficient image suppression ratio can be secured over a wide frequency range, so that a quadrature modulator with good modulation accuracy over a wide band can be realized. Also, since both amplifiers are internal circuits of the IC, high impedance connection with a load can be realized, and it can be realized with low current consumption.

Next, the operation of the differential output buffer amplifier 20 will be described. Transistors 50 and 51 and additional resistor 5
In the differential output buffer amplifier 20 composed of 2, 53, etc.,
The carrier component and the even-order distortion component which become the in-phase input are suppressed and modulated in accordance with the modulation baseband signal.
An output signal of the system is obtained and extracted from the output terminal 12.

As described above, according to the present embodiment, the half is performed.
Alternatively, a change in resistance, capacitance, and carry caused by variations in the semiconductor manufacturing process can be performed with less current consumption than a 90 ° divider configured using a quarter frequency divider.
A) It is possible to compress the amplitude error between the in-phase component and the quadrature component due to the change in the frequency, and to secure a sufficient image suppression ratio, thereby realizing a quadrature modulator with good modulation accuracy over a wide band . In addition, the suppression effect on the in-phase input
Because a differential output amplifier is used together,
In the suppression characteristics of harmonic components generated in the output and saturation circuits
An excellent quadrature modulator can be realized.

Embodiment 2 Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a block diagram of a quadrature modulator according to a second embodiment of the present invention, and FIG. 5 is a 90 ° distributor and output saturation, which are main parts of the quadrature modulator according to the second embodiment of the present invention. FIG. 6 shows a detailed circuit as an embodiment of the circuit, and FIG. 6 shows a detailed circuit as an embodiment of the single-system output buffer amplifier. 4 is different from the configuration of FIG. 1 in that a capacitor constituting a 90 ° distributor is formed by a collector of a transistor and a base-to-base capacitance, and that a two-phase input differential amplifier constituting an output saturation circuit is used. The point is that the modulation output terminal is made into one system and the configuration of the output buffer amplifier is changed.

In FIG. 4, reference numeral 61 denotes a carrier input terminal;
Reference numeral 62 denotes a modulation output terminal, 63 denotes an in-phase signal input terminal of a modulation base band signal, 64 denotes a quadrature signal input terminal of the modulation base band signal, 65 denotes a 90 ° distributor for dividing a carrier into two, and 66 and 67 output. A saturation circuit, 68 is a double balance mixer (DBM) for in-phase signals, 69 is a double balance mixer (DBM) for quadrature signals, and 70 is an output buffer amplifier comprising a differential amplifier 71 and a buffer amplifier 72.

FIG. 5 is a view showing a main part of FIG.
5 and details of the output saturation circuits 66 and 67. More specifically, a 90 ° divider 6 composed of a calculus circuit composed of a resistor, a collector of a transistor, and a base-to-base capacitance.
5, and output saturation circuits 66 and 6 each comprising one stage of a single-phase input differential amplifier and two stages of a two-phase input differential amplifier thereafter.
7 shows a detailed circuit as a seventh embodiment. In addition,
The output saturation circuit 67 is omitted because it is the same as the output saturation circuit 66.

In FIG. 5, reference numeral 73 denotes a power supply voltage terminal;
Is a control terminal, 75 is a bias terminal, 76 and 77 are output terminals of an output saturation circuit 66, 78 and 79 are resistors forming a calculus circuit, 80 and 81 are transistors forming a calculus circuit, and 82 and 83 are DC blocking. MIM capacity, 84, 85
Is the capacitance between the MIM capacitor and the sub, and 86 is the transistor 8
Bias resistors for supplying voltages for controlling the collectors 0 and 81 and the base-to-base capacitance; 87 to 89 are resistors and capacitors for determining the base bias of the transistors 90 and 91 constituting the single-phase input differential amplifier; Reference numerals 92 and 93 denote load resistances of the single-phase input differential amplifier, 94 denotes a constant current source of the single-phase input differential amplifier, 95 to 98 denote transistors constituting the two-phase input differential amplifier, and 99 to 102 denote the two-phase input differential amplifier. 103, a resistor connected to the emitters of the transistors 95 and 96; 104, a resistor connected to the emitters of the transistors 97, 98; and 105 to 108, constant current sources of the two-phase input differential amplifier. .

FIG. 6 shows a differential amplifier 71 which is a main part of FIG.
3 shows a detailed circuit as an embodiment of an output buffer amplifier 70 composed of a buffer amplifier 72 and a buffer amplifier 72. 109 is a bias terminal, 110 and 111 are transistors constituting a two-phase input differential amplifier, 112 and 113 are load resistances of the two-phase input differential amplifier, and 114 is transistors 110 and 111
, 115 and 116 are constant current sources of a two-phase input differential amplifier, 117 is a transistor for directly inputting the output signal of the differential amplifier 71, and 118 is the other output signal of the differential amplifier 71. Input transistor,
119 is a DC blocking capacitance, 120 is a base bias resistor,
121 is an emitter resistance.

The operation of the quadrature modulator configured as described above will be described below. In FIG. 4, since the basic operation as a quadrature modulator is the same as that of FIG. 1, detailed description will be omitted. However, the difference from the configuration of FIG. The difference is that the two-phase input differential amplifier constituting the output saturation circuit has two stages, the modulation output terminal is one system, and the configuration of the output buffer amplifier is changed.

First, the operation of the 90.degree. Divider 65, which is a main part of the quadrature modulator, and the output saturation circuits 66 and 67 composed of one stage of a single-phase input differential amplifier and two stages of a two-phase input differential amplifier will be described. I do. The 90 ° distributor 65 has the capacity shown in FIG.
Instead of the MIM capacitor shown in FIG. 7, the transistor is formed by the collector of the transistor and the capacitance between the bases, and constitutes a calculus circuit together with the resistors 78 and 79. The voltage applied to the control terminal 74 is applied to the transistor 8 via the bias resistor 86.
The collector and base capacitances of 0 and 81 are controlled. The capacitance value is varied by the voltage applied to the control terminal 74, and the output via the MIM capacitors 82 and 83 at a desired frequency is made constant. The function of the output saturation circuit 66 is the same as that of the embodiment shown in FIG. 2, except that two-phase input differential amplifiers connected after the input stage are provided in two stages to more completely shape the waveform. The output saturation circuit 67 is the same as 66, and a description thereof will be omitted.

Next, the differential amplifier 71 and the output buffer amplifier 7
2 will be described. Transistors 110 and 111 and load resistors 112 and 1
13 and the like, the carrier component serving as the in-phase input and its harmonic components are suppressed. Since the output is of one system unlike the embodiment shown in FIG. 3, by combining both inverted outputs of the differential amplifier 71, a modulated output signal with lower distortion than that of a normal emitter follower can be obtained. It is taken out from the output terminal 62.

As described above, by simplifying the internal circuit configuration of the output buffer amplifier 70 , it is possible to reduce the current consumption while maintaining the basic performance of the buffer amplifier.

(Embodiment 3) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 7 shows a detailed circuit as an embodiment of a 90 ° divider and an output saturation circuit which are the main parts of the quadrature modulator, and FIG.
Is a detailed circuit as an embodiment of a single-system output buffer amplifier,
FIG. 9 shows a detailed circuit as an embodiment of a two-system output buffer amplifier. The difference from the configurations of the first and second embodiments is that a function as a low-pass filter is added to the output of the two-phase input differential amplifier constituting the output saturation circuit, and the differential amplifier constituting the output buffer amplifier is provided. The difference is that a function as a low-pass filter is added to the output of the amplifier.

FIG. 7 shows a detailed circuit as an embodiment of the 90 ° distributor and the output saturation circuit. The 90 ° distributor 65 uses the capacitance of the MIM structure as the capacitance shown in FIG. 2, and the same numbers as those in FIG. 2 perform the same functions as the elements in FIG. 2. Output saturation circuit 66 has the same single-phase input differential amplifier first stage, both phases input differential amplifier 2 stage and FIG. Numbers are the same ones are those that are equivalent to the elements of FIG. Reference numerals 122 and 123 denote capacitors constituting a low-pass filter with the load resistance of the final-stage two-phase input differential amplifier.

FIG. 8 shows a differential amplifier 71 and a buffer amplifier 72.
3 shows a detailed circuit as an embodiment of the output buffer amplifier 70 composed of the above. 6 have the same functions as those in FIG. Reference numerals 124 and 125 denote capacitances constituting a low-pass filter with the load resistance of the differential amplifier 71. The transistor 126 and the current source 127 shift the DC voltage of the output of the differential amplifier 71, and
8 is a component that constitutes a level shift circuit for supplying the signal to the control circuit 8.

FIG. 9 shows a detailed circuit as an embodiment of the differential amplification type output buffer amplifier 20. The difference from the configuration of FIG. 3 is that the output is not output directly from the load of the differential amplifier but is output via an emitter follower. The same numbers as those in FIG. 3 have the same functions. However, since the current is not directly output from the load of the differential amplifier, the current flowing through the current sources 55 and 56 is small. 128, 129
A capacitance constituting a low-pass filter with the load resistance of the differential amplifier, transistors 130 and 131, current sources 132 and
Reference numeral 33 denotes an element constituting a level shift circuit for shifting the DC voltage output from the differential amplifier, and reference numerals 134 and 135 denote internal resistances of the transistors 130 and 131 and a capacitance constituting a low-pass filter.

The operation of the quadrature modulator configured as described above will be described below. The operation of the 90 ° splitter 65, which is a main part of the quadrature modulator shown in FIG. 7, and the output saturation circuits 66 and 67 composed of one stage of a single-phase input differential amplifier and two stages of a dual-phase input differential amplifier will be described. . The basic operation of the 90 ° splitter and a detailed description thereof will be omitted because it is the same as FIG. The basic operation of the output saturation circuit is the same as that of the embodiment shown in FIG. 5, but a capacitor is added to the output of the final-stage two-phase input differential amplifier, and a low-pass filter is constituted by the load resistance.
By configuring the low-pass filter, it is possible to attenuate harmonics generated in the output saturation circuit.

Next, the operation of the output buffer amplifier 70 including the differential amplifier 71 and the output buffer amplifier 72 shown in FIG. 8 will be described. Since the configuration of the differential amplifier 71 is the same, the description is omitted.
6 and a current source 127 are supplied to a transistor 118 via a level shift circuit composed of a signal input to the transistor 117 and a signal whose phase is inverted. The modulated output signal is obtained from the output terminal 62.

Next, the operation of the differential amplification type output buffer amplifier 20 shown in FIG. 9 will be described. The difference from the configuration of FIG. 3 is that the output is of course two systems,
The point is that the function of the low-pass filter is provided in two places, the output of the differential amplifier and the output of the emitter follower. Although the description of the configuration of the differential amplifier is omitted because it is the same, a low-pass filter including load resistors 52 and 53 and capacitors 128 and 129 is provided at the output of the differential amplifier . Carrier component and output saturation
The harmonic components generated by the sum circuit are converted by the differential buffer amplifier.
To a certain extent, but constitute a low-pass filter
As a result, higher harmonic components can be further attenuated. Further, transistors 130 and 131 and current sources 132 and 1
The DC level is shifted and output via a level shift circuit comprising 33 so as to be convenient for connection to the next stage. Capacitors 134 and 135 are also added to the output stage, and a low-pass filter function is realized by the internal resistance of the transistors 139 and 131, and the harmonics generated in the output saturation circuit are further attenuated.

As described above, the in- phase input component is suppressed.
By using an effective differential output saturation circuit and incorporating the function of a low-pass filter in the output saturation circuit and output buffer amplifier, the harmonics generated in the output saturation circuit are attenuated, and the modulation accuracy over a wide band is improved. A quadrature modulator with high harmonics suppressed can be realized.

In the first and second embodiments, the output saturation circuit and the circuit using a transistor as the output buffer amplifier have been described. However, it goes without saying that the active element is not limited to this. Further, in the third embodiment, an example in which the low-pass filter function is incorporated in both the output saturation circuit and the output buffer amplifier has been described, but it goes without saying that either one may be used.

[0041]

As described above, according to the present invention, by adding an output saturation circuit to the next stage of a 90 ° divider for a quadrature modulator, the resistance and capacitance values caused by variations in the semiconductor manufacturing process with small current consumption can be obtained. Change and carrier frequency
Since the amplitude error between the in-phase component and the quadrature component due to the change can be compressed and a sufficient image suppression ratio can be secured, a quadrature modulator with excellent modulation accuracy and a wide band can be realized.
You. In addition, it suppresses common-mode input components as an output circuit.
High-precision, high-bandwidth quadrature modulator that suppresses carriers and their harmonic components by incorporating a low-pass filter function into the output saturation circuit and output buffer amplifier using an effective differential output buffer amplifier . Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a quadrature modulator according to a first embodiment of the present invention.

FIG. 2 is a main part circuit diagram of the quadrature modulator according to the first embodiment of the present invention.

FIG. 3 shows a quadrature modulator 2 according to the first embodiment of the present invention.
Output buffer amplifier circuit diagram

FIG. 4 is a block diagram of a quadrature modulator according to a second embodiment of the present invention;

FIG. 5 is a main part circuit diagram of a quadrature modulator according to a second embodiment of the present invention.

FIG. 6 illustrates a quadrature modulator according to a second embodiment of the present invention.
Output buffer amplifier circuit diagram

FIG. 7 is a main part circuit diagram of a quadrature modulator according to a third embodiment of the present invention.

FIG. 8 shows a quadrature modulator according to a third embodiment of the present invention.
Output buffer amplifier circuit diagram

FIG. 9 illustrates a second example of the quadrature modulator according to the third embodiment of the present invention.
Output buffer amplifier circuit diagram

FIG. 10 is a block diagram of a conventional quadrature modulator.

[Explanation of symbols]

11, 61 Carrier input terminal 12, 62 Modulation output terminal 13, 63 In-phase signal input terminal for modulated base band signal 14, 64 Quadrature signal input terminal for modulated base band signal 15, 65 90 ° distribution for dividing carrier into 2 Amplifier 16, 17, 66, 67 Output saturation circuit 18, 68 Double balance mixer for in-phase signal (DB
M) 19, 69 Double balance mixer for orthogonal signals (DB
M) 20 differential output buffer amplifier 70 output buffer amplifier

Continuation of front page (56) References JP-A-6-232925 (JP, A) JP-A-6-104675 (JP, A) JP-A-5-347529 (JP, A) JP-A-5-75658 (JP) JP-A-4-34938 (JP, A) JP-A-5-48662 (JP, A) K Yamamoto, "A 1.9 GHz-Band GaAs Direct-Quadrature Modulator IC", GaAs IC SYMICONUM L DIgest 1992, October 1992, p. 37-40 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 27/00-27/38 H03H 7/18 H03H 7/21

Claims (2)

(57) [Claims] 1. A 90 ° splitter for splitting a carrier into two,
An output saturation circuit for amplifying and saturating the output of the 90 ° divider; first and second double balance mixers for multiplying the output of the output saturation circuit with in-phase and quadrature modulation baseband signals; 1, the output of the second double balanced mixer to synthesize, and an output buffer amplifier for suppressing the carrier component and harmonic components thereof, wherein the 90 ° distributor has a capacity of resistance and MIM structure
It is composed of a calculus circuit to help reduce the carrier signal level.
In order to reduce the capacitance between sub
A source voltage is applied, and the output saturation circuit includes one stage of a single-phase input differential amplifier,
Connect at least one stage of the two-phase input differential amplifier in the subsequent stage
The output buffer amplifier comprises a differential amplifier and a two-input one-output buffer.
The two-input one-output buffer amplifier is
The two inverted outputs of the differential amplifier at the stage
The resulting, the output saturation circuit and said output buffer amplifier, therein
That has a built-in low-pass filter function
Intermodulator . 2. The capacity of a 90 ° distributor is MIM.
2. The quadrature modulator according to claim 1, wherein a capacitance between a base collector and a base emitter of the transistor is used instead of the structure .