JP2000196364A - Frequency converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency converting circuit for simultaneously realizing the reduction in the voltage, current, and noise and a high conversion gain, and for reducing the deterioration of a noise figure against the fluctuation of a local oscillation signal. SOLUTION: In this frequency converting circuit 100, output of thermal noise generated from eighth and ninth resistances 18 and 19 connected with the bases of the second and third differential transistor pairs 12 and 13 is multiplied by a difference in gain between second and third differential transistor pairs 12 and 13, then the influence of the thermal noise generated from the eighth and ninth resistances 18 and 19 is offset and does not appear in the output when the gains of the second and third transistor pairs 12 and 13 are made equal. That is, the load resistances of the second and third differential transistor pairs 12 and 13 are adjusted so that the gains of the second and third differential transistor pairs 12 and 13 can be made equal. Thus, any thermal noise signal generated by the eighth and ninth resistances 18 and 19 can not be outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency conversion circuit used for a cellular phone, a television, a VTR, etc., and more particularly, to a frequency conversion circuit realizing low voltage, low current, low noise and high conversion gain. Circuit.

[0002]

2. Description of the Related Art There are two types of conventional frequency conversion circuits, a single balance type and a double balance type. Hereinafter, each type of frequency conversion circuit will be described.

FIG. 10 is a diagram showing a conventional single balance type frequency conversion circuit. In the figure, a single balance type frequency conversion circuit 1000 includes a transistor Q2
And a transistor Q3 and a differential transistor pair 101 having a common emitter, a bias resistor R4 connected to the base of the transistor Q2, and a transistor Q3.
A first DC power supply V113 connected to the base of the transistor Q2 via the bias resistor R4 and connected to the base of the transistor Q3 via the bias resistor R5; A resistor R2 connected to the collector of Q2, a resistor R3 connected to the collector of transistor Q3,
A first DC power supply V112 connected to the collector of the transistor Q2 via the second transistor 2 and to the collector of the transistor Q3 via the resistor R3; and a transistor Q1 connected to the collector with the common emitter of the differential transistor pair 101 connected to the collector. And a resistor R1 connected to the base of the transistor Q1, and a first DC power supply V111 connected to the base of the transistor Q1 via the resistor R1.

[0004] A local oscillation signal source 103 is connected to the base of the transistor Q2 via a capacitor C2 to supply a local oscillation signal LO. Further, a carrier signal source 105 is connected to the base of the transistor Q1 via a capacitor C1, and the carrier signal RF is supplied.

In the conventional single-balanced frequency conversion circuit 1000 having such a configuration, the carrier signal RF and the local oscillation signal LO are integrated, and the transistors Q2, Q
3 is a first output terminal out1 and a second output terminal out2, respectively, and the first and second output terminals out1 and out2 have a difference and a sum of the carrier signal RF and the local oscillation signal LO, respectively. Is output.

FIG. 11 is a diagram showing a conventional double-balanced frequency conversion circuit. In the figure, a double balance type frequency conversion circuit 1100 has a transistor Q6 and a transistor Q7 as a pair and a second differential transistor pair 112 having a common emitter, and a transistor Q8 and a transistor Q9 as a pair and having a common emitter. The third differential transistor pair 113 and the transistor Q
6, a bias resistor Ra connected to the base of Q9, a bias resistor Rb connected to the bases of transistors Q7 and Q8, and a transistor Q via a bias resistor Ra.
6, a first DC power supply V113 connected to the bases of transistors Q7, Q8 via a bias resistor Rb, a resistor R8 connected to the collectors of transistors Q6, Q8, and a transistor Q7. , Q
A first DC power supply V112 connected to the collectors of the transistors Q6 and Q8 via the resistor R8 and to the collectors of the transistors Q7 and Q9 via the resistor R9; A transistor Q4 having a common emitter connected to the collector of the second differential transistor pair 112 and a third differential transistor pair 1
A first differential transistor pair 111 in which the transistor Q5 whose thirteen common emitters are connected to the collector forms a pair and has a common emitter, a resistor R6 connected to the base of the transistor Q5, and a base connected to the base of the transistor Q4. A first DC power supply V111 connected to the base of the transistor Q5 via the resistor R6 and to the base of the transistor Q4 via the resistor R7,
And a current source 107 connected to the common emitter of the first differential transistor pair 111. Also,
The bases of the transistors Q7 and Q8 are AC grounded via a capacitor C3.

A local oscillation signal source 103 is connected to the base of the transistor Q6 via a capacitor C2, and a local oscillation signal LO is supplied. Further, a carrier signal source 105 is connected to the base of the transistor Q2 via a capacitor C1, and the carrier signal RF is supplied.

In the conventional double-balanced frequency conversion circuit 1100 having such a configuration, the carrier signal RF and the local oscillation signal LO are integrated as in the single-balanced frequency conversion circuit 1000, and the collectors of the transistors Q6 and Q9 are collected. To the first output terminal out1 and the second output terminal
, The first and second output terminals out1 and out2 are connected to the carrier signal RF, respectively.
A signal having a difference and a sum frequency component between the signal and the local transmission signal LO is output.

[0009]

However, in the conventional single-balanced frequency conversion circuit 1000 described above,
High conversion gain and good noise figure (Noise Figure: N
F) is good, but the transistor Q
2 and Q3, each of which has a bias resistor R connected to its base.
Thermal noise generated from the first and second output terminals out1 and out2 is amplified by the thermal noise generated from the first and second output terminals out1 and out2, which causes NF deterioration, and the resistance values of the bias resistors R4 and R5 cannot be increased.

As described above, since the impedance of the local oscillation signal LO input portion of the single balance type frequency conversion circuit 1000 is low, when an amplifier or the like is connected to the base of the transistor Q2 before the input of the local oscillation signal LO, the local oscillation signal is converted. There is a problem that a loss of the signal LO level is likely to appear. In addition, since the NF deteriorates remarkably due to the fluctuation of the local oscillation signal LO due to temperature, voltage fluctuation, element fluctuation, etc., there is also a problem that the NF of the whole system is affected.

The conventional double-balanced frequency converter 1100 proposed to improve the problem of the single-balanced frequency converter 1000 has the following features.
Transistors Q6, Q9 and transistors Q7, Q8
Noise generated from the bias resistors Ra and Rb respectively connected to the bases of the first and second output terminals out
At 1 and out2, they do not appear offset. Therefore, since the resistance values of the bias resistors Ra and Rb can be increased, even when an amplifier or the like is connected as a preceding stage of the input of the local oscillation signal LO, the loss of the local oscillation signal LO level can be suppressed to a small value. The amount of deterioration of the NF with respect to the fluctuation of the transmission signal LO is smaller than that of the single balance type frequency conversion circuit 1000. However, the double balance type frequency conversion circuit 1100 has a problem that the conversion gain is low and the NF is high as compared with the single balance type frequency conversion circuit 1000 at the same level of operating current. Further, the current source 107 is required for the constant current operation, so that the operating voltage becomes high, which is not suitable for lowering the voltage.

The present invention has been made in view of the above circumstances and problems, and realizes low voltage, low current, low noise, and high conversion gain at the same time, and suppresses the fluctuation of the local oscillation signal LO. It is another object of the present invention to provide a frequency conversion circuit capable of minimizing deterioration of a noise figure (NF).

[0013]

In order to solve the above-mentioned problems, a frequency conversion circuit according to a first aspect of the present invention comprises a first transistor and a second transistor having a common emitter and having different emitter areas. And a second differential transistor pair having a third transistor and a fourth transistor having a common emitter and having the common emitter connected to the collector of the first transistor. And the fifth with a common emitter
And a sixth transistor, the common emitter being connected to the collector of the second transistor, the bases of the third transistor and the sixth transistor being connected respectively, and the fifth transistor being connected to the third transistor. A third differential transistor pair having a base connected to the base of the fourth transistor, and a third differential transistor pair connected to the collectors of the third and fourth transistors and the collectors of the fifth and sixth transistors, respectively. And a second load resistor connected to the collectors of the fifth and sixth transistors, respectively.
And the resistance value of the second load resistor is adjusted according to the emitter area ratio of the first transistor and the second transistor, so that the transfer conductance of the second differential transistor pair and the first and second And the product of the transfer conductance of the third differential transistor pair and the product of the second load resistance value are equalized.

Further, the frequency conversion circuit according to claim 2 is
A first differential transistor pair having a first transistor and a second transistor having a common emitter and different emitter areas, respectively, and a third differential transistor having a common emitter;
And a fourth transistor having a common emitter connected to the collector of the first transistor, and a fifth transistor and a sixth transistor having a common emitter. The common emitter is connected to the collector of the second transistor, the base of the sixth transistor is connected to the base of the third transistor, and the base of the fifth transistor is connected to the base of the fourth transistor. A first differential transistor pair having a third differential transistor pair connected to the base, a fourth resistor connected to the collector of the third transistor, and a sixth resistor connected to the collector of the fourth transistor; A load resistor, a fifth resistor connected to the collector of the fifth transistor, and a collector of the sixth transistor; Second having a seventh resistor, which is continued
, A capacitor and a first resistor respectively connected to a common emitter of the first differential transistor pair, and a second resistor connected to a base of the first transistor via a third resistor. A first power supply connected to the base of the second transistor via the resistor of the second transistor, a collector of the sixth transistor via the seventh resistor, the seventh resistor and the sixth resistor. Through the fourth
And the collector of the fifth transistor
A collector of the fifth transistor through a resistor of
A second power supply connected to the collector of the third transistor via the fifth resistor and the fourth resistor, and the third transistor and the sixth transistor via an eighth resistor And a third power supply connected to the bases of the fourth transistor and the fifth transistor via a ninth resistor,
A first signal is supplied to a base of the second transistor, and a second signal is supplied to a base of the third transistor and the sixth transistor, and a collector of the third and fourth transistors is supplied. A frequency conversion circuit for obtaining an output, wherein a resistance value of said fourth to seventh resistors is adjusted according to an emitter area ratio of said first transistor and said second transistor, and said second difference The product of the transmission conductance of the dynamic transistor pair and the first load resistance value and the second load resistance value is equal to the product of the transmission conductance of the third differential transistor pair and the second load resistance value. It is characterized by the following.

The frequency conversion circuit according to claim 3 is
3. The frequency conversion circuit according to claim 1, wherein an emitter area of the second transistor is larger than an emitter area of the first transistor.

The frequency conversion circuit according to claim 4 is
The frequency conversion circuit according to claim 1, 2 or 3,
A plurality of differential transistor pairs connected in parallel to the first differential transistor pair, each including two transistors, and connected in parallel with each other; and optionally, the first differential transistor pair and the plurality of differential transistor pairs. And a switch for operating one of the differential transistor pairs effectively.

Further, a frequency conversion circuit according to claim 5 is
5. The frequency conversion circuit according to claim 1, wherein the connection point between the emitter of the first transistor and a common emitter of the first differential transistor is connected to the emitter of the second transistor. A resistor is provided between each connection point of the emitters and between each connection point serving as a common emitter of each of the plurality of differential transistors and the emitter of each transistor of the plurality of differential transistor pairs.

The frequency conversion circuit according to claim 6 is
6. The frequency conversion circuit according to claim 4, wherein an attenuating means for attenuating a signal level is connected to one base of the plurality of differential transistor pairs.

The frequency conversion circuit according to claim 7 is
7. The frequency conversion circuit according to claim 1, further comprising an amplifier connected to a base of said third and sixth transistors or a base of said fourth and fifth transistors. It is characterized by.

Further, the frequency conversion circuit according to claim 8 is:
8. The frequency conversion circuit according to claim 7, wherein said amplification means is a differential amplifier, a common emitter amplifier, or a cascode amplifier.

Further, a frequency conversion circuit according to claim 9 is
8. The frequency conversion circuit according to claim 7, wherein said amplification means has a ninth transistor and a first transistor having a common emitter.
0 is a differential amplifier having a transistor of
Alternatively, a collector of the tenth transistor is connected to a base of the third and sixth transistors or a base of the fourth and fifth transistors.

A frequency conversion circuit according to a tenth aspect is the frequency conversion circuit according to the ninth aspect.
Alternatively, the collector of the tenth transistor is connected to the base of the third and sixth transistors, and the collector of the ninth or tenth other transistor is connected to the base of the fourth and fifth transistors. It is characterized by.

The frequency conversion circuit according to claim 11 is the frequency conversion circuit according to claim 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10, wherein the first differential transistor A current source connected to the pair of common emitters is provided.

According to a twelfth aspect of the present invention, in the frequency conversion circuit of the eleventh aspect, the current source is a combination of a first resistor and a capacitor or a current mirror circuit and the capacitor. And

The frequency conversion circuit according to the thirteenth aspect is characterized in that the frequency conversion circuit according to the thirteenth aspect has the following features.
13. The frequency conversion circuit according to 0, 11, or 12, further comprising: a thirteenth transistor having a base and a collector connected to each other, wherein the bases of the first and second transistors are connected to a base and a collector of the thirteenth transistor. It is characterized by having.

Further, the frequency conversion circuit according to claim 14 is a frequency conversion circuit according to claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 1
14. The frequency conversion circuit according to 0, 11, 12 or 13, wherein the transistors included in the first to tenth transistors or the plurality of differential transistor pairs are field effect transistors.

In the frequency conversion circuit according to the first and second aspects of the present invention, the first and second transistors have different emitter area ratios, and the first and second transistors have different emitter area ratios.
By adjusting the respective resistance values of the load resistors according to the emitter area ratio, the gain of the second differential transistor pair is made equal to the gain of the third differential transistor pair. In particular, in the frequency conversion circuit according to claim 2,
By adjusting the resistance value of the seventh resistor, the product of the transfer conductance of each differential transistor pair and the load resistance value,
That is, the gains are made equal.

When a bias resistor is connected to the bases of the second and third differential transistor pairs, a thermal noise signal generated from the bias resistor causes an output of the second differential transistor pair and the third differential transistor pair at the output. Is multiplied by the gain difference between the second differential transistor pair and the third differential transistor pair, and if the gains of the second differential transistor pair and the third differential transistor pair are equal, the effect of the thermal noise generated by the base bias resistor will be affected by the output. It doesn't show up offset. Further, since the gain of the differential transistor pair is generally determined by the transfer conductance and the load resistance, the load resistance of each of the second differential transistor pair and the third differential transistor pair is set to the second and third differential transistor pairs. By adjusting the gain of the differential transistor pair to be equal, the thermal noise signal generated by the base bias resistor is not output. Therefore, since the resistance value of the base bias resistor can be increased,
The gain of the second and third differential transistor pairs can be set high, and high-gain conversion of signals in the frequency conversion circuit can be realized. Further, by setting the resistance value of the base bias resistor to be high, the input impedance on the base side of the third and sixth transistors can be set to be high. Degradation can be kept small.

Further, in the frequency conversion circuit according to the first and second aspects, for example, by flowing the emitter area of the first transistor smaller than the emitter area of the second transistor, the current flows through the first differential transistor pair. Since the current can be reduced, the power consumption of the entire system can be reduced. Therefore, since the frequency conversion circuit can be operated at a relatively low operating voltage, a reduction in voltage can be realized, and a reduction in the current supplied to the frequency conversion circuit can be realized.

In particular, in the frequency conversion circuit according to the second aspect, the first signal (carrier signal) is supplied to the base of the second transistor by using the base bias resistors as the eighth and ninth resistors, and A second signal (local oscillation signal) is supplied to the base of the transistor, a frequency-converted signal is output from the collectors of the fifth and sixth transistors, and third and fourth signals are output from the frequency-converted output. The negative phase components of the noise are added from the collectors of the transistors to cancel the noise. That is, by connecting the second differential transistor pair, the thermal noise generated from the base bias resistor is added to cancel the in-phase component and the negative-phase component, so that the noise does not appear at the output.

Summarizing the above, according to the frequency conversion circuit according to the first and second aspects, it is possible to reduce the voltage and the current regardless of the magnitude of the base bias resistance of the second signal (local oscillation signal) input. In addition, it is possible to provide a frequency conversion circuit that can simultaneously realize low noise and high conversion gain, and can suppress deterioration of the noise figure to a small degree even when the input signal on the base bias resistor side fluctuates.

Further, in the frequency conversion circuit according to claim 3, the emitter area of the second transistor is made larger than the emitter area of the first transistor. Accordingly, the operating current flowing through the first transistor can be reduced, so that the power consumption of the frequency conversion circuit can be suppressed, and the voltage and current of the circuit can be reduced.

In the frequency conversion circuit according to the fourth aspect, a plurality of differential transistor pairs each having two transistors and connected in parallel with each other are connected in parallel to the first differential transistor pair. A switch for effectively operating one differential transistor pair and one of the plurality of differential transistor pairs is provided, and a differential transistor pair to be used is selected by switching the switch.
In such a configuration, by setting the conversion gain for each differential transistor pair to be different, the conversion gain of the differential transistor that operates effectively can be selected, so that the conversion gain can be changed in many patterns. Becomes

In the frequency conversion circuit according to the fifth aspect, for example, in the first differential transistor pair, an emitter of the first transistor and a connection point serving as a common emitter of the first differential transistor pair are connected. A tenth resistor is connected therebetween, and an eleventh resistor is connected between the emitter of the second transistor and the connection point. Tenth and eleventh
By adjusting the resistance value of the second resistor, the second and third
Can be determined, the distortion characteristics of the frequency conversion circuit can be improved. The same applies to a plurality of differential transistor pairs such as a fourth differential transistor pair connected in parallel to the first differential transistor pair.

Further, in the frequency conversion circuit according to the sixth aspect, attenuating means for attenuating the level of a signal input to the base of one of the plurality of differential transistor pairs connected in parallel is connected. Accordingly, the signal level of the first signal (carrier signal) having a large signal level can be reduced, so that the first signal (carrier signal) can be linearly processed over a wide range. Become.

Further, the frequency conversion circuit according to the seventh, eighth and ninth aspects includes amplification means connected to the bases of the third and sixth transistors or the fourth and fifth transistors, and the second signal ( The local oscillation signal is amplified and supplied to the second and third differential transistor pairs. In particular, in the frequency conversion circuit according to claim 8, the amplifying means includes:
Preferably, it is a differential amplifier, a common emitter amplifier or a cascode amplifier. In particular, in the frequency conversion circuit according to claim 9, the amplifying means is a differential amplifier having ninth and tenth transistors having a common emitter, and the collector of the ninth or tenth transistor is a third amplifier.
And the base of the sixth transistor or the fourth and fifth transistors. Thus, when the level of the second signal (local oscillation signal) input to the bases of the third and sixth transistors is low, the level of the input signal can be amplified and input to the base. Become. As described above, in the frequency conversion circuit of the present invention,
Since the resistance value of the base bias resistance of the second and third differential transistor pairs can be increased, it is not necessary to consider the base bias resistance of the parallel connection as the load resistance of the amplification means. Design can be performed easily.

Further, in the frequency conversion circuit according to the tenth aspect, the collector of the ninth or tenth transistor is connected to the third transistor.
And the collectors of the ninth and tenth other transistors were connected to the bases of the fourth and fifth transistors. This allows the differentially amplified second signal (local oscillation signal) to be input to the second and third differential transistor pairs, thereby reducing the DC offset voltage at the output of the frequency conversion circuit. Becomes possible. Note that the bases of the fourth transistor and the fifth transistor do not need to be grounded in an alternating manner, so that the number of elements can be reduced.

Further, in the frequency conversion circuit according to the eleventh and twelfth aspects, the current source is connected to the common emitter of the first differential transistor pair. A first resistor and a capacitor,
Alternatively, it is desirable to use a combination of a current mirror circuit and a capacitor. Thus, the operation current flowing through the first differential transistor pair can be stabilized, and the constant frequency operation can be performed stably in the frequency conversion circuit.

Further, the frequency conversion circuit according to the thirteenth aspect includes a thirteenth transistor having a base and a collector connected to each other, wherein the bases of the first and second transistors are connected to the base and the collector of the thirteenth transistor. are doing. Therefore, the thirteenth transistor and the first
Transistors constitute a first current mirror circuit,
The thirteenth transistor and the second transistor are the second transistor
Of the current mirror circuit of FIG. Thus, the first current mirror circuit supplies a stable current to the common emitter of the second differential transistor pair, and the second current mirror circuit supplies a stable current to the common emitter of the third differential transistor pair. Since the supply can be performed, stable constant current operation can be performed in the frequency conversion circuit.

Further, in the frequency conversion circuit according to the fourteenth aspect, the first to tenth transistors or the transistors included in the plurality of differential transistor pairs are realized by using field effect transistors. Since the current flows between the drain and the source in proportion to the square of the gate voltage in the field-effect transistor, in addition to the effect of the frequency conversion circuit according to the above-described claims 1 to 13, the third-order intermodulation distortion is reduced. The effect of suppressing is also exerted.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a frequency conversion circuit according to the present invention will be described with reference to [first embodiment] and [second embodiment].
Embodiment], [Third Embodiment], [Fourth Embodiment], [Fifth Embodiment], [Sixth Embodiment], [Seventh Embodiment] in the following order: This will be described in detail.

[First Embodiment] FIG. 1 shows a first embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating a frequency conversion circuit according to the embodiment.
In the figure, the same reference numerals are given to the portions that overlap with the conventional technology (FIGS. 10 and 11). In FIG. 1, the frequency conversion circuit 100 according to the present embodiment includes a second differential transistor pair 1 in which a third transistor Q13 and a fourth transistor Q14 are paired and have a common emitter.
2, a third transistor pair 13 in which the fifth transistor Q15 and the sixth transistor Q16 are paired and have a common emitter, and a third differential transistor pair connected to the bases of the third and sixth transistors Q13 and Q16. 8 resistors R18
A ninth resistor R19 connected to the bases of the fourth and fifth transistors Q14 and Q15, and an eighth resistor R1
8, the third and sixth transistors Q13, Q1
A third DC power supply, which is connected to the base of the third power supply and connected to the bases of the fourth and fifth transistors Q14 and Q15 via the ninth resistor R19. V13.

The frequency conversion circuit 100 is connected to the fourth resistor R14 connected to the collectors of the third and fifth transistors Q13 and Q15, and to the collectors of the fourth and sixth transistors Q14 and Q16. A sixth resistor R16, a fifth resistor R15 connected to the collector of the fifth transistor Q15 and the fourth resistor R14, and a collector and a sixth resistor R of the sixth transistor Q16.
16, a seventh resistor R17 connected to the fourth and fifth resistors R17 and R16.
Connected to the collectors of the third and fifth transistors Q13 and Q15 via the resistors R14 and R15 of
And a second DC power supply V12 connected to the collectors of the fourth and sixth transistors Q14 and Q16 via the seventh resistors R16 and R17, and a common emitter of the second differential transistor pair 12 connected to the collector. A first differential transistor pair 11 having a common emitter of the first transistor Q11 and the third differential transistor pair 13 connected to the collector and a second transistor Q12 having a common emitter, A second resistor R12 connected to the base of the second transistor Q12, a third resistor R13 connected to the base of the first transistor Q11, and a second resistor R12 via the second and third resistors R12 and R13. And a first DC power supply V11 connected to the bases of the first transistors Q12 and Q11, and one end shared by the first differential transistor pair 11. It is connected to the emitter, and the other end is constituted by a capacitor C4 and a first resistor R11 which is grounded.

Further, the fourth and fifth transistors Q
The bases of the first and second transistors Q15 and Q15 are AC grounded via a capacitor C3.
The common emitters of Q11 and Q12 are grounded in an alternating manner by a capacitor C4, and grounded via a first resistor R11 serving as a current source. Note that bipolar transistors are used as the first to sixth transistors Q11 to Q16 of the present embodiment.

The base of the third transistor Q13 is connected to a local oscillation signal source 103 via a capacitor C2, and is supplied with a local oscillation signal (second signal) LO. Also, the base of the second transistor Q2 has
The carrier signal source 105 is connected via the capacitor C1, and a carrier signal (first signal) RF is supplied.

In the frequency conversion circuit 100 of this embodiment having such a configuration, the carrier signal RF and the local oscillation signal LO are integrated, and the third and fourth transistors Q1
3 and Q14 as first and second output terminals out1 and out2, respectively, the first and second output terminals out1 and out2 respectively provide the difference and sum of the carrier signal RF and the local oscillation signal LO. Is output.

In this embodiment, the first and second transistors Q11 and Q12 have different emitter area ratios, and the ratio of the area of the first transistor Q11 to the area of the emitter of the second transistor Q12 is 1: n.
Is set. Here, n is one or more real numbers. Accordingly, the operating current of the first transistor Q11: the operating current of the second transistor Q12 is also 1: n due to the emitter area ratio, and the operating current flowing through the second differential transistor pair 12 is equal to the third difference. Dynamic transistor pair 13
Than the operating current flowing through the

In this embodiment, when the thermal noise signal generated from the eighth resistor R18 is Vno, the thermal noise signal Vn
o is applied to the bases of the third and sixth transistors Q13 and Q16, respectively. When the differential transistor pair is considered as a differential amplifier, the voltage gain obtained from the second differential transistor pair 12 and the first and second loads is A2, and the third differential transistor pair 13 and the second Assuming that the voltage gain obtained from the load of the third transistor is A3, the thermal noise signal appearing at the collector of the third transistor Q13 is -A2 × Vno
And the thermal noise signal appearing at the collector of the fourth transistor Q14 is A2 × Vno. Similarly, the thermal noise signal appearing at the collector of the fifth transistor Q15 is A3 × Vno, and the thermal noise signal appearing at the collector of the sixth transistor Q16 is −A3 × Vno.

Therefore, the thermal noise signal appearing from the first output terminal out1 is transmitted to the third transistor Q13 and the fifth transistor Q13.
Is connected to the collector of the transistor Q15, the sum becomes (−A2 + A3) × Vno. On the other hand, the thermal noise signal appearing from the second output terminal out2 is
Fourth transistor Q14 and sixth transistor Q16
(A2-A)
3) × Vno. Therefore, the voltage gain A2 obtained from the second differential transistor pair 12 and the first and second loads and the voltage gain A3 obtained from the third differential transistor pair 13 and the second load are different. When equal, the respective thermal noise signals cancel each other out and the first and second
No signal due to the thermal noise of the eighth resistor R18 appears at the output terminals out1 and out2. The ninth resistor R
The thermal noise signal generated by the signal 19 is canceled out similarly to the eighth resistor R18, and does not appear at the output terminal.

In general, the voltage gain of a transistor is represented by gm × RL, where gm is the transconductance (or mutual conductance) and RL is the load resistance. The transfer conductance of each of the second differential transistor pair 12 and the third differential transistor pair 13 is gm
1 and gm2, and the fourth and sixth resistors R14 and R14.
Assuming that the combined resistance of the sixteenth resistor 16 is the first load resistor RL1 and the combined resistance of the fifth and seventh resistors R15 and R17 is the second load resistor RL2, the second differential transistor pair 12 and the third Of the differential transistor pair 13 are gm1 × (RL1 + RL2) and gm2
× RL2.

Since the thermal noise signals applied to the bases of the second differential transistor pair 12 and the third differential transistor pair 13 are the same, the ratio of the conductance = the ratio of the operating current = the ratio of the emitter area . Therefore, the second differential transistor pair 12 and the third differential transistor pair 1
In order to equalize the voltage gains of Nos. 3 and 3, the resistance values are determined so that the following equation (1) holds for the first and second load resistors RL1 and RL2.

[0052]

(Equation 1)

As described above, the first and second load resistances RL1, RL1 are determined based on the determined emitter area ratio of the first and second transistors Q11, Q12 and the equation (1).
RL2 is determined, that is, the fourth to seventh resistors R14 to R1
7 to determine the eighth and ninth resistors R1
The respective thermal noise signals generated at R8 and R19 do not appear because they are canceled at the first and second output terminals out1 and out2, and at the same time, the required operating current can be suppressed smaller than in the conventional case.

FIG. 2 shows, using a circuit simulator SPICE, the output level and the NF local oscillation signal of the frequency conversion circuit 100 of the present embodiment, the conventional single balance type frequency conversion circuit 1000 and the double balance type frequency conversion circuit 1100. FIG. 9 is an explanatory diagram showing a result of performing simulation on LO dependency. The parameters used in this simulation are as follows. That is, the collector current of the differential transistor pair is set to 1
The test was performed by setting the power supply voltage to 5 μV, the load resistance to 2 kΩ, the frequency of the local oscillation signal LO to 100 MHz, and the frequency of the carrier signal RF to 110 MHz.

As shown in FIG. 2, the frequency conversion circuit 1 of the present embodiment
00 has substantially the same characteristics as the output level of the conventional double-balanced frequency conversion circuit 1100,
It can be seen that NF is suppressed to a low level with respect to the local transmission signal LO level.

As described above, the frequency conversion circuit 100 of the present embodiment differs from the conventional double-balanced frequency conversion circuit 1100 in that the capacitor C4 and the first resistor R11 are replaced by the first resistor R11 instead of the current source. The third to sixth transistors Q connected to the base of the differential transistor pair 11
Fourth to seventh resistors R14 to R17 are provided as load resistors connected to the collectors of 13 to Q16.

In such a configuration, the fourth to seventh resistors R14 to R14 are set such that the voltage gains of the second differential transistor pair 12 and the third differential transistor pair 13 are equal.
Since R17 is determined, the eighth and ninth resistors R1
8, the thermal noise signal generated at R19 is canceled by the third differential transistor 13, and does not appear at the first and second output terminals out1, out2. Therefore, the resistance values of the eighth and ninth resistors R18 and R19 can be set high, and a high conversion gain can be realized. In addition, the conventional double-balanced frequency conversion circuit 1
It has almost the same input / output characteristics as 100, and the input impedance from the local oscillation signal LO can be set high.
Degradation can be kept small. Further, since the configuration does not require a current source, the device can be operated at a low operating voltage, and low voltage and low current can be realized. Further, the emitter area of the first transistor Q11 is 1 / n of the emitter area of the second transistor Q12.
, The current flowing through the first differential transistor pair 11 can be kept small, and the power consumption can be kept low as a whole. In summary, according to the frequency conversion circuit 100 of the present embodiment, low voltage, low current, low noise, and high conversion gain can be realized at the same time. Note that the frequency conversion circuit 100 of the present embodiment
Can be easily manufactured by configuring with an IC.

[Second Embodiment] FIG. 3 shows a second embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating a frequency conversion circuit according to the embodiment.
Note that, in the same figure, the same reference numerals are given to portions overlapping with the first embodiment (FIG. 1). 3, the frequency conversion circuit 200 of the present embodiment is different from the circuit configuration of the first embodiment shown in FIG.
A tenth resistor R20 for AC-grounding one emitter,
In addition, an eleventh resistor R21 for connecting the emitter of the second transistor Q12 to the ground in an AC manner is added.

In this embodiment, the tenth resistor R2
The current flowing into the second differential transistor pair 12 and the third differential transistor pair 13 (that is, the operating current) depends on the 0th and the eleventh resistor R21, so that Tenth and eleventh resistors R
The ratio of the operating current is determined by setting the resistance values of R20 and R21. Therefore, according to the frequency conversion circuit 200 of this embodiment having such a configuration, the tenth and eleventh resistors R
The distortion characteristics can be improved by adjusting the resistance values of R20 and R21.

[Third Embodiment] FIG. 4 shows a third embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating a frequency conversion circuit according to the embodiment.
Note that, in the same figure, the same reference numerals are given to portions overlapping with the first embodiment (FIG. 1). In FIG. 4, the frequency conversion circuit 300 of the present embodiment is different from the circuit configuration of the first embodiment shown in FIG.
7, a seventh transistor Q17 connected in parallel to
, An eighth transistor Q18, an attenuator 301, and a switch 303 connected in parallel to the transistor Q12.

That is, the collector of the seventh transistor Q17 is connected to the collector of the first transistor Q11,
The emitter is connected to the common emitter of the first differential transistor pair 11, and the base is connected to the first DC power supply V11 via the thirteenth resistor R23 and the terminal of the switch 303. On the other hand, the collector of the eighth transistor Q18 is connected to the collector of the second transistor Q12, the emitter is connected to the common emitter of the first differential transistor pair 11, and the base is the terminal of the twelfth resistor R22 and the switch 303. Through the first DC power supply V11
It is connected to the. Seventh and eighth transistors Q1
7, Q18 are paired to form the fourth differential transistor pair 14
And is connected in parallel to the first differential transistor pair 11.

The switch 303 selects a terminal or connection to a terminal. When the switch 303 is connected to a terminal, the first DC power supply V11 is connected via the twelfth and thirteenth resistors R22 and R23. When a voltage is applied to the fourth differential transistor pair 14 and connected to the terminal, the first DC power supply V11 is connected to the first differential transistor pair 1 via the second and third resistors R12 and R13.
1 is applied with a voltage. Further, the attenuator 301 has one end connected to the base of the eighth transistor Q18 and the twelfth resistor R2.
2 and the other end is connected to the carrier signal source 105 via the capacitor C5.

According to the frequency conversion circuit 300 of this embodiment having such a configuration, the seventh transistor Q 17 and the eighth transistor Q 17 are connected to the first differential transistor pair 11.
18 are connected in parallel and the connection is switched by the switch 303, so that either the first differential transistor pair 11 or the fourth differential transistor pair 14 If the gains of the first differential transistor pair 11 and the fourth differential transistor pair 14 are different, the conversion gain can be changed to two patterns by switching the switch. When the switch 303 is connected to the terminal, the level of the carrier signal RF having a large voltage level can be reduced by the attenuator 301, so that the carrier signal RF can be changed linearly over a wide range. it can.

[Fourth Embodiment] FIG. 5 shows a fourth embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating a frequency conversion circuit according to the embodiment.
Note that, in the same figure, the same reference numerals are given to portions overlapping with the first embodiment (FIG. 1). 5, the frequency conversion circuit 400 of the present embodiment has a configuration in which a differential amplifier 401 is added to the circuit configuration of the first embodiment shown in FIG.

The differential amplifier 401 includes a fifth differential transistor pair 15 in which a ninth transistor Q19 and a tenth transistor Q20 are paired and have a common emitter.
The first connected to the collector of the ninth transistor Q19
The fourth resistor R24, the fifteenth resistor R25 connected to the collector of the tenth transistor Q20, and the fourteenth resistor R24 connected to the collector of the ninth transistor Q19. A fourth DC power supply V14 connected to the collector of the tenth transistor Q20 through the base of the ninth transistor Q19;
A sixteenth resistor R26 connecting the base of the transistor Q20 of the first transistor Q20 to each other; a fifth DC power supply V15 connected to the base of the tenth transistor Q20;
And a current source 403 connected to the common emitter of the differential transistor pair 15 of FIG.

The base of the ninth transistor Q19 of the differential amplifier 401 is connected to the local oscillation signal source 103 via a capacitor C2, and the collector of the tenth transistor Q20 is connected via a capacitor C6. It is connected to the bases of the third and sixth transistors Q13, Q16. Therefore, after the local oscillation signal LO generated by the local oscillation signal source 103 is amplified by the differential amplifier 401, the third and sixth transistors Q
13 and Q16.

In the frequency conversion circuit 400 of this embodiment having such a configuration, even if the level of the local oscillation signal LO is low, it is amplified to a large level by the differential amplifier 401,
It can be supplied to the second differential transistor pair 12 and the third differential transistor pair 13. Also, the first
As described in the frequency conversion circuit 100 of the embodiment, the thermal noise signals generated by the eighth and ninth resistors R18 and R19 are output from the first and second output terminals out1 and o.
It does not appear offset in ut2. Because of these two features, in the frequency conversion circuit 400 of the present embodiment, the resistance values of the eighth and ninth resistors R18 and R19 are set to be sufficiently larger than the fourteenth and fifteenth resistors R24 and R25. Can be. The load resistance of the differential amplifier 401 is obtained by connecting the combined resistance of the eighth and fifteenth resistors R18 and R25 and the combined resistance of the ninth and fourteenth resistors R19 and R24. From the magnitude relationship, this is approximately the fourteenth and fifteenth resistors R24, R2
Only the combined resistance of No. 5 needs to be considered. Therefore, the gain design of the differential amplifier 401 can be easily performed. For example, to amplify the local oscillation signal LO at a voltage level of 90 dBμV to 110 dBμV, 20
It is sufficient to design a differential amplifier that amplifies dB. In this case, only the fourteenth and fifteenth resistors R24 and R25 need to be considered as the load resistance of the differential amplifier 401.

In this embodiment, the differential amplifier 401 is used as a means for amplifying the local oscillation signal LO.
Amplifying means having another circuit configuration such as a common emitter amplifier or a cascode amplifier may be used.

As a modification of the fourth embodiment (FIG. 5), as shown in FIG. 6, the collector of the ninth transistor Q19 is connected via the capacitor C7 to the bases of the fourth and fifth transistors Q14 and Q15. , The capacitor C3 may be removed, and these bases may not be grounded. In the configuration of this modification, the local oscillation signal LO can be differentially input to the second differential transistor pair 12 and the third differential transistor pair 13, so that the output out1 of the frequency conversion circuit 500 is output. At out2, the DC offset voltage can be reduced.

[Fifth Embodiment] FIG. 7 shows a fifth embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating a frequency conversion circuit according to the embodiment.
Note that, in the same figure, the same reference numerals are given to portions overlapping with the first embodiment (FIG. 1). 7, the frequency conversion circuit 600 of the present embodiment is the same as the first resistance R in the frequency conversion circuit 100 of the first embodiment shown in FIG.
11th transistor Q21, twelfth
Transistor Q22, the seventeenth resistor R27 and the sixth
Is a configuration using a current mirror circuit 601 provided with the DC power supply V16.

The current mirror circuit 601 connects the collector of the eleventh transistor Q21 to the common emitter of the first differential transistor pair 11, grounds the emitter, and connects the base to the base and collector of the twelfth transistor Q22. The emitter of the twelfth transistor Q22 is grounded, and the collector is connected to a sixth DC power supply V16 via a seventeenth resistor R27. According to the frequency conversion circuit 600 of the present embodiment having such a configuration, the operation current flowing through the first differential transistor pair 11 can be stabilized, and the frequency conversion circuit 600 performs a stable constant current operation. be able to.

[Sixth Embodiment] FIG. 8 shows a sixth embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating a frequency conversion circuit according to the embodiment.
Note that, in the same figure, the same reference numerals are given to portions overlapping with the first embodiment (FIG. 1). 8, the frequency conversion circuit 700 of the present embodiment is different from the circuit configuration of the first embodiment shown in FIG.
23 and an eighteenth resistor R28 are added. Incidentally, the common emitter of the first differential transistor pair 11, that is, the first and second transistors Q11,
The emitters of Q12 are each grounded.

The base of the thirteenth transistor Q23 is
It is connected to the base of the first transistor Q11 via the third resistor R13, and is connected to the collector of the thirteenth transistor Q23. The thirteenth transistor Q
The collector and base of 23 are connected to a first DC power supply V11 via an eighteenth resistor R28.

In this embodiment, the thirteenth transistor Q23, the eighteenth resistor R28, and the first DC power supply V
The circuit configuration including the first transistor Q11 in addition to the first transistor Q11 can be regarded as a current mirror circuit connected to the common emitter of the second differential transistor pair 12. Therefore, according to the frequency conversion circuit 700 of the present embodiment, the operating current of the second differential transistor pair 12 can be stabilized, so that stable constant current operation can be performed during frequency conversion.

The base of the thirteenth transistor Q23 is connected to the second transistor Q23 via the second resistor R12.
12 is connected to the base of the third differential transistor pair 13, the eighteenth resistor and the first DC power supply V11 and the second transistor Q12 are combined. Can be regarded as a current mirror circuit connected to the common emitter. Therefore, according to the frequency conversion circuit 700 of the present embodiment, since the operating current of the third differential transistor pair 13 can be stabilized, stable constant current operation can be performed during frequency conversion.

[Seventh Embodiment] FIG. 9 shows a seventh embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating a frequency conversion circuit according to the embodiment.
Note that, in the same figure, the same reference numerals are given to portions overlapping with the first embodiment (FIG. 1). 7, the frequency conversion circuit 800 of the present embodiment is different from the frequency conversion circuit 100 of the first embodiment shown in FIG. 1 in that the bipolar transistors (Q11 to Q16) are replaced with p-channel voltage effect transistors (FETs). ) Is used. At this time, the base of the transistor is replaced with a gate, the emitter is replaced with a source, and the collector is replaced with a drain.

In the present embodiment shown in FIG.
Although a junction type is used, a MOS type may be used. Also, instead of replacing all the transistors with FETs, by replacing a part, the transistors and the FE are replaced.
T and T may be mixed. Furthermore, not only the first embodiment (FIG. 1) but also the other second to sixth embodiments,
Similar substitutions are possible. For example, in the frequency conversion circuit 300 of the third embodiment shown in FIG.
The seventh and eighth transistors Q17 and Q18 of the differential transistor pair 14 may be replaced with FETs.

The frequency conversion circuit 800 of the present embodiment having such a configuration is different from the frequency conversion circuit 100 of the first embodiment.
Operates in the same manner as that of the frequency conversion circuit 100 of the first embodiment. However, in the FET, a current flows between the drain and the source in proportion to the square of the gate voltage. Can be suppressed.

[0079]

As described above, according to the frequency conversion circuit of the present invention, the first transistor and the second transistor have different emitter area ratios, and the first and second load resistors have different emitter area ratios. Is adjusted in accordance with the emitter area ratio to equalize the gain of the second differential transistor pair and the gain of the third differential transistor pair. If a bias resistor is connected to the base of the pair, the thermal noise signal generated from the bias resistor can be canceled, and as a result,
Since the resistance value of the base bias resistor can be increased, the gains of the second and third differential transistor pairs can be set high, and high gain conversion of a signal in the frequency conversion circuit can be realized. Further, by setting the resistance value of the base bias resistor to be high, the input impedance on the base side of the third and sixth transistors can be set to be high. Degradation can be kept small.

Further, for example, by making the emitter area of the first transistor smaller than the emitter area of the second transistor, the current flowing through the first differential transistor pair can be suppressed to be small. Power consumption can be suppressed, and lower voltage and lower current can be realized.

According to the frequency conversion circuit of the present invention,
A plurality of differential transistor pairs each having two transistors and connected in parallel with each other are connected in parallel to the first differential transistor pair, and the first differential transistor pair and the plurality of differential transistor pairs are connected to each other. Is provided and a differential transistor pair to be used is selected by switching the switch, so that the conversion gain can be changed in many patterns.

According to the frequency conversion circuit of the present invention,
For example, in the first differential transistor pair, a tenth resistor is connected between an emitter of the first transistor and a connection point serving as a common emitter of the first differential transistor pair, and a Since the eleventh resistor is connected between the emitter and the connection point to adjust the resistance values of the tenth and eleventh resistors, the current value flowing into the second and third differential transistor pairs Can be determined, and the distortion characteristics in the frequency conversion circuit can be improved.

According to the frequency conversion circuit of the present invention,
Since the attenuating means for attenuating the level of the signal input to the base of one of the plurality of differential transistor pairs connected in parallel is connected, the signal can be applied to the first signal (carrier signal) having a large signal level. The level can be reduced, and the first signal (carrier signal) can be linearly processed over a wide range.

According to the frequency conversion circuit of the present invention,
Amplifying means connected to the bases of the third and sixth transistors or the fourth and fifth transistors amplifies the second signal (local oscillation signal) and supplies it to the second and third differential transistor pairs. If the level of the second signal (local oscillation signal) input to the bases of the third and sixth transistors is low, the level of the input signal is amplified and input to the base. Becomes possible.

According to the frequency conversion circuit of the present invention,
Since the current source is connected to the common emitter of the first differential transistor pair, the operation current flowing through the first differential transistor pair can be stabilized, and the constant current operation can be stabilized in the frequency conversion circuit. Can be performed.

According to the frequency conversion circuit of the present invention,
A thirteenth transistor having a base and a collector connected to each other, and the bases of the first and second transistors are connected to the base and the collector of the thirteenth transistor; A stable current can be supplied to the pair of common emitters, and a stable constant current operation can be performed in the frequency conversion circuit.

Further, according to the frequency conversion circuit of the present invention, the first to tenth transistors or the transistors included in the plurality of differential transistor pairs are realized by using the field effect transistors. Intermodulation distortion can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a frequency conversion circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a result of simulating the frequency conversion circuit according to the first embodiment of the present invention and a conventional frequency conversion circuit.

FIG. 3 is a circuit diagram illustrating a frequency conversion circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a frequency conversion circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a frequency conversion circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a frequency conversion circuit according to another embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a frequency conversion circuit according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating a frequency conversion circuit according to a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating a frequency conversion circuit according to a seventh embodiment of the present invention.

FIG. 10 is a circuit diagram showing a conventional single balance type frequency conversion circuit.

FIG. 11 is a circuit diagram showing a conventional double balance type frequency conversion circuit.

[Description of Signs] C1 to C7 Capacitors Q11 to Q23 Transistors R11 to R28 Resistance RL1 First load resistance RL2 Second load resistance V11 First DC power supply V12 Second DC power supply V13 Third DC power supply 11 to 14 Differential transistor pair 103 Local oscillation signal source 105 Carrier signal source 301 Attenuator 303 Switch 401 Differential amplifier 403 Current source

Claims (14)

[Claims] 1. A first differential transistor pair having a first transistor and a second transistor having a common emitter and different emitter areas, respectively, and a third transistor and a fourth transistor having a common emitter. And a second differential transistor pair having the common emitter connected to the collector of the first transistor; and a fifth transistor and a sixth transistor having a common emitter. A third transistor connected to the collector of the second transistor, the bases of the third transistor and the sixth transistor connected to each other, and the base of the fifth transistor connected to the base of the fourth transistor; A differential transistor pair; collectors of the third and fourth transistors; and fifth and sixth transistors. A first load resistor connected to the collector of the transistor, and a second load resistor connected to the collector of the fifth and sixth transistors, respectively, wherein the first and second load resistors are Is adjusted according to the emitter area ratio of the first transistor and the second transistor, and the product of the transfer conductance of the second differential transistor pair and the first and second load resistance values is adjusted. And a product of a transmission conductance of the third differential transistor pair and a second load resistance value. 2. A first differential transistor pair having a common emitter and a first transistor and a second transistor having different emitter areas, respectively, and a third transistor and a fourth transistor having a common emitter. And a second differential transistor pair having the common emitter connected to the collector of the first transistor; and a fifth transistor and a sixth transistor having a common emitter. Connecting the collector of the second transistor, connecting the base of the sixth transistor to the base of the third transistor,
A third differential transistor pair having the base of the fifth transistor connected to the base of the fourth transistor; a fourth resistor connected to the collector of the third transistor; and a collector of the fourth transistor A first load resistor having a sixth resistor connected to the first resistor, a fifth resistor connected to the collector of the fifth transistor, and a seventh resistor connected to the collector of the sixth transistor. A second load resistor, a capacitor and a first resistor respectively connected to a common emitter of the first differential transistor pair, and a third resistor connected to a base of the first transistor via a third resistor. A first power supply connected to the base of the second transistor via a second resistor, and a collector of the sixth transistor via the seventh resistor. And a collector of the fifth transistor connected to the collector of the fourth transistor via the seventh resistor and the sixth resistor, and a collector of the fifth transistor via the fifth resistor. The third through the resistor and the fourth resistor;
A second power supply connected to a collector of the third transistor, a fourth power supply connected to a base of the third transistor and the sixth transistor via an eighth resistor, and a fourth power supply connected to a base of a third transistor via a ninth resistor. And a third power supply connected to the bases of the fifth and fifth transistors, and supplying a first signal to the base of the second transistor; the third transistor and the sixth transistor A frequency conversion circuit that supplies a second signal to a base of the third transistor and obtains an output from the collectors of the third and fourth transistors, wherein the resistance value of the fourth to seventh resistors is determined by the first transistor. And the emitter area ratio of the second transistor and the second transistor, the transmission conductance of the second differential transistor pair, the first load resistance value, and the second negative resistance. And the product of the resistance value, the third differential transistor pair transfer conductance of the frequency converter circuit, characterized in that equal the product of the second load resistance. 3. The frequency conversion circuit according to claim 1, wherein an emitter area of the second transistor is larger than an emitter area of the first transistor. 4. A plurality of differential transistor pairs connected in parallel to the first differential transistor pair, each pair including two transistors and connected in parallel with each other, wherein the first differential transistor pair is selectively connected to the first differential transistor pair. 4. The frequency conversion circuit according to claim 1, further comprising a transistor pair and a switch for effectively operating one of said plurality of differential transistor pairs. 5. The method according to claim 1, further comprising: a connection point between an emitter of the first transistor and a common emitter of the first differential transistor; a connection point between an emitter of the second transistor and the common emitter; 4. A resistor is provided between each connection point serving as a common emitter of each of the plurality of differential transistors and an emitter of each transistor of the dynamic transistor pair.
Or the frequency conversion circuit according to 4. 6. The frequency conversion circuit according to claim 4, wherein attenuating means for attenuating a signal level is connected to one base of said plurality of differential transistor pairs. 7. An apparatus according to claim 1, further comprising an amplifier connected to a base of said third and sixth transistors or a base of said fourth and fifth transistors.
7. The frequency conversion circuit according to 3, 4, 5, or 6. 8. The frequency conversion circuit according to claim 7, wherein said amplification means is a differential amplifier, a common emitter amplifier, or a cascode amplifier. 9. The amplifying means is a differential amplifier having a ninth transistor and a tenth transistor having a common emitter, and the collector of the ninth or tenth transistor is connected to the third and sixth transistors. The frequency conversion circuit according to claim 7, wherein the frequency conversion circuit is connected to a base of the transistor or the fourth and fifth transistors. 10. The collector of said ninth or tenth transistor is connected to the bases of said third and sixth transistors, and the collector of said ninth or tenth other transistor is connected to said fourth and fifth transistors. The frequency conversion circuit according to claim 9, wherein the frequency conversion circuit is connected to a base of the transistor. 11. The device according to claim 1, further comprising a current source connected to a common emitter of the first differential transistor pair. 10
The described frequency conversion circuit. 12. The frequency conversion circuit according to claim 11, wherein said current source is a first resistor and a capacitor, or a combination of a current mirror circuit and said capacitor. 13. A first device in which a base and a collector are connected.
3. The semiconductor device according to claim 1, further comprising a third transistor, wherein a base and a collector of the thirteenth transistor are connected to bases of the first and second transistors. ,
The frequency conversion circuit according to 8, 9, 10, 11 or 12. 14. The semiconductor device according to claim 1, wherein the first to tenth transistors or the transistors included in the plurality of differential transistor pairs are field-effect transistors. 7, 8, 9, 10, 1
14. The frequency conversion circuit according to 1, 12, or 13.