JPH05100999A - Bus sizing system for microprocessor - Google Patents

Abstract

PURPOSE:To make it easy to design an external circuit by providing a microprocessor with an address mapping register for a device with a prescribed bus width, comparing, the address and an external device reference address and generating a data bus sizing signal. CONSTITUTION:The address of 16 bit memory 3 is stored in a 16 bit device mapping register 100 and the address of an 8 bit device mapping register 200. After this, at the time of accessing with regard to external devices 2 to 4, the values of an external device reference address signal 300 and the registers 100, 200 are compared by comparators 400, 401. Then, in the case of the external device reference address signal 200 is 0000 to 7FFF, 16 bits/8 bits bus sizing signals 7, 8 is not generated. Besides, the same signal 300 is 8000 to 7FFF, in the case of the comparator 400 generates the 16 bits bus sizing signal 7 is generated and in the case of B0000 to FFFF, the 8 bits bus sizing signal 8 is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus sizing system for a microprocessor, and more particularly to switching the size of a data bus of a microprocessor used in various computers such as personal computers and various control devices.

[0002]

2. Description of the Related Art FIG. 4 shows a system using a conventional microprocessor having a data bus. In the figure, 1 is a microprocessor, 2, 3, 4 are external devices, and 2 is 32-bit data handling. Memory or IO device (hereinafter, 32-bit memory / IO device) capable of performing 16-bit memory or IO device (hereinafter, 1-bit capable of performing 16-bit data handling)
6-bit memory / IO device), 4 is a memory or IO device capable of 8-bit data handling (hereinafter, 8-bit memory / IO device), 5 is the microprocessor 1 and 32, 16 or 8-bit memory / I
A data bus signal for exchanging data between the O devices 2, 3 and 4, 6 is an address signal indicating the reference location of the external device by the microprocessor 1, and 7 is the external reference of the microprocessor 1 at present. A 16-bit bus sizing signal for indicating that the device performs 16-bit data handling, and 8 indicates that the device to which the microprocessor 1 is currently making an external reference performs 8-bit data handling. Is an 8-bit bus sizing signal, and 9 is an address decoding circuit for generating the 16-bit bus sizing signal 7 and the 8-bit bus sizing signal 8 from the address signal 6.

Next, the operation will be described. Hereinafter, regarding the operation of the microprocessor 1 for accessing the external devices 2, 3, 4, when the microprocessor 1 reads data from the external devices 2, 3, 4, and when writing data to the external devices 2, 3, 4, The data handling of the two cases will be described. First, the case of reading data will be described. The microprocessor 1 performs 32-bit data handling unless either the 16-bit bus sizing signal 7 or the 8-bit bus sizing signal 8 is valid. Therefore, when reading data from the 32-bit memory / IO device 2, the address decoding circuit 9 reads the 32-bit memory / I.
The address reference to the O device 2 is decoded to invalidate the 16-bit bus sizing signal 7 and the 8-bit bus sizing signal 8. 32-bit memory / IO device 2
Outputs 32 bits of data to the data bus signal 5, and the microprocessor 1 outputs this data to H / H
It is read at a predetermined timing according to the W configuration. When reading data from the 16-bit memory / IO device 3, the address decoding circuit 9 enables the 16-bit bus sizing signal 7, and the 16-bit memory / IO device 3 outputs the data to the lower 16 bits of the data bus signal 5. Then, the microprocessor 1 reads it. Similarly, for the 8-bit memory / IO device 4, the address decoding circuit 9 enables the 8-bit bus sizing signal 8, and the 8-bit memory / IO device 4 outputs the data to the lower 8 bits of the data bus signal 5. , And the microprocessor 1 reads it.

Next, the case of writing data will be described. The address decoding circuit 9 invalidates the bus sizing signals 7 and 8 when the 32-bit memory / IO device 2 is accessed, as in the case of reading data.
When the 6-bit memory / IO device 3 is accessed, the 16-bit bus sizing signal 7 is enabled, and when the 8-bit memory / IO device 4 is accessed, the 8-bit bus sizing signal 8 is enabled, and the microprocessor 1 is enabled. Informs the bus size that the external reference device can handle data. Since the microprocessor 1 is a byte machine, the write data is output from the microprocessor 1 to the most significant byte of the data bus signal 5 when writing data to the 8-bit memory / IO device 4, depending on the arrangement address of the external device. Will be done. However, at this time, if the 8-bit bus sizing signal 8 is valid, the microprocessor 1 knows that the external device is an 8-bit data handling device, and outputs the write data to the least significant byte of the data bus signal 5. 8-bit memory /
The IO device 4 will be written with the data. The same applies to the 16-bit memory / IO device 3. From the above, various data size devices can be supported by enabling the bus sizing signals 7 and 8, and the microprocessor 1 and various devices 2 to 4 can be used.
The data handling buffer circuit and the control circuit therefor can be omitted.

[0005]

Since the conventional microprocessor is constructed as described above, the bus sizing signal for dealing with devices having various data widths must be generated externally. In particular, when data is written, the data normally output from the microprocessor is fast, and a high-speed address decode circuit that enables the bus sizing signal is required, which makes timing design difficult.

The present invention has been made in order to solve the above problems, and a bus of a microprocessor capable of performing the same bus sizing as described above without an external bus sizing signal generating circuit such as an address decoding circuit. The purpose is to obtain a sizing method.

[0007]

A bus sizing system for a microprocessor according to the present invention has the following elements. (A) an address mapping register (an example of an identification register) that stores an address (an example of an identification information) of a device having a predetermined bus width; and (b) a reference address (an example of reference information) for accessing the device. A comparator for comparing the addresses of the address mapping registers to generate a bus sizing signal indicating the bus width of the device to be accessed.

[0008]

According to the bus sizing method of the microprocessor of the present invention, the microprocessor internally has an address mapping register (identification register) for accessing an external device having various bus widths. A bus sizing signal is dynamically generated by setting an address (identification information) assigned to the device and comparing it with the address of the device to be accessed by the comparator. As described above, in the bus sizing method of the microprocessor according to the present invention, the external bus sizing signal generation circuit is made unnecessary by having the identification register supporting the device having various bus widths inside the microprocessor. Facilitates W timing design.

[0009]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a microprocessor, 100
Is a 16-bit device mapping register, 200 is 8
Bit device mapping register, 300 is an external device reference address signal inside the microprocessor, 40
Reference numerals 0 and 401 are comparators, 7 is a 16-bit bus sizing signal, and 8 is an 8-bit bus sizing signal. Also, 2
Is a 32-bit memory having addresses 0000 to 7FFF, 3 is a 16-bit memory having addresses 8000 to AFFF, and 4 is an 8-bit memory having addresses B000 to FFFF.

Next, the operation will be described. The data handling of the external device and the microprocessor 1 is the same as the conventional operation. First, before the microprocessor refers to the external device, the address to which the 16-bit memory / IO device is mapped is written to the 16-bit device mapping register 100 by S / W. For example, in this example, address 8 of 16-bit memory 3
000 to AFFF are stored in the 16-bit device mapping register 100. Similarly, 8-bit memory / IO
The device is written to the 8-bit device mapping register 200. In this example, an 8-bit memory 4
The addresses B000 to FFFF are stored in the 8-bit device mapping register 200. Thereafter, when accessing the external devices 2, 3, and 4, the values of the external device reference address signal 300 in the microprocessor and the values of the registers 100 and 200 are compared with each other by the comparators 400 and 401.
And the access to the address set in the mapping register is performed, 16-bit and 8-bit bus sizing signals 7 and 8 are generated in the microprocessor, and the data handling is performed. For example,
External device reference address signal 300 is 0000-7F
In the case of FF, the result of comparison between the comparators 400 and 401 is 1
Neither 6-bit nor 8-bit bus sizing signals 7, 8 are generated. When the external device reference address signal 300 is 8000 to AFFF, the comparator 400 generates the 16-bit bus sizing signal 7. Similarly, the external device reference address is B000 to FFFF.
In the case of, an 8-bit bus sizing signal 8 is generated.

Embodiment 2. In the above embodiment, the data bus sizing signals 7 and 8 are closed inside the microprocessor. However, as shown in FIG. 2, the OR with the external data bus sizing signals 7a and 8a described in the conventional example is used. You may comprise so that it may detect inside.

Embodiment 3. Further, in the above-described embodiment, the case where the addresses of the respective external devices are consecutive at one location is shown, but a plurality of addresses may exist discontinuously as shown in FIG. Figure 3 shows a 16-bit device mapping register
This is provided with five units 00a to 100e so that an address map can be stored in each. Since there are a plurality of registers in this way, it is possible to deal with the case where a plurality of addresses exist discontinuously.

Embodiment 4. Further, in the above embodiment, the case of the memory address has been described, but the case of the IO address assigned to the IO device may be used. For example, 1
Since device A transfers data in 6 bits and device B transfers data in 8 bits, 0A00,
Assuming that 0A01 is assigned as the IO address, 0A00 is stored in the 16-bit device mapping register 100 and 0A01 is stored in the 8-bit device mapping register 200. Then, since the microprocessor 1 transfers data to and from these IO addresses, if 0A00 or 0A01 is set to the external device reference address signal 300,
The 16-bit or 8-bit bus sizing signal 7 or 8 is generated by the comparators 400 and 401.

Example 5. Further, in the above embodiment, an example in which the size of the data bus is switched has been shown, but the present invention can be applied to devices having different sizes of the control bus, the address bus, and other buses.

Embodiment 6. Further, in the above-described embodiment, the example in which the memory address and the IO address are used as the identification information / reference information has been shown, but other identification information / reference information such as a channel number, a unit number, a board number may be used.

Example 7. Further, in the above embodiment, the address mapping register is taken as an example, but any identification register capable of storing the above identification information may be used. Further, it does not have to be called a register as long as it can store identification information.

[0017]

As described above, according to the present invention, since the generation of the data bus sizing signal is configured by the method involving register setting inside the microprocessor, the ease of designing the external circuit can be obtained. There is an effect that a highly reliable one can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a data bus sizing portion of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a data bus sizing portion of a microprocessor according to another embodiment of the present invention.

FIG. 3 is a schematic diagram of a data bus sizing portion of a microprocessor according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional microprocessor system.

[Explanation of symbols]

1 Microprocessor 2 32-bit memory / IO device 3 16-bit memory / IO device 4 8-bit memory / IO device 5 Data bus signal 6 Address signal 7 16-bit bus sizing signal 8 8-bit bus sizing signal 9 Decoding circuit 100 16-bit device Mapping register (one example of identification register) 200 8-bit device mapping register (one example of identification register) 300 External device reference address signal 400 Comparator (for 16-bit device) 401 Comparator (for 8-bit device)

Claims (1)

[Claims] 1. A bus sizing system for a microprocessor comprising: (a) an identification register for storing identification information of a device having a predetermined bus width; (b) reference information for accessing the device and the identification. A comparator that compares the identification information of registers to generate a bus sizing signal that indicates the bus width of the device that is trying to access.