JPH049896A - Multi-window control system - Google Patents

Abstract

PURPOSE:To enable flexible multi-window display operation which is easily controlled without the limitation of the number of windows, etc., by writing plotting data in a frame buffer through an address converting circuit and a clipping circuit. CONSTITUTION:This system is provided with an address converting circuit 104 which converts the address of a window to be processed in a window memory 103 into the frame buffer address of a corresponding window to be displayed and a clipping circuit 105 which operates so that only the part where the window is displayed is written in a frame buffer between a system bus 102 and a frame buffer 106 of a processor 101. Then when the processor 101 writes the plotting data in the window memory 103, the plotting data is written in the frame buffer 106 through the address converting circuit 104 and clipping circuit 105. Consequently, the control is easy, the limitation of the number of windows is eliminated, and the flexible multi-window display operation becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-window control system, and more particularly to a multi-window control system that displays a plurality of screens on a display using a bitmap memory.

[Prior art] In a method of realizing multi-windows using bitmap memory, a window memory is provided to restore the window when the priority order, size, position, etc. of window overlap is changed, and the drawing Sometimes, first
Writes to the window memory above, and writes the displayed part of the window to the display frame buffer (hereinafter referred to as
It is common to also write to a frame buffer (also simply called a "frame buffer"). Further, window recovery processing is generally performed by reading a newly displayed portion from the window memory and writing it to the frame buffer.

In these processes, since both window memory processing and frame buffer processing are required, there is a problem in that high-speed processing is difficult.

As a solution to this problem, for example, JP-A-63
There is a technique disclosed in Publication No. -7347s. This technique selects a window memory at the time of display using hardware control.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, since the window memory is selected at the time of display by hardware control, there is a limit to the number of windows that can be displayed at the same time, and it is difficult to display a large number of windows at the same time. This had a practical problem in that it resulted in an extreme increase in the amount of hardware required. In addition, since hardware control becomes complicated, there is a problem in that there is a problem in realizing high-definition disk bracelets that require hardware capable of high-speed processing.

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the conventional technology, to make it possible to freely control by software, and to make the control possible. An object of the present invention is to provide a multi-window control method that is easy to use, has no restrictions on the number of windows, and can realize flexible multi-windows.

[Means for Solving the Problem] The above-mentioned object of the present invention is to provide a processing device that performs multi-window processing using a frame buffer. An address conversion circuit that converts a window memory address of a window into a corresponding frame buffer address of a window to be displayed, and operates so that only a portion of the window that is being displayed is written to the frame buffer. a clipping circuit, and when the processing device writes the drawing data to the window memory, the processing device also writes the drawing data to the writing frame buffer via the correction address conversion circuit and the clipping circuit. This is achieved through a control method.

[Operation] In the multi-window control method according to the present invention, the address conversion circuit operates to convert the address of the window memory of the window to be processed into the frame buffer address of the corresponding window to be displayed. . As a result, the processing device only needs to calculate the address of the window memory during the drawing process.
Frame buffer address calculations are no longer required, and
When writing to the window memory, writing to the frame buffer is performed at the same time, allowing high-speed processing. The clipping circuit operates so that only the portion of the window that is being displayed is written to the frame buffer.

This allows the processing device to perform processing without being aware of which part of the window is being displayed, eliminating the need for boundary determination processing and enabling high-speed processing.

Also, on the other hand, the frame buffer recovery write signal is
When the priority of the window is changed or the display position is changed, it is set and output by the processing device prior to window recovery processing, and the frame buffer is also written when reading the window memory. It works like this. This allows the processing device to
When the recovered portion of the window is read from window memory, it will be automatically written to the frame buffer at the same time. This eliminates the need for frame buffer address calculation, frame buffer writing, etc., simplifying processing and increasing speed.

[Embodiment J] Hereinafter, one embodiment of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an overview of a multi-window control system showing one embodiment of the present invention. In the figure, a processing device +01 is a processing device that performs multi-window processing, and is connected via a system bus 102 to a window memory 103 that holds multiple window screens. Converter engineer 04. A frame buffer +06 is connected via a clipping circuit +05. Further, a display 108 is connected to the end of the frame buffer 106, and is configured to display the contents of the frame buffer 1.06.

The recovery write control circuit 107 includes window memory 1
It has a function to control writing to the frame buffer 106 at the same time as reading 03. window memory 10
3 and the frame buffer 106 are configured so that they can be written to simultaneously by the processing device 101. However, if the clipping circuit 105 determines that it is outside the area, it is not written to the frame buffer 106. Furthermore, the action of the recovery write control circuit 107 makes it possible to read data from the processing device lot/twin window memory 103 and simultaneously write data to the frame buffer 106.

FIG. 2 shows the procedure of multi-window processing and window recovery processing by processing device +01.

Hereinafter, the operation of the multi-window control system of this embodiment will be explained based on FIGS. 1 and 2.

First, the processing device +01 converts the address of the window memory 103 of the window to be processed into the address of the corresponding point of the displayed window in the frame buffer 106 using the address conversion circuit 10.
4 (step 201).

Further, the processing device 101 sets the display area of the window in the clipping circuit 105 (step 202) to prevent writing outside the corresponding window display area of the frame buffer.

The subsequent processing differs depending on whether it is a drawing process or a recovery process, so they will be explained separately.

(1) In the case of drawing processing: Address calculation is performed to the window memory 103, and drawing data is written. Window memory 103
Writing all drawing data to (step 20
When step 4) is completed, the process ends.

(2) For recovery processing: The recovery write control circuit 107 is set to operate (step 205). The processing device reads data in window memory +03 corresponding to the display area of the window to be restored in the frame buffer (step 2).
06). As the data is read, it is written to the frame buffer 106 and the window is restored. After reading all the data in the area to be recovered, reset the recovery write control circuit +07 (step 207).
, ends the process.

FIG. 3 shows the address conversion circuit 104. A detailed configuration example of the clipping circuit 105 and the first write control circuit 107 is shown. The operation of this circuit will be explained below.

An address 301 on the system bus 102 is divided into an X address representing the X coordinate of the screen and a Y address representing the Y coordinate. The X address and Y address each have an X offset of 302. Y offset 303 is added independently. The addresses after addition are integrated again,
This becomes the frame buffer address 304. The above is the operation of the address conversion circuit +04.

Next, the X address to which the above offset has been added is input to comparators 306a and 306b. The comparators 306 a and 306 b have a minimum value 305 a and a maximum value 30 of the X coordinate of the display area as comparison values, respectively.
5b is input and a comparison is made with this value. The output from the comparator 306a indicating that the X coordinate is greater than or equal to the minimum value 3058 and the output from the comparator 306b indicating that the X coordinate is less than or equal to the maximum value 305b are input to the logic AND circuit 307a, and This becomes a signal indicating that the X address to which the offset of is added is within the range of the display area. In parallel with this, the range of the Y address is similarly determined (output of the logical AND circuit 307b). Signals that satisfy the ranges for each of the X address and Y address are input to the logical AND circuit 307c,
This output becomes a signal indicating that it is within the display area.

The above is the operation of the clipping circuit 104.

Further, the value of the recovery write control register 308 of the recovery write control circuit +07 is input to the logic AND circuit 307d together with the read control signal 310, and the output thereof is input to the logic OR circuit 309 together with the write control signal 311. The output of this logic OR circuit 309 is sent to the logic AND circuit 309 along with the output of the above-mentioned clipping circuit +04.
7e, frame buffer write control signal 3
It becomes 12.

In addition, the above-mentioned example shows an example of the present invention,
It goes without saying that the present invention should not be limited to this.

[Effects of the Invention] As described above in detail, according to the present invention, in a processing device that performs multi-window processing using a frame buffer, a processing target is connected between the system bus of the processing device and the frame buffer. an address conversion circuit that converts a window memory address of a window to be displayed into a frame buffer address of a corresponding window to be displayed; and an address conversion circuit that operates so that only the portion where the window is being displayed is written to the frame buffer. A clipping circuit is provided, and when the processing device writes the drawing data to the window memory, the drawing data is also written to the frame buffer via the address conversion circuit and the clipping circuit.
It has the remarkable effect of realizing a multi-window control method that can be easily controlled by software, has no restrictions on the number of windows, etc., and can realize flexible multi-windows. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of a multi-window control system showing an embodiment of the present invention, FIG. 2 is a flowchart showing the steps of multi-window processing and window recovery processing, and FIG. 3 is an address conversion circuit and a clipping circuit. FIG. 7 is a diagram illustrating a detailed configuration example of a ninth-time post-write control circuit. 101: Processing device, 102 System bus, 103: Window memory, 104 Near address converter, 105: Ripping circuit, 106: Frame buffer, 107
: Recovery write control circuit, +08 : Display, 2
01 to 207 Processing steps, 301: Address on window memory, 302 a, 302 b: Offset, 303 a, 303 b: Adder, 304
．． Frame buffer address, 305a, 305b
: Minimum value, maximum value of X address, 305c, 305d
: Minimum value, maximum value of Y address, 3o6 a +3
06b, 306c, 306cl: Comparator, 307a
, 307 b , 308 c and 307 d , 307
e: Logic AND circuit, 3080 recovery write control register, 309: logic off circuit, 310: read control signal, 311 write control signal, 312° frame buffer write signal. No.

Claims (1)

[Claims] 1. In a processing device that performs multi-window processing using a display frame buffer, between the system bus of the processing device and the display frame buffer, the address of the window memory of the window to be processed is displayed in a corresponding manner. an address conversion circuit that converts into a display frame buffer address of a window to be displayed, and a clipping circuit that operates so that only the portion of the window that is being displayed is written to the display frame buffer, and the processing device A multi-window control system characterized in that when writing the drawing data to the window memory, the drawing data is also written to the display frame buffer via the address conversion circuit and the clipping circuit.