JPH0498950A - Signal transmission system - Google Patents

Signal transmission system

Info

Publication number
JPH0498950A
JPH0498950A JP2216163A JP21616390A JPH0498950A JP H0498950 A JPH0498950 A JP H0498950A JP 2216163 A JP2216163 A JP 2216163A JP 21616390 A JP21616390 A JP 21616390A JP H0498950 A JPH0498950 A JP H0498950A
Authority
JP
Japan
Prior art keywords
circuit
signal line
driver
driver circuits
pull
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2216163A
Other languages
Japanese (ja)
Inventor
Susumu Saito
晋 齋藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Ibaraki Ltd
Original Assignee
NEC Ibaraki Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Ibaraki Ltd filed Critical NEC Ibaraki Ltd
Priority to JP2216163A priority Critical patent/JPH0498950A/en
Publication of JPH0498950A publication Critical patent/JPH0498950A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To detect a specific driver circuit to be driven by providing a pull- down resistor having a resistance to specify its own circuit, a daisy chain connection switching means and its control means to the system. CONSTITUTION:When a fault is detected by a control circuit 2-l of a driver circuit 1-1, the control circuit 2-1 turns on a switch circuit 3-1 and informs a fault to a CPU 6 of a receiver circuit 4 through a daisy chain connection signal line 101. The CPU 6 outputs an inhibit signal to all control circuits 2-i so that all switch circuit other than a switch circuit of the driver circuit in which a fault is detected are not closed. Then a potential V1 at a connection point between the signal line 100 and the other end of a register R0 is expressed as V1=(R0/R1+R0).Vcc. That is, when the potential V1 is expressed as Vi=(R0/ Ri+R0).Vcc, it is discriminated that the driver circuit 1-i is driven.

Description

【発明の詳細な説明】 技術分野 本発明は信号伝達システムに関し、特に複数のドライバ
回路からの出力信号をディジーチェイン接続の信号線を
介してワイヤードオアし、レシーバ回路に入力する信号
伝達システムに関する。
TECHNICAL FIELD The present invention relates to a signal transmission system, and more particularly to a signal transmission system in which output signals from a plurality of driver circuits are wire-ORed via daisy-chained signal lines and input to a receiver circuit.

従来技術 従来、この種の信号伝達システムにおいては、複数のド
ライバ回路各々のスイッチ回路に、たとえばオーブンコ
レクタ出力T T L (transistor−tr
ansistor logic )回路が使用され、こ
れらのドライバ回路からの出力信号をディジーチェイン
接続の信号線を介してワイヤードオアし、レシーバ回路
に入力する構成となっていた。
Prior Art Conventionally, in this type of signal transmission system, a switch circuit of each of a plurality of driver circuits is provided with, for example, an oven collector output TTL (transistor-tr
Ansistor logic) circuits are used, and the output signals from these driver circuits are wire-ORed via daisy-chained signal lines and input to a receiver circuit.

このような従来の信号伝達システムでは、複数のドライ
バ回路各々の出力回路がスイッチ回路がら構成されてい
るので、ディジーチェイン接続の信号線を介してワイヤ
ードオアした場合、ドライバ回路の出力としてはすべて
のスイッチ回路がオフか、またはそれ以外かの2通りの
状態判別しかできないため、ドライブした特定のドライ
バ回路を検出することかできないという欠点がある。
In such a conventional signal transmission system, the output circuit of each of the multiple driver circuits is composed of a switch circuit, so when wired-OR is performed via a daisy chain connected signal line, all the outputs of the driver circuits are Since it is possible to determine only two states, ie, whether the switch circuit is off or not, there is a drawback that the specific driver circuit driven cannot be detected.

発明の目的 本発明は上記のような従来のものの欠点を除去すべくな
されたもので、ドライブした特定のドライバ回路を検出
することができる信号伝達システムの提供を目的とする
OBJECTS OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional system, and it is an object of the present invention to provide a signal transmission system capable of detecting a specific driver circuit driven.

発明の構成 本発明による信号伝達システムは、各々第1の信号線に
よりディジーチェイン接続された複数のドライバ回路か
らの出力信号を前記第1の信号線を介してレシーバ回路
に入力する信号伝達システムであって、前記複数のドラ
イバ回路をディジーチェイン接続する第2の信号線と、
前記複数のドライバ回路各々に設けられ、夫々自回路を
特定するための抵抗値を有する複数のプルアップ抵抗器
と、前記複数のドライバ回路各々に設けられ、前記プル
アップ抵抗器と前記第2の信号線との接続をオンオフす
る複数のスイッチング手段と、前記複数のドライバ回路
各々に設けられ、前記第1の信号線に出力する特定信号
に応して前記スイッチング手段の接続を制御する複数の
制御手段と、前記第2の信号線を介して入力される電圧
値に応して前記特定信号を送出したドライバ回路を判別
する判別手段とを有することを特徴とする。
Configuration of the Invention A signal transmission system according to the present invention is a signal transmission system in which output signals from a plurality of driver circuits each connected in a daisy chain by a first signal line are inputted to a receiver circuit via the first signal line. a second signal line connecting the plurality of driver circuits in a daisy chain;
a plurality of pull-up resistors provided in each of the plurality of driver circuits, each having a resistance value for specifying its own circuit; and a plurality of pull-up resistors provided in each of the plurality of driver circuits, the pull-up resistor and the second a plurality of switching means for turning on and off connections with the signal line; and a plurality of controls provided in each of the plurality of driver circuits and controlling the connection of the switching means in response to a specific signal output to the first signal line. and a discriminating means for discriminating the driver circuit that has sent out the specific signal in accordance with the voltage value input via the second signal line.

実施例 次に、本発明の一実施例について図面を参照して説明す
る。
Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の構成を示すブロック図であ
る。図において、複数のドライバ回路1−i (i =
1.2. ・・・・・−、n)とレシーバ回路4とは信
号線100.lotによりディジーチェイン接続されて
いる。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a plurality of driver circuits 1-i (i =
1.2. . . . -, n) and the receiver circuit 4 are connected to the signal line 100. connected in a daisy chain by lots.

ドライバ回路1−iには夫々信号線1ullに接続され
た制御回路2−1と、一端がプルアップ電源(■。C)
に接続され、他端が各々自回路を特定するための抵抗値
を有する、すなわち各々異なる抵抗値が割り当てられた
プルアップ抵抗器Rjを介して信号線100に接続され
たスイッチ回路3−1とが設けられている。
The driver circuits 1-i each have a control circuit 2-1 connected to the signal line 1ull, and one end connected to a pull-up power supply (■.C).
and a switch circuit 3-1 whose other end is connected to the signal line 100 via a pull-up resistor Rj, each having a resistance value for specifying its own circuit, that is, each of which is assigned a different resistance value. is provided.

レシーバ回路4には信号線100と、一端がグランドに
接地された抵抗器ROの他端との接続点の電位V1をA
/D (アナログ/ディジタル)変換するA/D変換回
路5と、異常が発生し、障害報告を送出したドライバ回
路1−iを判別する判別処理などを行うCPU (中央
処理装置)6と、出方端子7とが設けられている。
The receiver circuit 4 has a potential V1 at the connection point between the signal line 100 and the other end of the resistor RO whose one end is grounded.
/D (Analog/Digital) conversion circuit 5, CPU (Central Processing Unit) 6, which performs determination processing to determine which driver circuit 1-i has generated an abnormality and has sent a failure report, and output. A terminal 7 is provided on both sides.

この第1図を用いて本発明の一実施例の動作について説
明する。
The operation of one embodiment of the present invention will be explained using FIG.

ドライバ回路1−1の制御回路2−1により異常が検出
された場合、制御回路2−1はスイッチ回路3−iをオ
ンとするとともに、ディジーチェイン接続の信号線10
1を介してレシーバ回路4のCPU6にその異常を通知
する。
When an abnormality is detected by the control circuit 2-1 of the driver circuit 1-1, the control circuit 2-1 turns on the switch circuit 3-i and turns on the signal line 10 of the daisy chain connection.
1 to notify the CPU 6 of the receiver circuit 4 of the abnormality.

CPU6は制御回路2−1からの異常通知を受信すると
、異常が検出されたドライバ回路のスイッチ回路(ここ
ではスイッチ回路3−1)以外のすべてのスイッチ回路
(ここではスイッチ回路3−2〜3−n)かオンになら
ないように、すべての制御回路2−iに対してインハイ
ピット(1nhibit )信号を出力する。
Upon receiving the abnormality notification from the control circuit 2-1, the CPU 6 switches all the switch circuits (here, switch circuits 3-2 to 3-3) except the switch circuit of the driver circuit in which the abnormality has been detected (here, switch circuit 3-1). -n) is outputted to all the control circuits 2-i to prevent them from turning on.

これにより、ドライバ回路1〜Iのスイッチ回路3−1
のみがオンとなり、他のドライバ回路1−2〜1−nの
スイッチ回路3−2〜B−nはオフのままとなる。
As a result, switch circuit 3-1 of driver circuits 1 to I
switch circuits 3-2 to B-n of the other driver circuits 1-2 to 1-n remain off.

よって、信号線100と抵抗器ROの他端との接続点の
電位V1は、 Vl = (RO/R1+RO)  ・Vccとなる。
Therefore, the potential V1 at the connection point between the signal line 100 and the other end of the resistor RO is Vl=(RO/R1+RO)·Vcc.

ドライバ回路1−2の制御回路2−2により異常が検出
された場合にも、上述の動作と同様にして、ドライバ回
路1−2のスイッチ回路3−2のみがオンとなり、他の
ドライバ回路1−1.1−3〜1−nのスイッチ回路3
−1. 3−3〜3−nがオフのままとなるので、電位
v1は、 Vl  =、  (RO/R2+RO)  ’ Vcc
となる。
Even when an abnormality is detected by the control circuit 2-2 of the driver circuit 1-2, only the switch circuit 3-2 of the driver circuit 1-2 is turned on, similar to the operation described above, and the other driver circuits 1-2 are turned on. -1.1-3 to 1-n switch circuit 3
-1. Since 3-3 to 3-n remain off, the potential v1 is Vl =, (RO/R2+RO) 'Vcc
becomes.

また、ドライバ回路1−nの制御回路2−nにより異常
が検出された場合にも、上述の動作と同様にして、ドラ
イバ回路1−nのスイッチ回路3−nのみがオンとなり
、他のドライバ回路1−1〜1−(n−1)のスイッチ
回路3−1〜3−(n−1)がオフのままとなるので、
電位v1は、 Vl −(RO/Rn +RO)  ’Vo。
Further, even when an abnormality is detected by the control circuit 2-n of the driver circuit 1-n, only the switch circuit 3-n of the driver circuit 1-n is turned on, similar to the operation described above, and the other drivers Since the switch circuits 3-1 to 3-(n-1) of circuits 1-1 to 1-(n-1) remain off,
The potential v1 is Vl-(RO/Rn+RO)'Vo.

となる。becomes.

A/D変換回路5は電位vlをA/D変換してCPU6
に送出するので、CPU6てはA/D変換回路5からの
値によりドライバ回路1−iを特定することができる。
The A/D conversion circuit 5 A/D converts the potential vl and sends it to the CPU 6.
Therefore, the CPU 6 can specify the driver circuit 1-i based on the value from the A/D conversion circuit 5.

スナワチ、電位VlがVi −(RO/Ri +RO)
・VCCのときにはドライバ回路1−iがドライブした
ことを判別することができる。
Sunawachi, the potential Vl is Vi - (RO/Ri +RO)
- When the voltage is VCC, it can be determined that the driver circuit 1-i is driving.

このように、信号線100,101によりディジーチェ
イン接続されたドライバ回路1−i夫々に自回路を特定
するための抵抗値を有するプルアップ抵抗器R1と、一
端かプルアップ電源(V cc)に接続され、他端がプ
ルアップ抵抗器Riを介して信号線100に接続された
スイッチ回路3−iと、異常検出時にスイッチ回路3−
iの接続を制御する制御回路2−iとを設け、ドライバ
回路1−1の制御回路2−1で異常が検出された場合に
、A/D変換回路5によりA/D変換された電位V1の
値に応してCPU6で障害報告を出力したドライバ回路
1−iを判別するようにすることによって、ドライブし
た特定のドライバ回路1−jを検出することができる。
In this way, each driver circuit 1-i connected in a daisy chain by the signal lines 100 and 101 is provided with a pull-up resistor R1 having a resistance value for specifying its own circuit, and one end connected to the pull-up power supply (Vcc). A switch circuit 3-i is connected to the switch circuit 3-i, the other end of which is connected to the signal line 100 via a pull-up resistor Ri, and a switch circuit 3-i that is
A control circuit 2-i is provided to control the connection of the driver circuit 2-i, and when an abnormality is detected in the control circuit 2-1 of the driver circuit 1-1, the potential V1 which is A/D converted by the A/D conversion circuit 5 is provided. By having the CPU 6 determine the driver circuit 1-i that outputs the failure report according to the value of , it is possible to detect the specific driver circuit 1-j that has been driven.

たとえば、コンピュータシステムにおいてはどの装置が
異常となったかを特定することができるため、該システ
ムの保守交換時間を大幅に短縮することができる。
For example, since it is possible to specify which device has become abnormal in a computer system, maintenance and replacement time for the system can be significantly reduced.

発明の詳細 な説明したように本発明によれば、複数のドライバ回路
各々に、夫々自回路を特定するための抵抗値を有するプ
ルアップ抵抗器と、このプルアップ抵抗器とディジーチ
ェイン接続の信号線との接続をオンオフするスイッチン
グ手段と、出力される障害報告に応してスイッチング手
段の接続を制御する制御手段とを設け、該信号線を介し
て入力される電圧値に応して障害報告を送出したドライ
バ回路を判別するようにすることによって、ドライブし
た特定のドライバ回路を検出することができるという効
果がある。
DETAILED DESCRIPTION OF THE INVENTION According to the present invention, each of the plurality of driver circuits includes a pull-up resistor having a resistance value for specifying its own circuit, and a signal connected to the pull-up resistor in a daisy chain. A switching means for turning on and off the connection to the line, and a control means for controlling the connection of the switching means according to the fault report output, are provided, and the fault report is made according to the voltage value inputted through the signal line. By determining the driver circuit that has sent out the signal, it is possible to detect the specific driver circuit that has driven the signal.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の構成を示すプロ・ンク図で
ある。 主要部分の符号の説明 1−1〜1−n・・・・・・ドライバ回路2−1〜2−
n・・・・・・制御回路 3−1〜3−n・・・・・・スイッチ回路5・・・・・
・A/D変換回路 6・・・・・・CPU
FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1-1 to 1-n...Driver circuit 2-1 to 2-
n...Control circuit 3-1 to 3-n...Switch circuit 5...
・A/D conversion circuit 6...CPU

Claims (1)

【特許請求の範囲】[Claims] (1)各々第1の信号線によりデイジーチェイン接続さ
れた複数のドライバ回路からの出力信号を前記第1の信
号線を介してレシーバ回路に入力する信号伝達システム
であって、前記複数のドライバ回路をデイジーチェイン
接続する第2の信号線と、前記複数のドライバ回路各々
に設けられ、夫々自回路を特定するための抵抗値を有す
る複数のプルアップ抵抗器と、前記複数のドライバ回路
各々に設けられ、前記プルアップ抵抗器と前記第2の信
号線との接続をオンオフする複数のスイッチング手段と
、前記複数のドライバ回路各々に設けられ、前記第1の
信号線に出力する特定信号に応じて前記スイッチング手
段の接続を制御する複数の制御手段と、前記第2の信号
線を介して入力される電圧値に応じて前記特定信号を送
出したドライバ回路を判別する判別手段とを有すること
を特徴とする信号伝達システム。
(1) A signal transmission system that inputs output signals from a plurality of driver circuits each connected in a daisy chain by a first signal line to a receiver circuit via the first signal line, the plurality of driver circuits a second signal line for daisy chain connection of the plurality of driver circuits, a plurality of pull-up resistors provided in each of the plurality of driver circuits and each having a resistance value for specifying its own circuit, and a plurality of pull-up resistors provided in each of the plurality of driver circuits. and a plurality of switching means for turning on and off the connection between the pull-up resistor and the second signal line, and a plurality of switching means provided in each of the plurality of driver circuits, according to a specific signal output to the first signal line. It is characterized by comprising a plurality of control means for controlling the connection of the switching means, and a discrimination means for discriminating the driver circuit that has sent out the specific signal according to a voltage value inputted through the second signal line. signal transmission system.
JP2216163A 1990-08-16 1990-08-16 Signal transmission system Pending JPH0498950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2216163A JPH0498950A (en) 1990-08-16 1990-08-16 Signal transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2216163A JPH0498950A (en) 1990-08-16 1990-08-16 Signal transmission system

Publications (1)

Publication Number Publication Date
JPH0498950A true JPH0498950A (en) 1992-03-31

Family

ID=16684282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2216163A Pending JPH0498950A (en) 1990-08-16 1990-08-16 Signal transmission system

Country Status (1)

Country Link
JP (1) JPH0498950A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008234266A (en) * 2007-03-20 2008-10-02 Nec Corp Failure processing system, electronic equipment and failure processing method
WO2014203678A1 (en) * 2013-06-20 2014-12-24 富士電機株式会社 Semiconductor module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6068450A (en) * 1983-09-22 1985-04-19 Matsushita Electric Ind Co Ltd Interruption request circuit
JPS61100854A (en) * 1984-10-22 1986-05-19 Fujitsu Ltd Signal processing circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6068450A (en) * 1983-09-22 1985-04-19 Matsushita Electric Ind Co Ltd Interruption request circuit
JPS61100854A (en) * 1984-10-22 1986-05-19 Fujitsu Ltd Signal processing circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008234266A (en) * 2007-03-20 2008-10-02 Nec Corp Failure processing system, electronic equipment and failure processing method
WO2014203678A1 (en) * 2013-06-20 2014-12-24 富士電機株式会社 Semiconductor module
JPWO2014203678A1 (en) * 2013-06-20 2017-02-23 富士電機株式会社 Semiconductor module
US9906009B2 (en) 2013-06-20 2018-02-27 Fuji Electric Co., Ltd. Semiconductor module

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