JP3710114B2 - Data bus circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data bus circuit, and more particularly to a data bus circuit that is used in a control processing unit of a digital processing apparatus and collects information.
[0002]
[Prior art]
In digital processing apparatuses such as computers, a plurality of devices such as processors and various memories are used. Data transmission / reception is performed between these devices, but it is not always necessary to connect them. Therefore, it is common to provide a signal transmission path composed of one or more conductors called a data bus, and to connect to the data bus when necessary to transmit and receive data between devices. This simplifies the configuration. Alternatively, an output signal is selectively output to the common data bus.
[0003]
A conventional data bus circuit used in a control system processing unit of a digital processing apparatus generally has a data reception signal bus connected from the control unit directly to the output of each part circuit of a number of part circuits in the system. It is connected. Signals are transmitted and received by controlling the output of each part circuit so that the output signals do not overlap. With such a configuration, the number of signal lines between the control unit and the plurality of partial circuits is significantly reduced, and the circuit scale is also reduced, thereby making it possible to reduce the size.
[0004]
FIG. 3 shows an example of a conventional data bus circuit. FIG. 4 shows an operation timing chart of the data bus circuit of FIG.
[0005]
In the conventional system shown in FIG. 3, the system is composed of one control unit 1 and n (positive integer) part circuits 2a, 2b,..., 2n (only 2a and 2b are shown in FIG. 3). Is done. A control signal from the control unit 1 is commonly input to the respective part circuits 2 a to 2 n via the control bus 5. The output signals of the respective part circuits 2a to 2n are output to the data bus 6 through the output buffers 3a to 3n, respectively, and are input to the control unit 1 and connected to the common resistor 4.
[0006]
Next, the operation of the conventional system of FIG. 3 will be described with reference to the timing chart of FIG. First, the control unit 1 outputs a control signal 2-1 (see FIG. 4A) to the control bus (or line) 5. The control signal 2-1 is input to the part circuits 2a to 2n, and only the part circuit (for example, 2a) that receives the request from the control unit 1 takes in the control signal 2-1 and performs processing according to the request. . This part circuit places the processing results in the output buffer 3 as response signals 2-2 and 2-4 (see FIGS. 4B and 4D). At the same time, output control signals 2-3 and 2-5 indicating the validity of the response signals 2-2 and 2-4 are sent to the control terminal of the output buffer 3 (see FIGS. 4C and 4E).
[0007]
The output buffer 3 places the response signals 2-2 and 2-4 on the data bus 6 under the control of the output control signals 2-3 and 2-5, and sends the signals to the control unit 1 (see FIG. 4 (f)). Send. As apparent from FIG. 4 (f), only the output buffer 3 that receives the control signals 2-3 and 2-5 places the response signal on the data bus 6, so that the plurality of part circuits 2 a to 2 n are simultaneously applied to the data bus 6. No response signal is output.
[0008]
[Problems to be solved by the invention]
As described above, in the prior art, a large number of part circuits 2a to 2n are connected to the control unit 1 that collects information, and information is efficiently collected therefrom and the circuit scale is reduced. However, while simplifying the circuit configuration and increasing the efficiency, information collection is entrusted to a single bus, and the outputs of the multiple part circuits 2a to 2n are directly connected in parallel to the data bus. Therefore, there is a problem that even if an abnormality on the circuit or an error (error) occurs in the collected information, the occurrence location cannot be determined quickly.
[0009]
This is because the configuration of the data bus circuit can only monitor abnormality of data being communicated. Although an abnormality or circuit failure and communication abnormality in each part circuit can be determined, it has occurred in a situation where it is impossible to determine which part circuit affects the failure or communication abnormality on the data bus circuit. The identification of such a failure location is considered to be one of very important functions in recent digital processing devices and data transmission devices, and has a great influence on the identification or recovery of the failure location of the device.
[0010]
An object of the present invention is to provide a data bus circuit that has a function of facilitating maintenance or maintenance (maintenance) of a device by enabling specification of a failure location in the event of a circuit failure or line abnormality.
[0011]
[Means for Solving the Problems]
In order to solve the above-described problems, the data bus circuit according to the present invention employs the following characteristic configuration.
[0012]
(1) A data bus that includes a control unit and a plurality of part circuits that receive a control signal from the control part and output a corresponding output signal, and inputs the output of the part circuit to the control unit via a data bus In the circuit
Providing a plurality of output buffers in which the output of the part circuit is input to an output control terminal;
The data bus is a data bus circuit configured by sequentially connecting the output of the output buffer to which the output of the subsequent partial circuit among the plurality of partial circuits is connected to the input terminal of the preceding output buffer.
[0013]
(2) The data bus circuit according to (1), wherein the control signal of the control unit is input to the plurality of part circuits via a common control line.
[0014]
(3) The data bus circuit according to (1), further including a test circuit unit that receives a control signal from the control unit and inputs a failure location determination test signal to the output buffer.
[0015]
(4) The data bus circuit according to (3), wherein the test signal of the test circuit unit is input to the output control terminal of the test output buffer connected in series with the output buffer and having an output control terminal.
[0016]
(5) The data bus circuit according to (1), (2), (3) or (4) used in the control system processing unit of the digital processing device.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the configuration and operation of a preferred embodiment of the data bus circuit according to the present invention will be described in detail with reference to FIG. 1 and FIG.
[0018]
FIG. 1 is a block diagram of a preferred embodiment of a data bus circuit according to the present invention. FIG. 2 is a timing chart for explaining the operation of each part of the data bus circuit of FIG.
[0019]
The configuration of the data bus circuit according to the present invention will be described with reference to FIG. This data bus circuit includes a control unit 10, n (in this example, three) part circuits 12a, 12b, and 12c, and a pair of output buffers 13a to 13c and 14a to 14c connected in series between the power supply VDD and the ground. And the load resistors 15a to 15c, the control signal bus 16 connected from the control unit 10 to the input side of each of the part circuits 12a to 12c, and the input buffers 14b, 14a to the output buffers 14b, 14a of the previous stage Alternatively, the data buses 17c, 17b, and 17a are sequentially connected to the input terminal of the control unit 10, and the test circuit unit 20 is connected to the output side of the control unit 10.
[0020]
The control unit 10 sends commands to the respective part circuits 12a to 12c, collects information, and controls the corresponding part circuits 12a to 12c based on the information. Each part circuit 12a-12c is controlled by the command or control signal output from the control part 10, and outputs a corresponding response signal to the output buffers 14a-14c. The output buffers 14a to 14c place response signals from the respective part circuits 12a to 12c on the data buses 17a to 17c. The test circuit unit 20 sends a test signal to the test output buffers 13a to 13c connected in series to the output buffers 14a to 14c. The test output buffers 13a to 13c receive test signals sent from the test circuit unit 20, and are connected to the pre-stage data buses 17b and 17c on the input side of the output buffers 14a to 14c.
[0021]
Each of the data buses 17a to 17c is connected to a load resistor or a power supply VDD for guaranteeing the H level via a pull-up resistor 15a to 15c.
[0022]
In this data bus circuit, when the circuit is normal and there is no failure or the like, the control signal output from the control unit 10 is input to each of the part circuits 12a to 12c and the test circuit unit 20. The control unit 10 takes in the control signal only from the part circuit for which an answer is requested. The part circuit 12 processes the request and sends a response signal to the output control inputs of the output buffers 14a to 14c. Therefore, the output buffers 14a to 14c receive response signals from the partial circuits 12a to 12c, and turn on / off the outputs under the control of the response signals. The data bus 17 of the previous stage is input to the input terminal of the output buffer 14. That is, the data bus 17b is connected to the output buffer 14a, and the data bus 17c is connected to the output buffer 14b. Since all the output buffers other than the part circuit 12 for which a response is requested are in the ON state, the input terminal of the output buffer 14 that responds is at the L level.
[0023]
In addition, the test output buffer 13 is turned off by the test signal from the test circuit unit 20 except for the final stage buffer 13, and has a high impedance. The final-stage test output buffer 13c is normally on and outputs an L level. Therefore, the output buffer 14 connected to the part circuit 12 that actually requires a response corresponds to data corresponding to the L level when turned on and the H level when turned off by controlling the response signal of the part circuit 12. Output to the bus 17. This signal passes through the next-stage output buffer 14 whose control terminal is turned on, is finally transmitted to the data bus 17a, and is input to the control unit 10. This signal is recognized as a response signal of the target part circuit 12 in the control unit 10 and is determined to have been processed normally.
[0024]
Next, a case where a failure occurs in the data bus circuit will be described. In this case, a normal response does not return to the control unit 10. The individual test of each part circuit 12 is started by a control signal from the control unit 10.
[0025]
First, a target part circuit (for example, 12b) is determined. For each part circuit (for example, 12a) before that, the control terminal of the corresponding output buffer 14 is turned off to make the output high impedance. In each subsequent circuit (for example, 12c), the control terminal of the corresponding output buffer 14 is turned on, and the output is set to through. Next, the output control terminal of the test output buffer 13 of the target part circuit 12 a is turned on by a test signal from the test circuit unit 20. As a result, the output is set to L level. As a result, the target part circuit 12 is completely in one-to-one correspondence with the control unit 10, and the normality of the circuit and the state of the line can be freely confirmed without being influenced by the outside. Here, if the response to the control unit 10 is normal, it is determined that the target part circuit (for example, 12b) and the subsequent data bus 17 and output buffer 14 are normal. Therefore, the failure is other than the target part circuit 12.
[0026]
If the response to the control unit 10 is abnormal in this state, the target part circuit (12b) or the subsequent output buffer 14 is abnormal, or the output buffer 14 in the previous stage is abnormal. Can be squeezed. Further, by shifting the target part circuit 12 back and forth, the troubled part can be further reduced.
[0027]
Next, FIG. 2 showing an operation timing chart of the data bus circuit of FIG. 1 will be briefly described. Since the operation of the data bus circuit is as described above, the timing charts (a) to (j) will be described.
[0028]
(A) is a control signal 4-1 sent from the control unit 10 to each of the part circuits 12a to 12c.
(B) is a control signal 4-2 taken by the part circuit 12.
(C) is a response signal 4-3 from the part circuit 12.
(D) is a data bus signal 4-4 output from the output buffer 14 to the data bus 17.
(E) is a data bus signal 4-5 in the case of a circuit failure or a data bus failure.
(F) is a normal signal 4-6 when the response signal from the part circuit 12 is normal.
(G) is an abnormal signal 4-7 in which the response signal from the part circuit 12 is abnormal.
(H) is a signal 4-8 when each response signal from each part circuit 12 is normal.
(I) is a signal 4-9 when each response signal from each part circuit 12 is abnormal.
(J) is a signal 4-10 of the data bus 17 when the response signal from the part circuit 12 is abnormal.
[0029]
As described above, the data bus circuit according to the present invention provides a data bus circuit with a monitoring function by providing a control unit, a plurality of part circuits, an output buffer, a test output buffer, and a test circuit unit. However, the present invention should not be limited to such specific examples, and various modifications and changes can be made without departing from the gist of the present invention. For example, the number of partial circuits included in the data bus circuit can be selected as an arbitrary number according to the application.
[0030]
【The invention's effect】
As can be understood from the above description, according to the data bus circuit of the present invention, the operation of the entire apparatus can be ensured by providing a test circuit unit capable of monitoring the operation of each part circuit or between part circuits. Will improve.
[Brief description of the drawings]
FIG. 1 is a block diagram of a preferred embodiment of a data bus circuit according to the present invention.
FIG. 2 is an operation timing chart of the data bus circuit of FIG.
FIG. 3 is a configuration diagram of a conventional data bus circuit.
4 is an operation timing chart of the data bus circuit of FIG. 4;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Control part 12a-12c Part circuit 13a-13c Test output buffer 14a-14c Output buffer 16 Control signal bus | bath 17a-17c Data bus 20 Test circuit part

Claims (5)

In a data bus circuit that includes a control unit and a plurality of part circuits that receive a control signal from the control unit and output a corresponding output signal, and that inputs the output of the part circuit to the control unit via a data bus,
Providing a plurality of output buffers in which the output of the part circuit is input to an output control terminal;
The data bus is configured by sequentially connecting the output of the output buffer to which the output of the subsequent stage circuit among the plurality of partial circuits is connected to the input terminal of the output buffer of the previous stage. circuit. The data bus circuit according to claim 1, wherein a control signal of the control unit is input to the plurality of part circuits through a common control line. The data bus circuit according to claim 1, further comprising a test circuit unit that receives a control signal from the control unit and inputs a failure location determination test signal to the output buffer. 4. The data bus circuit according to claim 3, wherein a test signal of the test circuit unit is input to the output control terminal of a test output buffer connected in series with the output buffer and having an output control terminal. 5. The data bus circuit according to claim 1, wherein the data bus circuit is used in a control system processing unit of a digital processing device.

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