JPH0494122A - Double side abrasion of thin plate - Google Patents
Double side abrasion of thin plateInfo
- Publication number
- JPH0494122A JPH0494122A JP2213325A JP21332590A JPH0494122A JP H0494122 A JPH0494122 A JP H0494122A JP 2213325 A JP2213325 A JP 2213325A JP 21332590 A JP21332590 A JP 21332590A JP H0494122 A JPH0494122 A JP H0494122A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- carrier
- polishing
- thickness
- cut
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005299 abrasion Methods 0.000 title 1
- 238000005498 polishing Methods 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000000843 powder Substances 0.000 abstract description 8
- 239000003822 epoxy resin Substances 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 229920000647 polyepoxide Polymers 0.000 abstract description 3
- 125000006850 spacer group Chemical group 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 72
- 238000010586 diagram Methods 0.000 description 8
- 238000009826 distribution Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012776 electronic material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000012050 conventional carrier Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- IYLGZMTXKJYONK-ACLXAEORSA-N (12s,15r)-15-hydroxy-11,16-dioxo-15,20-dihydrosenecionan-12-yl acetate Chemical compound O1C(=O)[C@](CC)(O)C[C@@H](C)[C@](C)(OC(C)=O)C(=O)OCC2=CCN3[C@H]2[C@H]1CC3 IYLGZMTXKJYONK-ACLXAEORSA-N 0.000 description 1
- 229910003327 LiNbO3 Inorganic materials 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- IYLGZMTXKJYONK-UHFFFAOYSA-N ruwenine Natural products O1C(=O)C(CC)(O)CC(C)C(C)(OC(C)=O)C(=O)OCC2=CCN3C2C1CC3 IYLGZMTXKJYONK-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Landscapes
- Grinding Of Cylindrical And Plane Surfaces (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体ウェハーや電子材料基板などの薄板の研磨方法の
改善に関し、
ウェハー厚みのバラツキを少なくして、厚みを均一化す
るように研磨することを目的とし、切り欠き部を有する
円形薄板からなる被加工物(例えば、半導体ウェハー)
をキャリヤに保持して両面研磨する研磨方法において、
被加工物を保持せしめるキャリヤの真円孔に該被加工物
を嵌め込み、同時に、真円孔が満たされていない前記切
り欠き部に該切り欠き部と同形の薄板を嵌め込んで両面
研磨するようにしたことを特徴とする。[Detailed Description of the Invention] [Summary] Regarding the improvement of a method for polishing thin plates such as semiconductor wafers and electronic material substrates, the present invention aims to reduce variations in wafer thickness and polish the wafer so that the thickness is uniform. A workpiece consisting of a circular thin plate with a notch (e.g. a semiconductor wafer)
In a polishing method in which both surfaces are polished while holding the workpiece in a carrier, the workpiece is fitted into a perfect circular hole in the carrier that holds the workpiece, and at the same time, the notch is inserted into the notch portion where the perfect circular hole is not filled. The feature is that a thin plate of the same shape as the part is inserted and both sides are polished.
〔産業上の利用分野1
本発明は半導体ウェハーや電子材料基板などの薄板の両
面研磨法の改善に関する。[Industrial Application Field 1] The present invention relates to an improvement in a method for double-sided polishing of thin plates such as semiconductor wafers and electronic material substrates.
例えば、LSIなどの半導体デバイスは半導体ウェハー
(以下、ウェハーと呼ぶ)の表面に微細素子が多数形成
されているが、その集積度は年々増大しており、一方で
は合理化のためにウェハーは益々大口径になっている。For example, in semiconductor devices such as LSI, many microscopic elements are formed on the surface of a semiconductor wafer (hereinafter referred to as a wafer), but the degree of integration is increasing year by year, and on the other hand, wafers are becoming larger and larger due to rationalization. It has a caliber.
従って、大口径ウェハーに微細素子を多数形成しなけれ
ばならないために、製造歩留や品質の維持ないし向上が
次第に困難になっており、本発明はその基礎になるウェ
ハー厚みの均一化に関している。Therefore, it is becoming increasingly difficult to maintain or improve manufacturing yield and quality because a large number of fine elements must be formed on a large-diameter wafer, and the present invention relates to uniformity of wafer thickness, which is the basis for this.
〔従来の技術]
例えば、シリコンウェハーは引上げ法または帯域溶融法
によって円筒状、の単結晶インゴットに作成して、この
インゴットは高速回転する内周刃によってスライシング
(Slicing) シてウェハーに裁断される。この
粗ウェハーをラッピング(Lapping)して平坦な
粗面にしたのち、ウェハー周縁の面取り(ベベリング;
Bevel ing)をおこない、次いで、ウェハー
をポリッシュ(Polish ;研磨)してウェハー表
面の加工歪や欠陥を除去し、且つ、半導体素子形成の可
能な鏡面を有するウェハーに仕上げている。[Prior Art] For example, a silicon wafer is made into a cylindrical single crystal ingot by a pulling method or a zone melting method, and this ingot is cut into wafers by slicing with a high-speed rotating internal blade. . After this rough wafer is lapped to make it a flat rough surface, the wafer periphery is beveled;
Then, the wafer is polished to remove processing distortions and defects on the wafer surface, and is finished into a wafer with a mirror surface on which semiconductor elements can be formed.
そのような粗ウェハーの両面をラッピング、またはポリ
ッシュする方法に関しており、従来は片面研磨が主流で
あったが、最近は加工精度の向上の要求から両面研磨法
が汎用されつつある。第4図はそのような両面研磨用の
ウェハー研磨装置の概要斜視図を示しており、記号1は
ウェハー、2はウェハーを保持するキャリヤ、3は駆動
部で、キャリヤ2の4つの孔にウェハー1を嵌め込み、
駆動部3を中心にしてギヤによってキャリヤ2を回転さ
せながら、キャリヤ2自身もまた回転しながら、そのよ
うな遊星運動によってウェハーの両面が研磨される。図
示されていないが、ウェハー1を保持したギヤリヤ2は
ポリウレタン含浸ポリエステル不織布などからなる研磨
布を被覆した2枚の定盤(テーブル)に挟持されて押圧
されており、この2枚の定盤もまたお互に逆方向に回転
している。そのように回転させて、微粉末を懸濁したエ
ツチング液を滴下しながらウェハーを研磨すると、均一
に研磨される。この研磨法はメカノケミカル研磨と呼ば
れているが、微粉末(径0.05μmのパウダー)によ
る機械的研磨とアルカリなどのエツチング溶液による化
学的研磨との相乗作用によって研磨が進行するわけであ
る。The present invention relates to a method of lapping or polishing both sides of such a rough wafer. Conventionally, single-sided polishing was the mainstream, but recently, due to the demand for improved processing accuracy, double-sided polishing has become widely used. FIG. 4 shows a schematic perspective view of such a wafer polishing apparatus for double-sided polishing, in which symbol 1 is a wafer, 2 is a carrier that holds the wafer, and 3 is a drive unit, and the wafer is inserted into the four holes of the carrier 2. Insert 1,
While the carrier 2 is rotated by the gear around the drive unit 3, the carrier 2 itself also rotates, and both sides of the wafer are polished by such planetary motion. Although not shown, the gear 2 holding the wafer 1 is held between and pressed by two surface plates (tables) covered with an abrasive cloth made of polyurethane-impregnated polyester nonwoven fabric, etc., and these two surface plates are also They also rotate in opposite directions. By rotating the wafer in this manner and polishing the wafer while dropping the etching liquid in which fine powder is suspended, the wafer is polished uniformly. This polishing method is called mechanochemical polishing, and polishing progresses through the synergistic effect of mechanical polishing using fine powder (powder with a diameter of 0.05 μm) and chemical polishing using an etching solution such as alkali. .
次の第5図は従来のウェハーを保持したキャリヤの平面
図を示しており、lはウェハー、2はキャリヤ、4はギ
ヤ(歯車)である。キャリヤ2の厚みは研磨後のウェハ
ー1の厚みの273程度にすることが多く、例えば、口
径150mmφ、厚み620μmのシリコンウェハーに
対してキャリヤは厚み約430μmのものを使用して、
そのキャリヤの材質は例えばエポキシ樹脂を用いている
。The following FIG. 5 shows a plan view of a conventional carrier holding a wafer, where l is the wafer, 2 is the carrier, and 4 is a gear. The thickness of the carrier 2 is often about 273 times the thickness of the wafer 1 after polishing. For example, for a silicon wafer with a diameter of 150 mmφ and a thickness of 620 μm, a carrier with a thickness of about 430 μm is used.
The material of the carrier is, for example, epoxy resin.
なお、図のように、ウェハー1には定形の切り欠き部C
があり、その直線5の部分をオリエンティションフラッ
トライン(OFライン)と称し、結晶方位を示す重要な
ラインである。このOFライン5は単結晶インゴットの
ときに結晶方位を測定して研削されて作成される。As shown in the figure, the wafer 1 has a regular notch C.
The straight line 5 is called the orientation flat line (OF line) and is an important line that indicates the crystal orientation. This OF line 5 is created by measuring the crystal orientation of a single crystal ingot and grinding it.
ところで、上記のようなウェハー研磨装置を用いて両面
を研磨する理由はウェハーの厚みを精度良く均一にする
ことが目的であるが、ウェハーが真円ではなくてOFラ
インが形成されていて、切り欠き部を有することに問題
があり、そのために、ウェハーの厚みが均一化されにく
い欠点がある。By the way, the reason why both sides are polished using the above-mentioned wafer polishing equipment is to make the thickness of the wafer uniform with high precision. There is a problem in that the wafer has a notch, which makes it difficult to make the thickness of the wafer uniform.
第2図(b)に従来の研磨後のウェハー等厚線図を示し
ており、この図は6インチφ(口径150mmφ)、厚
み620tImのウェハーの厚み変化を例示したもので
、図中の線は等原線であり、その等原線間隔は0.1μ
mにしである。この図から判かるように、従来の研磨方
法ではウェハーはOFライン5の部分が最も厚みが薄く
なって、テーパー状に形成されている。これは切り欠き
部があるために、ウェハー面への加圧が均一ではなくて
加圧分布が生じており、しかも、その切り欠き部の隙間
に研磨粉が溜ってその周囲の研磨が進むためと考えられ
る。Figure 2(b) shows a conventional wafer iso-thickness diagram after polishing, and this figure illustrates the thickness change of a wafer with a diameter of 6 inches (diameter 150 mm) and a thickness of 620 tIm. is an isogene line, and the isogene spacing is 0.1μ
It's at m. As can be seen from this figure, in the conventional polishing method, the wafer is formed into a tapered shape with the thickness being the thinnest at the OF line 5. This is because due to the notch, the pressure applied to the wafer surface is not uniform and the pressure is distributed, and moreover, polishing powder accumulates in the gap between the notches and polishing progresses around the area. it is conceivable that.
この第2図は1枚のウェハーを例示したものであるが、
第3図(b)は多数ウェハーを測定した従来のTTV値
の分布を示す図で、T T V (Total Th1
ckness Variation )とはウェハー内
の最も厚い部分と最も薄い部分の差を表わした評価値で
ある。This figure 2 illustrates one wafer, but
FIG. 3(b) is a diagram showing the distribution of conventional TTV values measured on a large number of wafers.
ckness Variation) is an evaluation value representing the difference between the thickest part and the thinnest part within the wafer.
横軸はTTV値(μm)、縦軸は全ウェハーに対する占
有ウェハー数の比率(%)であるが、これより従来は平
均のTTV値が1.21μm、TTV値が1μm以下の
ウェハー比率が42%程度であることが判る。このよう
なTTV値は小さいほど良いことは当然であるが、少な
くとも殆どのウェハーか1μm以下であることが望まし
い。The horizontal axis is the TTV value (μm), and the vertical axis is the ratio (%) of the number of occupied wafers to all wafers. %. It goes without saying that the smaller the TTV value, the better, but it is desirable that the TTV value be at least 1 μm or less for most wafers.
本発明はこのような問題点を低減させて、ウェハー厚み
のバラツキを少なくして、厚みを均一化するように研磨
することを目的とした両面研磨方法を提案するものであ
る。The present invention proposes a double-sided polishing method aimed at reducing such problems, reducing variations in wafer thickness, and polishing the wafer to make the thickness uniform.
即ち、例えば、ウェハーのOFラインのために形成され
た切り欠き部にその切り欠き部と同形の薄板を嵌め込ん
で真円孔を埋め、切り欠き部の隙間をなくする。That is, for example, a thin plate having the same shape as the notch is fitted into a notch formed for the OF line of the wafer to fill the circular hole and eliminate the gap between the notches.
そうすれば、ウェハーは上下定盤によって一様に加圧さ
れて、且つ、切り欠き部に研磨粉が溜りにくくなるため
に、平均に研磨されて厚みが均一化される。In this way, the wafer is uniformly pressed by the upper and lower surface plates, and polishing powder is less likely to accumulate in the notch, so that the wafer is polished evenly and has a uniform thickness.
その目的は、切り欠き部を有する円形薄板からなる被加
工物(例えば、半導体ウェハー)をキャリヤに保持して
両面研磨する研磨方法において、被加工物を保持せしめ
るキャリヤの真円孔に該被加工物を嵌め込み、同時に、
真円孔が満たされていない前記切り欠き部に該切り欠き
部と同形の薄板を嵌め込んで両面研磨するようにした研
磨方法によって達成される。The purpose of this polishing method is to polish both sides of a workpiece (for example, a semiconductor wafer) made of a circular thin plate having a notch by holding it on a carrier. Inserting things and at the same time,
This is achieved by a polishing method in which a thin plate having the same shape as the notch is fitted into the notch where the perfect circular hole is not filled, and both sides are polished.
以下、図面を参照して実施例によって詳細に説明する。 Hereinafter, embodiments will be described in detail with reference to the drawings.
第1図は本発明にかかるウェハーを保持したキャリヤの
平面図を示しており、第5図と同一部位に同一記号をつ
けであるが、その他の6はスペーサ(切り欠き部と同形
の薄板)である。このスペーサ6はキャリヤ2と同材質
の例えばエポキシ樹脂から作成し、しかも、キャリヤと
同じ厚みにする。そうすれば、キャリヤの真円孔が埋め
られて隙間がなくなり、キャリヤ全体の加圧も一様にな
り、且つ、研磨粉も蓄積されなくなるために、層均−る
こ研磨することができる。FIG. 1 shows a plan view of a carrier holding a wafer according to the present invention, and the same parts as in FIG. 5 are given the same symbols. It is. This spacer 6 is made of the same material as the carrier 2, for example, epoxy resin, and has the same thickness as the carrier. By doing so, the perfect circular hole in the carrier is filled, there is no gap, the pressure on the entire carrier becomes uniform, and polishing powder is not accumulated, so that uniform layer polishing can be performed.
第2図(a)、 (b)は研磨後のウェハー等厚線図を
示しており、同図(a)は本発明にかかる研磨後のウェ
ハーの等厚線図、同図(b)は従来の研磨後のウェハー
の等厚線図である。図中の線は等厚線で、その等原線間
隔は0.1μmとしであるが、本発明にかかるウェハー
はやや中央が厚くなっている傾向にあるが、従来法によ
って研磨したウェハーのようなOFライン5の部分が厚
みが薄くなったテーパー形状は見られない。FIGS. 2(a) and 2(b) show wafer iso-thickness diagrams after polishing; FIG. 2(a) is an iso-thickness diagram of the wafer after polishing according to the present invention, and FIG. FIG. 3 is an isopic diagram of a wafer after conventional polishing. The lines in the figure are iso-thickness lines, and the iso-line spacing is 0.1 μm.The wafer according to the present invention tends to be slightly thicker in the center, but it is similar to wafers polished by conventional methods. There is no tapered shape in which the thickness of the OF line 5 is reduced.
第3図(a)、 (b)は研磨後のTTV分布図で、同
図(a)は本発明にかかる研磨後の多数ウェハーの分布
図、同図(b)は従来の研磨後の多数ウェハーの分布図
である。横軸はTTV値(μm)2縦軸は全ウェハーに
対する占有ウェハー数の比率(%)であり、従来法によ
る研磨後は平均のTTV値は1.21μm、TTV値が
1μm以下のウェハー比率は42%程度であったが、本
発明にかかる研磨後には平均のT T V 4Mは0.
80 um、 TTV値が1μm以下のウェハー比率は
92%になって、殆どのウェハーのTTV値が1μm以
下という目的がほぼ達成されている1゜なお、使用した
ウェハー試料は6インチφ(口径150mmφ)、厚み
620μmのシリコンウェハーである。3(a) and 3(b) are TTV distribution charts after polishing, where (a) is a distribution diagram of a large number of wafers after polishing according to the present invention, and FIG. 3(b) is a distribution chart of a large number of wafers after conventional polishing. It is a distribution map of wafers. The horizontal axis is the TTV value (μm)2 The vertical axis is the ratio (%) of the number of occupied wafers to all wafers.After polishing using the conventional method, the average TTV value is 1.21μm, and the ratio of wafers with a TTV value of 1μm or less is However, after polishing according to the present invention, the average T T V 4M was about 0.42%.
80 um, the ratio of wafers with a TTV value of 1 μm or less is 92%, and the goal of having most wafers with a TTV value of 1 μm or less has been almost achieved. ), a silicon wafer with a thickness of 620 μm.
上記例は両面をポリッシュ(研磨)する実施例であるが
、ポリッシュによる研磨量は片面で25μm程度と少な
い。一方、その前工程のラッピングによる研磨はその研
磨量が片面で50μm程度と厚く、この両面ラッピング
法にも本発明を適用して一層大きな効果が得られるもの
である。The above example is an example in which both sides are polished, but the polishing amount is as small as about 25 μm on one side. On the other hand, polishing by lapping, which is a pre-process, results in a thick polishing amount of about 50 μm on one side, and even greater effects can be obtained by applying the present invention to this double-sided lapping method.
また、発振子として用いられる石英基板や他の基板(例
えば、ニオブ酸リチウム(LiNb O3) )などの
電子材料基板にも適用できることはいうまでもないこと
である。It goes without saying that the present invention can also be applied to electronic material substrates such as quartz substrates used as oscillators and other substrates (for example, lithium niobate (LiNbO3)).
[発明の効果]
以上の説明から明らかなように、本発明にかかる両面研
磨方法によれば、薄板の厚みを−層均一化する口上がで
きて、半導体デバイスや電子の歩留向上、高品質化に著
しく寄与するものる。[Effects of the Invention] As is clear from the above explanation, according to the double-sided polishing method according to the present invention, it is possible to make the thickness of the thin plate uniform, improving the yield of semiconductor devices and electronics, and improving the quality. There are some things that make a significant contribution to the
第1図は本発明にかかるウェハーを保持したリヤの平面
図、
第2図(a)、■)は研磨後のウェハー等厚線図、第3
図(a)、 (b)は研磨後のTTV分布図、第4図は
ウェハー研磨装置の概要斜視図、第5図は従来のウェハ
ーを保持したキャリヤ面図である。
図において、
1はウェハー(被加工物)、
2はキャリヤ、 3は駆動部、4はギヤ、
5はOFライン、6はスペーサ(切り欠き部
と同形の薄板)を示している。Fig. 1 is a plan view of the rear holding a wafer according to the present invention, Fig. 2(a), (■) is a wafer iso-thickness diagram after polishing, and Fig. 3
Figures (a) and (b) are TTV distribution diagrams after polishing, Figure 4 is a schematic perspective view of a wafer polishing apparatus, and Figure 5 is a plan view of a conventional carrier holding a wafer. In the figure, 1 is a wafer (workpiece), 2 is a carrier, 3 is a drive unit, 4 is a gear,
Reference numeral 5 indicates an OF line, and 6 indicates a spacer (a thin plate having the same shape as the notch).
Claims (2)
キャリヤに保持して両面研磨する研磨方法において、 被加工物を保持せしめるキャリヤの真円孔に該被加工物
を嵌め込み、同時に、真円孔が満たされていない前記切
り欠き部に該切り欠き部と同形の薄板を嵌め込んで両面
研磨するようにしたことを特徴とする薄板の両面研磨方
法。(1) In a polishing method in which a workpiece consisting of a circular thin plate having a notch is held in a carrier and polished on both sides, the workpiece is fitted into a circular hole in the carrier that holds the workpiece, and at the same time A method for polishing both sides of a thin plate, characterized in that a thin plate having the same shape as the notch is fitted into the notch where the circular hole is not filled, and both sides are polished.
徴とする請求項(1)記載の薄板の両面研磨方法。(2) The method for double-sided polishing of a thin plate according to claim (1), wherein the workpiece is a semiconductor wafer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2213325A JPH0494122A (en) | 1990-08-09 | 1990-08-09 | Double side abrasion of thin plate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2213325A JPH0494122A (en) | 1990-08-09 | 1990-08-09 | Double side abrasion of thin plate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0494122A true JPH0494122A (en) | 1992-03-26 |
Family
ID=16637286
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2213325A Pending JPH0494122A (en) | 1990-08-09 | 1990-08-09 | Double side abrasion of thin plate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0494122A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007290078A (en) * | 2006-04-25 | 2007-11-08 | Tosoh Corp | Grinding method of substrate |
WO2019044497A1 (en) * | 2017-08-30 | 2019-03-07 | 株式会社Sumco | Method for producing carrier and method for polishing wafer |
-
1990
- 1990-08-09 JP JP2213325A patent/JPH0494122A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007290078A (en) * | 2006-04-25 | 2007-11-08 | Tosoh Corp | Grinding method of substrate |
WO2019044497A1 (en) * | 2017-08-30 | 2019-03-07 | 株式会社Sumco | Method for producing carrier and method for polishing wafer |
JP2019046851A (en) * | 2017-08-30 | 2019-03-22 | 株式会社Sumco | Carrier manufacturing method and wafer polishing method |
KR20200024272A (en) * | 2017-08-30 | 2020-03-06 | 가부시키가이샤 사무코 | Manufacturing Method of Carrier and Polishing Method of Wafer |
TWI687991B (en) * | 2017-08-30 | 2020-03-11 | 日商Sumco股份有限公司 | Method of manufacturing a carrier and method of polishing a wafer |
US11127584B2 (en) | 2017-08-30 | 2021-09-21 | Sumco Corporation | Method of producing carrier and method of polishing wafer |
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