JPH0490016A - Data processor - Google Patents

Abstract

PURPOSE:To prevent the stop of the whole of a system by supplying a bus clock from the module, to which the highest level is set, out of the other modules at the time when the module to supply the bus clock is faulty to stop the bus clock supply. CONSTITUTION:When the supply of the bus clock from a module 21 set to the highest level is stopped, this stop is detected by the other modules 22 to 2n. When detecting the stop of the bus clock, each of these modules 22 to 2n outputs its own level to a common bus 10 and takes levels outputted from the other modules to the common bus as the input to detect the highest level and compares this detected highest level and the level set to the module itself; and when it is discriminated that the level set to the module itself is highest, a clock oscillating circuit is connected to the common bus 10 to supply the bus clock to the other modules. Thus, the whole of a device is not stopped when the module 21 which supplies the bus clock is faulty.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a data processing device that improves the fault tolerance of a common bus when a plurality of modules are connected by a synchronous common bus synchronized with a bus clock. Regarding.

[Conventional technology]

Figure 10 is U Intel? 1 is a block diagram illustrating the configuration of a conventional data processing device having a synchronous common bus disclosed in "1tl LTIBLIS II Babasu Architecture User's Manual" (published by Intel Japan Co., Ltd.).

In FIG. 10, reference numeral 11 is a clock mask module, and the bus clock signal 115 of the common bus 10 is
A bus clock generation circuit 110 that outputs a bus clock to
has.

Reference numerals 12, 13, . . . In indicate normal modules provided in the data processing device, that is, modules that do not have the bus clock generation circuit 110, respectively.

Note that the common bus 10 is composed of the above-mentioned bus clock signal line 15 and various other signal line groups 16.

In this conventional example, the bus clock is generated by the bus clock generation circuit 110 of the clock master module 11,
It is supplied to all other modules 12, 13, . . . , In via the bus clock signal line 15.

[Problem to be solved by the invention]

In a data processing device with such a conventional configuration, the bus clock is connected to a large number of modules 11 connected to a common bus.
．． 12... Clock master module 11 in In
generated only in each other module 12I3...1n
clock mask module 11.
If the bus clock signal line 15 fails, or if the bus clock signal line 15 is disconnected, the bus clock supply will be completely cut off, causing the l! function stops. Therefore, there is a serious weakness in terms of fault tolerance.

The present invention was made in view of these circumstances, and
To provide a data processing device that can supply a bus clock and has improved fault tolerance performance even when a failure occurs in a module that generates a bus clock or when the bus clock propagation path is cut off. purpose.

[Means to solve the problem]

In the first aspect of the data processing device of the present invention, each module connected to a common bus is assigned a priority as a bus clock supply source in advance, and when the bus clock stops, the data processing device means for detecting, means for outputting its own ranking to the common bus when a stop of the bus clock is detected, and means for inputting the ranking outputted by each module to the common bus to detect the highest ranking. , means for comparing the detected highest ranking with the ranking set for itself, a clock oscillation circuit, and a clock oscillation circuit when it is determined that the ranking set for itself is the highest. A plurality of modules includes a circuit for connecting the circuit to a common bus and supplying the bus clock to other modules.

Further, in the second invention, when the supply of the bus clock is stopped because the common bus is disconnected, the operation is performed in the same manner as described above;
A plurality of modules are provided with means for stopping the supply of the bus clock when the common bus is subsequently connected.

Furthermore, the third invention provides means for comparing the phase of the bus clock on the common bus with the phase of the clock oscillated by the self when the self supplies the bus clock, and a means for comparing the phase of the bus clock on the common bus with the phase of the clock oscillated by the self, Each module is provided with means for stopping the supply of the bus clock when there is a phase difference of .

[Effect]

In the first aspect of the data processing device of the present invention, when a module that supplies bus clocks to a plurality of modules connected to a common bus fails, the topmost module among the other modules Since the module to which the priority is set starts supplying the bus clock immediately, the entire device does not stop.

Further, in the second invention, when the supply of bus clock stops due to disconnection of the common bus or can be done, but
If the common bus is subsequently reconnected, the bus clock supply by the module that later became the bus clock supply source is stopped.

Furthermore, in the third invention, when a situation occurs in which the bus star lofter is supplied from two or more modules at the same time, the module supplying the bus clock outputs the bus clock output on the common bus and the module itself. The state is detected by detecting the phase difference with the clock that is being generated, and the supply of the bus clock is stopped.

(Margins below) [Examples] The present invention will be described in detail below with reference to drawings showing examples thereof.

FIG. 1 is a block diagram showing a configuration example of a first embodiment of a data processing apparatus according to the present invention.

In FIG. 1, reference numbers 21.22.23...2n
are modules, and both have the function of accessing the common bus 10 and the function of supplying a bus clock.

15 is a bus clock signal line, and each module 21,
The bus clock is supplied between 22, 23...20.

A signal line group 16 includes data lines and various other signal lines.

17 is a pasta lock output right request signal line, and a signal requesting the bus clock output right is propagated between each module 21, 22, 23, . . . 2n.

These bus clock signal lines 15. Signal line group 16 bus clotho clock output request signal! 17 etc. constitute a common bus lO. A common bus 10 connects all modules 21.2
Connected to 2.23.24.

FIG. 2 is a block diagram showing a circuit configuration for switching the bus clock supply source provided in each module 21, 22, 23, . . . 2n, ie, a configuration example of the bus clock switching circuit 210.

In FIG. 2, reference numeral 30 denotes a bus clock stop detection circuit, which is composed of a monostable multi-by-break or a counter connected to the bus clock signal line 15. The bus clock stop detection circuit 30 monitors whether the bus clock signal vA15 is supplying the bus clock, detects when the bus clock supply has stopped, and outputs the decode circuit 32 and the clock master signal. Bus clock stop signal S output to generation circuit 36
Make 1 significant.

Reference numeral 31 is a required level setting circuit. Each module 21, 22, 23...2n has a required level of pass crafter output right, that is, each module 21.
22, 23...2n can be a bus clock supply source with different values (for example, mono
122.23...2n in the order of 1st. (2nd... nth rank), and the value is set and held in this request level setting circuit 31 as a ranking holding means. The required level setting value set in the required level setting circuit 31 is output to the decoding circuit 32 and the comparing circuit 35.

Reference numeral 32 is a decoding circuit that decodes a signal representing the required level setting value outputted from the required level setting circuit 31. As a result of the decoding circuit 32 decoding the signal representing the required level setting value, a plurality of output signals WA32a, 32b, 32c, . . . from the decoding circuit 32 are generated.
Only one of 32n becomes significant. Note that the decoding result of this decoding circuit 32 is output to the driver circuit 33 only when the bus clock stop signal S1 given from the bus clock stop detection circuit 30 is significant.

In other words, the decoding circuit 32 functions as a required level output means, that is, a ranking output means.

The driver circuit 33 includes a plurality of drivers 33a, 33b,
33c...33r+, and the corresponding output signal lines 32a, 32b, 3 of the decoding circuit 32
2c...32n respectively open and close them. Specifically, each driver 33a, 3 of the driver circuit 33
3b, 33cm and 33n are output signal lines 32a, 32b, 32 of the decoding circuit 32 to which they are connected, respectively.
Only when cm32n is significant (low level in the configuration example shown in FIG. 2), a low level signal is sent to the corresponding signal W117a, 17b, of the bus clock output right request signal line 17.
Output to 17c -17n.

Reference numeral 34 is a priority encoder, and each signal line 17a17 of the bus clock output right request signal wA17
A pasta lock output right request signal is input from the circuits b, 17c, . . . , 17n, and its value is encoded and output to the comparison circuit 35. In this case, the output signal of the priority encoder 34 is the signal vA32a32b,
The logic of decoding by 32c . . . 32n and encoding by the priority encoder 34 is determined. In other words, the priority encoder 34 is an input means for the required level outputted by other modules;
That is, it functions as a ranking input means.

Reference numeral 35 is a comparison circuit that compares the output of the priority encoder 34 and the output of the above-mentioned required level setting circuit 31, and determines that the set value of the required level set in the required level setting circuit 31 is the output of the priority encoder 34. If it matches, the clock master signal generation circuit 36
makes the output signal S2 significant.

When the signal 52 given from the comparator circuit 35 maintains a significant state for a predetermined period of time, the clock master signal generation circuit 36 determines that its own module has obtained the pass clock output right and makes the output signal S3 significant. do. A clock master signal S3, which is an output signal of the clock master signal generation circuit 36, is provided to a driver 38.

FIG. 3 is a block diagram showing an example of the internal configuration of the clock master signal generation circuit 36.

In FIG. 3, reference numeral 360 is a counter, and reference numeral 361 is a counter.
is a T-flip-flop. The counter 360 counts the internal clock input to the terminal T, and when the counted value reaches a predetermined value, makes the signal input from the terminal Q to the terminal T of the T-flip-flop 361 significant. In addition, the negative logic reset terminal R of the counter 360 is connected to a bus clock stop signal S that becomes high level when the bus clock is stopped.
AND gate 362
is entered via. Therefore, the signal output from the terminal Q of the counter 360 and input to the terminal T of the T-flip-flop 361 is set to a predetermined value only when the bus clock supply stops and the own module acquires the right to supply the bus clock. becomes significant after some time.

The T-flip-flop 361 makes the clock master signal S3, which is the output signal from its output terminal, significant when the signal applied to its own terminal T from the terminal Q of the counter 360 becomes significant as described above. do.

Note that an initial recent signal IR, a bus connection signal S4, which will be described later, and a bus clock abnormality signal S5 are input to a negative logic reset terminal R of the T-flip-flop 361 via a NOR gate 363. These signals [R
, S4 and S5 are all significant at high level, and when they become significant, the clock mask signal S3, which is the output signal from the terminal J of the T-flip-flop 361, is stopped and the bus clock supply from that module is stopped. make it stop.

Reference numeral 37 is an oscillation circuit that oscillates a clock at the same oscillation frequency as the bus clock and outputs it to the driver 38.

The driver 38 outputs the clock signal oscillated by the oscillation circuit 37 to the bus clock signal line 15 only when the output signal S3 of the clock mask signal generation circuit 36 is valid.

Next, the operation of the data processing apparatus of the present invention configured as described above will be explained.

For example, in FIG. 1, it is assumed that the module 21, which has the first bus clock output right setting order, is the bus clock supply source. And this module 2
If some kind of failure occurs in module 22.1, each of the other modules 22.
Assume that the supply of bus clocks to 23...2n is stopped.

When the supply of bus clock from module 21 stops, each module 2223 other than module 21...
- In 2n, each bus clock stop detection circuit 30 detects the stop of bus clock supply after a predetermined period of time and makes the bus clock stop signal S1 significant. As a result, in each of the modules 22, 23, . As a result, each module 22.23...2n
Output signal lines 32a32b, 32 of the decoding circuit 32 of
Only one different one of c...32n becomes significant (low level in the example of FIG. 2), and the corresponding driver 33a (or 33b33c...) of the driver circuit 33 becomes significant.
・32n) becomes significant. As a result, the corresponding bus clock output right request signal lines 17a, 17b17
Since one of c...17n becomes significant, the bus clock output right request signal line 17b corresponds to the request level value preset in each module 22, 23...2n.
.

17c...17n all become significant.

The passcroft output product request signal on the passcroft output right request signal line 17 is input to the priority encoder 34 of each module 22, 23, . . . 2n, and is encoded. The priority encoder 34 of each of the modules 22, 23, . .

The comparison circuit 35 of each module 22, 23...2n compares the level value given from the priority encoder 34 with the level value set in the required level setting circuit 31, and if they match, the clock master The output signal S2 to the signal generation circuit 36 is made significant.

In this case, the output signal S2 of module 22 becomes significant.

In the module 22 where the comparison result in the comparison circuit 35 matches, both the bus clock stop signal S1 outputted from the bus clock stop detection circuit 30 and the output signal S2 outputted from the comparison diagram IR35 become significant, so that the counter 360
After a predetermined time delay, the T-flip-flop 361 maintains its state and makes the clock master signal S3, which is the output signal from its output terminal, significant. As a result, the clock oscillated by the oscillation circuit 37 is outputted to the bus clock signal line 15 via the driver 38.

As a result of the above, the bus clock supply source is automatically switched from the previous module 21 to the module 22 to which the highest required level has been preset among the other modules 22, 23, . . . 2n. The module 22 that has newly become a bus clock supply source continues to function as a bus clock supply source from now on unless a failure occurs internally or the power is cut off.

After this, when the supply of the bus clock from the module 22 is cut off, as a result of the same operation, the next module 23 to which the 111th position is set starts supplying the bus clock.

In the embodiment shown in FIG. 2, the bus clock output right request signal line 17 is set to be significant at a low level, but it is of course possible to employ a configuration in which it is made significant at a high level. Also, one of the signal lines 17a, 17b, 17c-17n of the bus clock output right request signal &1117
The module that drives the book is decoded by the decoding circuit 32 so that there is only one module on the bus, and each driver 33a, 33b, 33c, . . . 3 of the driver circuit 33
Use an oven collector driver for 3n, and use it as a bus clock output request signal! 17 signal lines 17a, 17b,
If 17c...17n are made low level and significant, it is also possible to output the requested level value as it is without decoding it.

When adopting such a configuration, the highest level value among the levels requesting bus clock output is set to each signal line 17a, 17 of the bus clock output right request signal vA17.
b, 17cm and 17n themselves, the priority encoder 34 becomes unnecessary, and the number of bus clock output right request signal lines 17 can also be reduced.

FIG. 4 is a circuit diagram showing the configuration of a main part of a second embodiment of the first aspect of the present invention. This second embodiment employs a circuit configuration in which the passcrotter output increase request signal line 17 can be omitted.

In FIG. 4, reference numeral 45 is a driver that drives the data bus lines of the signal line group 16 of the common bus 10. In FIG.

The data input to this driver 45 is the output of the 2-input NOR gate 81, and the 2-input Not? The outputs of the gates 83 are respectively given.

The bus clock stop signal S1 is applied to one input of the NOR gate 81 via the signal line 4I, and the output of the two-input AND gate 82 is applied to the other input.

An inverted signal of the bus clock stop signal SL is applied to one input of the AND gate 82, and a normal data output signal is applied to the other input via the signal line 42.

One input of the NOR gate 83 is negative logic, and the signal m 32 a of the decoding circuit 32 shown in FIG.
.

A signal that becomes significant when the bus clock output right of one of the modules 32b, 32c, . . . , 32n matches the required level is provided via a signal line 43. Also N
The output of a two-input AND gate 84 is applied to the other input of the 0II gate 83, respectively.

One input of the AND gate 84 receives an inverted signal of the bus clock stop signal S1, and the other input receives an output enable signal that becomes significant when performing a bus access output operation via the output enable signal line 44. It is given.

Reference numeral 46 is the receiver of the data bus line 16 of the common bus 10. The output signal of the receiver 46 is applied to the priority encoder 34 shown in FIG. 2 via a signal line 47, and is also input as a normal data input signal via a signal line 48.

Next, the operation of the second embodiment of the present invention having a circuit configuration as shown in FIG. 4 will be explained.

When the bus clock is normal, a normal data bus output signal is given to the data input of the driver 45 from the signal line 42 via the AND gate 82 and the NOR gate 81, and the output control line of the driver 45 is given the normal data bus output signal. Output enable signal 43 is provided via enable signal 144.

On the other hand, if the bus clock stops, the driver 45
A bus clock stop signal S1 (high level significant) is applied to the data input of the driver 45 via the NOR gate 81, and when the bus clock is stopped, the output signal of the decode circuit 32 in FIG. 2 is applied to the output control line of the driver 45. 43.

data bus line 16 receiver 46 of common bus 10
The output signal of
It is configured to be input to the priority encoder 34 in the figure. Therefore, the data bus signal line 16 of the common bus 10 functions as a normal data communication line when the bus clock is normal, and functions as a request signal line (17) for the bus clock output term when the bus clock is stopped. .

In this way, the request signal line (17) of the bus clock output term
By multiplexing the signals onto the data bus line (16), bus clocking can be performed without increasing the number of signals on the common bus 10.

Automatic switching of multiple supply sources is possible.

Note that here, the request signal line (17
) is multiplexed on the data bus line (16), but the same effect can be achieved even when multiplexed on the address line, control line, etc. of the common bus 10. Furthermore, if the drivers of these signal lines are configured with open collectors, it is also possible to multiplex the required level of the bus clock output term as is, as described above.

Next, a second aspect of the data processing device of the present invention will be explained. In this second invention, the common bus 10 is constituted by cables, etc., and the case where the common bus 10 may be separated due to the addition of modules or an accident is taken into consideration.

FIG. 5 is a block diagram showing a system configuration for explaining in detail the second aspect of the data processing apparatus of the present invention.

In FIG. 5, reference number 2L 22.23...2n
6L 62, 63...6n-1 are modules having the aforementioned bus clock generation circuit 110, and 6L 62, 63...6n-1 are for propagating a common bus signal between adjacent modules, for example, 21, 22, 22, 23, etc. cable.

For example, if the module 21 is the bus clock supply source and a cable breakage accident occurs at point "P" in FIG. module 23 of
. . . 2n, one module (for example, module 23) is automatically switched to function as a bus clock supply source (as in the first invention described above). As a result, 1 .As shown in the fifth jump, modules 21 and 23 become the bus clock supply sources for both module groups "A" and "B", respectively.Then, the cable is connected again at point "P" in FIG. Once connected, modules 21, 22, 23...
- Since the two modules 21 and 23 continue as bus clock sources in 2n(7), two systems of bus clocks are supplied to the entire system.

In view of the need to avoid the occurrence of such problems, a countermeasure can be considered by adopting the configuration of the second invention of the present invention shown in FIG.

In FIG. 6, reference numeral 60 is a bus connection recognition signal line fixed to the ground level at one end of the common bus;
15 is a bus clock signal line of the common bus, and 16 is a signal line of other common buses. The bus connection recognition signal line 60, the bus clock signal line 15, and the common bus 16 are actually connected to each module 2122.23...2n by a cable 61, as shown in FIG. .

Furthermore, each module 21, 22, 23...2n has a bus connection recognition signal vA60 and each bus connection recognition circuit 81, 82.
．． 83...8n, respectively. The order in which the modules 21.22.23...2n are connected to the bus connection recognition signal line 60 is from the ground end of the bus connection recognition signal line 60 to the modules 21.22.23...2n.
- 2n order, and each module 21.2
2.23...The required level of pass clock output authority set in 2n is from the upper side to module 21.22.2.
The order is 3...2n.

Figure 7 shows each bus connection recognition circuit 81, 82, 83...8
FIG. 2 is a circuit diagram showing the configuration of n.

Each bus connection recognition circuit 81.82.83...8n is connected to the bus connection recognition signal line 60 via a backflow prevention diode 91, and each module 21.22.23
. . . It is connected to the 2n side via a receiver 92.

A resistor 9 is connected between the diode 91 and the receiver 92.
A power supply potential Vcc is applied via 3.

Therefore, each bus connection recognition circuit 81, 82, 83...8
If the bus connection recognition signal line 60 is normal (not disconnected), the power supply potential Vcc applied between the diode 91 and the receiver 92 is grounded via the bus connection recognition signal line 60. Therefore, the output signal of the receiver 92 is at a low level. The output signal of this receiver 92 is the bus connection signal S4, which is applied to the reset terminal R of the T-flip and buffer flop 361 of the clock mask signal generation circuit 36 mentioned above.

The operation of the second aspect of the present invention is as follows.

For example, in FIG. 6, assume that the cable 61 is disconnected between the modules 22 and 23 and the bus connection recognition signal line 60 is also disconnected while the module 21 is also the bus clock supply source. In this case modules 21, 22.23
-2n is separated into two groups: a group of modules 21 and 22, and a group of modules 23...2n.

Since the bus connection recognition circuits 81.82 of the modules 21.22 of one group continue to be grounded via the bus connection recognition signal line 6o, the modules 21.
At 22, the bus connection signal s4 of each of the bus connection recognition circuits 81 and 82 remains at a low level, and the module 21 supplies the bus clock in the same manner as before.

Each bus connection recognition circuit 83...8n of the modules 23...2n of the other group is a bus connection recognition signal! 60, the bus connection signal s4 of each bus connection recognition circuit 83...8n becomes high level. In addition, each module 23...2n
Since the bus clock supply to the module 23 is cut off, the module 83 to which the highest bus clock output authority has been set in the group as described above becomes the bus clock supply source to each module 23 in the group. ...Supplies the bus clock to 2n.

By the way, when the cable 61 is once disconnected and then reconnected as described above, the modules 23...2n
In each group, each bus connection recognition circuit 83...
8n is grounded again via the bus connection recognition signal m60, so each bus connection signal S4 returns to low level. As a result, the low level bus connection signal S4 is applied to the reset terminal R of the T flip-flop 361 of the clock master signal generation circuit 36 in each of the modules 23...2n, so that the clock mask signal generation circuit 36 of the module 83 is supplied with the low level bus connection signal S4. The clock master signal S3, which is the output signal, becomes involuntary and stops supplying the bus clock.

By adopting such a configuration, even if a disconnection accident occurs in the middle of the cable and the cable is subsequently restored, there is only one bus clock supply source on the cable 61 (common bus 10), so the first The phenomenon that occurs in the configuration shown in FIG. 5 does not occur, and reliability is improved.

Further, the data processing device of the present invention has a third data processing device as shown in FIG.
It is also possible to adopt the configuration of the invention.

In other words, in the configuration shown in FIG. 8, when a certain module is the clock supply source, the internal clock generated by that module for the bus clock and the bus clock on the common bus are FIG. 2 is a block diagram of an embodiment showing a circuit configuration for monitoring bus clock disturbances at each rising and falling edge of .

In FIG. 8, reference numerals 72 to 75 are flip-flops on J-, and the clock master signal S whose output becomes high level only when serving as a bus clock supply source.
3 is applied to each reset terminal R via a delay circuit 77. Therefore, each J471J tube flop 7
2 to 75 are reset only when the clock master signal S3 is significant.

In addition, the output of flip-flops 72 to 75 for each J- is O
It is input to an R gate 78, and the output of this OR gate 78 is outputted via a signal line 76 as a bus clock abnormality signal S5. Therefore, each J- has a flip-flop 7b 7
If even one of the outputs from 2 to 75 becomes high level, the bus clock abnormal signal S5 becomes significant (high level).

The J input of the flip-flop 72 receives the bus clock from the bus clock signal line 15, and the T input receives the internal clock generated by the oscillation circuit 37 shown in FIG. 2 for the bus clock. Each signal is input from a signal line 71.

A signal obtained by inverting the bus clock is input to the J input of the flip-flop 73, and a signal obtained by inverting the internal clock is input to the T input.

An inverted internal clock signal is inputted to the J input of the flip-flop 74, and an inverted signal of the bus clock signal is inputted to the T input.

An internal clock is input to the J input of the flip-flop 75, and an inverted signal of the bus clock is input to the T input.

Further, the delay circuit 77 connects the flip-flops 72 to 72 to J- until at least each module detects the stop of the bus clock and the switching of the bus clock supply source is completed even if the master signal S3 becomes insignificant. The clock master signal S3 is delayed so that 75 is not reset.

Note that each module receives the aforementioned bus clock abnormal signal S5.
is significant, T of the clock mask signal generation circuit 36 that maintains the state of being the bus clock supply source
- The flip-flop 361 is reset, the bus clock supply is stopped, and the bus clock output right is not requested.

As shown in FIG. 9, the circuit for monitoring disturbances in the bus clock with such a configuration is configured such that, as shown in FIG. − to flip-flop 72~
All outputs of 75 are disabled.

However, as shown in FIG. 9 (bl), for example, if a disturbance occurs in the bus clock and the phase difference becomes larger than a certain level, the output of the flip-flop 74 at J- will become significant at the rising edge "mouth" due to the disturbance in the bus clock. and detects a bus clock abnormality.

As a result, the supply of the bus clock is stopped, and the bus clock supply source is switched between the modules that had only input the bus clock up to that point. In other words, by adopting a configuration using this circuit, the phenomenon of ``two bus clock supply sources on a common bus'' in the configuration shown in Figure 5 will only occur momentarily. , the effect on the entire system is virtually ignored. Therefore, it has the same effect as the configuration using the bus connection recognition signal line 60 described above.

Also, if the request level for passcrofter output authority with the same value is incorrectly set to multiple modules,
The above-mentioned phenomenon of "two bus clock supply sources on a common bus" occurs, but if the configuration shown in Figure 8 is adopted, it becomes possible to detect it as a bus clock disturbance, so it can be minimized. The disturbance can be suppressed.

Finally, although not specifically mentioned in the above description, the bus clock output right request level setting circuit may be configured to be used also as a normal bus access request level setting circuit. Further, FIGS. 4 and 8 both show one configuration example, and other configuration examples may also be adopted.

〔Effect of the invention〕

As described in detail above, in the first aspect of the data processing device of the present invention, even if the module supplying the bus clock fails and the bus clock supply is stopped, the other modules Since the bus clock is supplied from the module whose highest order is set in advance, the entire system will not stop.Also, in the event that the common bus that propagates the bus clock is disconnected, the Since the bus clock is also supplied from the module whose highest rank among the modules that were separated from the module that was supplying the clock is set in advance, the entire system does not stop.

Further, in the second invention, after the common bus is disconnected, one system of bus clock is supplied to each side of the disconnected common bus as described above, and then the common bus is reconnected. At this point, the module that later became the bus clock supply source stops supplying the bus clock, so the problem of two systems of bus clocks continuing to be supplied after the common bus is connected is resolved.

Furthermore, in the third invention, the module supplying the bus clock detects the phase difference between the bus clock on the common bus and the clock generated by itself, and the bus clock is supplied in duplicate. Since the system is configured to detect this, there is no possibility that two systems of bus clocks will be supplied at the same time due to a module failure or incorrect setting of the bus clock supply order.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of a first embodiment of a data processing device according to the present invention, and FIG. 2 is a circuit configuration for switching the bus clock supply source provided in each module. , that is, a block diagram showing an example of the configuration of the bus clock switching circuit, FIG. 3 is a block diagram showing an example of the internal configuration of the clock master signal generation circuit, and FIG. 4 is a block diagram showing an example of the internal configuration of the clock master signal generation circuit. FIG. 5 is a block diagram showing a system configuration for explaining in detail the second invention of the data processing device of the present invention; FIG. 6 is a circuit diagram showing the configuration of the main part of the data processing device of the present invention. FIG. 7 is a block diagram showing a configuration example of an embodiment of the second invention; FIG. 7 is a circuit diagram showing the configuration of each bus connection recognition circuit; FIG. FIG. 9 is a block diagram showing a configuration example of the embodiment, FIG. 9 is a timing chart for explaining the operation of the second invention of the data processing device of the present invention shown in FIG. 8, and FIG. 10 is a diagram of a conventional data processing device. FIG. 2 is a block diagram showing a configuration example. 10: Common bus 15: Bus clock signal line 17: Pass crofter output right request signal vA21, 22°23...
2n: Module 30: Bus clock stop detection circuit 31: Request level setting circuit 32: Decode circuit 33a, 33b, 33c...33n:
Driver 34 Ni priority encoder 35: Comparison circuit 36: Clock master signal generation circuit 37: Oscillator circuit 60: Bus connection recognition signal line 72.73.
7475: Flip-flop to J- 81.82.8
3-8n: Bus connection recognition circuit 210: Bus clock switching circuit 361: T-flip-flop 363
: NOR gate In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (3)

[Claims] (1) In a data processing device in which a plurality of modules are connected to a synchronous common bus that is synchronized with a bus clock, a bus clock monitoring means for monitoring the supply status of the bus clock from the synchronous bus, and a bus clock monitoring means configured in advance for each module are provided. and a ranking holding means for holding the ranking of bus clock supply that is currently being supplied to the bus; A ranking output means that outputs the output to the module, a ranking input means that inputs the ranking output from other modules, and a comparison between the ranking input from the ranking input means and the ranking held in the own ranking holding means. A bus clock switching circuit having a comparison means, a clock oscillation circuit, and a means for outputting a clock oscillated by the oscillation circuit to the common bus when the comparison result by the comparison means matches is included in the plurality of modules. A data processing device comprising at least two of the following. (2) In a data processing device in which a plurality of modules are connected to a synchronous common bus synchronized with a bus clock, a bus clock monitoring means for monitoring the supply status of the bus clock from the synchronous bus, and a bus clock monitoring means configured in advance for each module. and a ranking holding means for holding the ranking of bus clock supply that is currently being supplied to the bus; A ranking output means that outputs the output to the module, a ranking input means that inputs the ranking output from other modules, and a comparison between the ranking input from the ranking input means and the ranking held in the own ranking holding means. a bus clock switching circuit comprising: a comparison means; a clock oscillation circuit; and a means for outputting a clock oscillated by the oscillation circuit to the common bus when the comparison results by the comparison means match; means for inhibiting the operation of the bus clock switching circuit when the bus clock switching circuit is connected; and means for detecting an intermittent state of the common bus and applying the predetermined signal to the bus clock switching circuit when the common bus is connected. A data processing device comprising at least two of the modules. (3) In a data processing device in which a plurality of modules are connected to a synchronous common bus synchronized with a bus clock, a bus clock monitoring means for monitoring the supply status of the bus clock from the synchronous bus, and a bus clock monitoring means configured in advance for each module. and a ranking holding means for holding the ranking of bus clock supply that is currently being supplied to the bus; A ranking output means that outputs the output to the module, a ranking input means that inputs the ranking output from other modules, and a comparison between the ranking input from the ranking input means and the ranking held in the own ranking holding means. a bus clock switching circuit comprising a comparison means, a clock oscillation circuit, and a means for outputting a clock oscillated by the oscillation circuit to the common bus when the comparison result by the comparison means matches; and the bus clock switching circuit. a phase comparison means for comparing the phases of the clock oscillated by the oscillation circuit and the clock input from the common bus when a clock is supplied to the common bus by the phase comparison means; At least two of the plurality of modules are provided with means for stopping output of the clock oscillated by the oscillation circuit to the common bus and inhibiting operation of the bus clock switching circuit when a phase difference is detected. A data processing device comprising: