JP2736474B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a data processing apparatus having improved fault tolerance of a common bus when a plurality of modules are connected by a synchronous common bus synchronized with a bus clock. About.

[Conventional technology]

FIG. 10 is a block diagram showing a configuration of a data processing device having a conventional synchronous common bus disclosed in “Intel MULTIBUSII Bus Architecture Instruction Manual” (issued by Intel Japan Co., Ltd.).

In FIG. 10, reference numeral 11 denotes a clock master module, which has a bus clock generation circuit 110 that outputs a bus clock to a bus clock signal line 15 of the common bus 10.

Reference numerals 12, 13... 1n are ordinary modules provided in the data processing device, that is, a bus clock generation circuit 110.
Are shown, respectively.

The common bus 10 includes the bus clock signal lines 15 described above and various other signal line groups 16.

In this conventional example, the bus clock is generated by the bus clock generation circuit 110 of the clock master module 11, and the bus clock signal line 15 is connected to all other modules 12, 13,.
Is supplied via

[Problems to be solved by the invention]

In such a conventional data processing device, a large number of modules 11, 1 connected to a common bus clock bus are used.
Since only the clock master module 11 of 2... 1n is generated and supplied to the other modules 12, 13,... 1n, the clock master module 11 fails or the bus clock signal line 15 is disconnected. In this case, the supply of the bus clock is completely cut off, and the function of the entire device stops. Therefore, there is a significant weakness in terms of fault tolerance performance.

The present invention has been made in view of such circumstances, and even when a failure occurs in a module generating a bus clock or when a propagation path of the bus clock is cut off, the bus clock is not transmitted. An object of the present invention is to provide a data processing device capable of supplying data and having improved fault-tolerant performance.

[Means for solving the problem]

In the first aspect of the present invention, the data processing device of the present invention assigns in advance the order in which each of the modules connected to the common bus is to be the supply source of the bus clock, and when the bus clock is stopped, it gives the order. Means for detecting, a means for outputting its own rank to the common bus when the stop of the bus clock is detected, and a means for inputting the rank of each module outputting to the common bus and detecting the highest rank. Means for comparing the detected highest rank with the rank set for itself, a clock oscillation circuit, and clock oscillation when the rank set for itself is determined to be the highest rank. A circuit for connecting a circuit to a common bus and supplying the same to other modules as a bus clock is provided in a plurality of modules.

Further, in the second invention, when the supply of the bus clock is stopped because the common bus is disconnected, the same operation as described above is performed, and thereafter, when the common bus is connected, a plurality of means for stopping the supply of the bus clock are provided. Of the module.

Further, in the third aspect, when the bus itself is supplying a bus clock, a means for comparing the phase of the bus clock on the common bus with the phase of the clock oscillating by itself, and a means having a predetermined width or more between the two. Each module is provided with means for stopping the supply of the bus clock when there is a phase difference.

[Action]

According to the first aspect of the data processing device of the present invention, when a module that supplies a bus clock to a plurality of modules connected to a common bus fails,
Since the module with the highest rank among other modules starts supplying the bus clock immediately,
The entire device does not stop.

Further, in the second invention, when the supply of the bus clock is stopped due to the disconnection of the common bus, a module that newly supplies the bus clock can be provided in a module group separated from the module that has supplied the bus clock so far. But,
Thereafter, when the common bus is reconnected, the supply of the bus clock by the module serving as the supply source of the bus clock is stopped later.

Further, in the third invention, when a situation occurs in which the supply of the bus clock is simultaneously performed from two or more modules, the module supplying the bus clock is connected to the bus clock output on the common bus. The state is detected by detecting the phase difference from the clock generated by itself, and the supply of the bus clock is stopped.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings showing the embodiments.

FIG. 1 is a block diagram showing a configuration example of an embodiment of the first invention of the data processing apparatus according to the present invention.

In FIG. 1, reference numerals 21, 22, 23... 2n are modules, each of which has a function of accessing the common bus 10 and a function of supplying a bus clock.

Reference numeral 15 denotes a bus clock signal line, and each of the modules 21, 22,
Bus clock is supplied between 23 ... 2n.

A signal line group 16 includes data lines and other various signal lines.

Reference numeral 17 denotes a bus clock output right request signal line through which a signal requesting the bus clock output right is propagated among the modules 21, 22, 23,.

The common bus 10 is constituted by the bus clock signal line 15, the signal line group 16, the bus clock output right request signal line 17, and the like. The common bus 10 is connected to all the modules 21, 22, 23, 24.

FIG. 2 is a block diagram showing a circuit configuration for switching the supply source of the bus clock provided in each of the modules 21, 22, 23... 2n, that is, a configuration example of the bus clock switching circuit 210.

In FIG. 2, reference numeral 30 denotes a bus clock stop detection circuit, which comprises a monostable multivibrator or a counter connected to the bus clock signal line 15. The bus clock stop detection circuit 30 monitors whether or not the bus clock signal line 15 is supplying the bus clock, detects when the supply of the bus clock is stopped, and detects the bus Signal generation circuit
The bus clock stop signal S1 output to 36 is made significant.

Reference numeral 31 is a required level setting circuit. Each of the modules 21, 22, 23... 2n has a different required level of the bus clock output right, that is, a different order in which the respective modules 21, 22, 23. 22, 23... 2n in the order of first, second,... N), and the values are set and held in the required level setting circuit 31 as rank holding means. The request level set value set in the request level setting circuit 31 is output to the decode circuit 32 and the comparison circuit 35.

Reference numeral 32 denotes a decoding circuit, which decodes a signal indicating the required level setting value output from the required level setting circuit 31. As a result of the decoding circuit 32 decoding the signal representing the required level setting value, only one of the plurality of output signal lines 32a, 32b, 32c... 32n of the decoding circuit 32 becomes significant. The decoding result of the decoding circuit 32 is output to the driver circuit 33 only when the bus clock stop signal S1 provided from the bus clock stop detection circuit 30 is significant. In other words, the decoding circuit 32 functions as output means of a required level, that is, order output means.

The driver circuit 33 is composed of a plurality of drivers 33a, 33b, 33c... 33n, and the respective output signal lines 32a, 32b, 32c.
Specifically, each driver 33a, 33b, 33c of the driver circuit 33
.. 33n are bus clock output rights only when the output signal lines 32a, 32b, 32c... 32n of the decoding circuit 32 to which they are connected are significant (low level in the configuration example of FIG. 2). The corresponding signal lines 17a, 17b, of the request signal line 17,
Output to 17c ... 17n.

Reference numeral 34 denotes a priority encoder, and each signal line 17a, 17b, 17c ... 1 of the bus clock output right request signal line 17
The bus clock output right request signal is input from 7n, the value is encoded, and the encoded value is output to the comparison circuit 35. In this case, the logic of the decoding by the signal lines 32a, 32b, 32c... 32n and the logic of the encoding by the priority encoder 34 are determined so that the output signal of the priority encoder 34 becomes the highest required level value requesting the bus clock output right. Have been. In other words, the priority encoder 34 is an input means of the required level output by another module,
That is, it functions as order input means.

Reference numeral 35 denotes a comparison circuit which compares the output of the priority encoder 34 with the output of the above-described request level setting circuit 31 and outputs the setting value of the request level set in the request level setting circuit 31 to the output of the priority encoder 34. If the value matches, the output signal S2 to the clock master signal generation circuit 36 is made significant.

When the signal S2 provided from the comparison circuit 35 maintains a significant state for a predetermined period of time, the clock master signal generation circuit 36 determines that the own module has obtained the right to output the bus clock, and determines that the output signal S3 is significant. To A clock master signal which is an output signal of the clock master signal generation circuit 36
S3 is provided to the driver 38.

FIG. 3 is a block diagram showing an example of the internal configuration of the clock master signal generation circuit 36.

In FIG. 3, reference numeral 360 denotes a counter, and reference numeral 361 denotes T
-A flip-flop. The counter 360 counts the internal clock input to the terminal T, and when the count reaches a predetermined value, makes the signal input from the terminal Q to the terminal T of the T-flip-flop 361 significant. Also counter 36
The AND gate 362 is connected to the reset terminal R having a negative logic of 0 by a bus clock stop signal S1 which becomes high when the bus clock is stopped and an output signal S2 which becomes high when the own module obtains the right to output the bus clock. Have been entered through. Therefore, the output from the terminal Q of the counter 360 is
The signal input to the terminal T of the flip-flop 361 becomes significant after a predetermined time only when the supply of the bus clock is stopped and the own module acquires the right to supply the bus clock.

When the signal supplied from the terminal Q of the counter 360 becomes significant at its own terminal T as described above, the T-flip-flop 361 significantly changes the clock master signal S3, which is the output signal from its output terminal. I do.

Note that an initial reset signal IR, a bus connection restoration signal S4 described later, and a bus clock abnormality signal S5 are input to a negative logic reset terminal R of the T-flip-flop 361 via a NOR gate 363. These signals IR, S4 and S5
Are significant at the high level, and when they become significant, the clock master signal S3, which is the output signal from the terminal 0 of the T-flip-flop 361, is stopped to stop the supply of the bus clock from the module.

Reference numeral 37 denotes an oscillation circuit that oscillates a clock at the same oscillation frequency as the bus clock and outputs the clock to the driver 38.

The driver 38 outputs the clock signal oscillated by the oscillation circuit 37 to the bus clock signal line 15 only when the output signal S3 of the clock master signal generation circuit 36 is significant.

Next, the operation of the data processing device of the present invention configured as described above will be described.

For example, in FIG. 1, it is assumed that the module 21 in which the setting order of the bus clock output right is the first is the supply source of the bus clock. And this module 21
Some other failure occurs in other modules 22, 23… 2
It is assumed that the supply of the bus clock to n is stopped.

When the supply of the bus clock from the module 21 is stopped, in each of the other modules 22, 23... 2n other than the module 21, the respective bus clock stop detection circuits 30 detect the stop of the bus clock supply after a predetermined time has elapsed. The bus clock stop signal S1 is made significant. Thus, in each of the modules 22, 23... 2n, the respective required level setting circuits 3
The signal of the required level value preset to 1 is decoded by each decoding circuit 32. As a result, the output signal lines 32a, 32b, 3 of the decode circuit 32 of each of the modules 22, 23,.
31n, only one of them is significant (low level in the example of FIG. 2), and the corresponding driver 33a (or 33b, 33c... 32n) of the driver circuit 33 is significant. As a result, one of the corresponding bus clock output right request signal lines 17a, 17b, 17c... 17n becomes significant, and thus corresponds to the request level value preset in each of the modules 22, 23. Bus clock output right request signal line 17
b, 17c ... 17n are all significant.

The bus clock output right request signal on the bus clock output right request signal line 17 is input to the priority encoder 34 of each of the modules 22, 23,. Priority encoder 34 for each module 22, 23… 2n
Outputs the highest level (in this case, the second highest level) of the levels at which the bus clock output is requested to the comparison circuit 35.

The comparison circuit 35 of each of the modules 22, 23,... 2n compares the level value given from the priority encoder 34 with the level value set in the required level setting circuit 31, and generates a clock master signal if they match. The output signal S2 to the circuit 36 is made significant. In this case, the output signal S2 of the module 22 becomes significant.

In the module 22 in which the comparison result in the comparison circuit 35 matches, the bus clock stop signal S1 output from the bus clock stop detection circuit 30 and the output signal S2 output from the comparison circuit 35 are both significant. After a predetermined time delay, the T-flip-flop 361 holds the state and makes the clock master signal S3, which is an output signal from its output terminal, significant. As a result, the oscillation circuit 37
The clock oscillating is output to the bus clock signal line 15 via the driver 38.

As described above, the supply source of the bus clock is automatically switched from the previous module 21 to the module 22 in which the highest required level among the other modules 22, 23... 2n is set in advance. The module 22 that has newly become the bus clock supply source will continue to function as the bus clock supply source unless a failure occurs in the module 22 or the power supply is cut off.

Thereafter, when the supply of the bus clock from the module 22 is interrupted, as a result of the same operation, the module 23 to which the next order is set supplies the bus clock.

Although the bus clock output right request signal line 17 has a low level significance in the embodiment shown in FIG. 2 as described above, it is of course possible to adopt a configuration having a high level significance. Each signal line of the bus clock output request signal line 17
The modules that drive one of 17a, 17b, 17c... 17n are decoded by the decoding circuit 32 so that there is only one module on the bus, but each of the drivers 33a, 33b, 33 of the driver circuit 33
Use an open-collector driver for c ... 33n, and use the bus clock output right request signal lines 17 as signal lines 17a, 17b, 17c ... 17n
Can be output as it is without decoding the required level value.

In such a configuration, the highest level value among the levels requesting the output of the bus clock is set to the signal lines 17a, 17b, 17c... 17n of the bus clock output right request signal line 17.
Since it indicates itself, the priority encoder 34 becomes unnecessary, and the number of bus clock output right request signal lines 17 can be reduced.

FIG. 4 is a circuit diagram showing a configuration of a main part of a second embodiment of the first invention of the present invention. In the second embodiment, a circuit configuration in which the bus clock output right request signal line 17 can be omitted is adopted.

In FIG. 4, reference numeral 45 denotes a signal line group of the common bus 10.
It is a driver that drives 16 data bus lines. The data input to the driver 45 is given by the output of a two-input NOR gate 81, and the output control input is given by the output of a two-input NOR gate 83.

One input of the NOR gate 81 has a bus clock stop signal S
1 is provided via a signal line 41, and the other input is provided with the output of a two-input AND gate 82, respectively.

One input of the AND gate 82 has a bus clock stop signal S
One inverted signal is supplied to the other input via a signal line 42, and a normal data output signal is supplied to the other input.

One input of the NOR gate 83 is negative logic, and the signal lines 32a, 32b, 32c... 32n of the decode circuit 32 shown in FIG.
The signal which becomes significant when the bus clock output right of the own module coincides with the required level is provided via the signal line 43. The other input of the NOR gate 83 is given the output of the two-input AND gate 84, respectively.

One input of the AND gate 84 has a bus clock stop signal S
An inverted signal of 1 and an output enable signal which becomes significant when the output operation of the bus access is performed are applied to the other input via the output enable signal line 44, respectively.

Reference numeral 46 denotes a receiver of the data bus line 16 of the common bus 10. The output signal of the receiver 46 is supplied to the priority encoder 34 shown in FIG. 2 through a signal line 47, and is also input as a normal data input signal through a signal line 48.

Next, the operation of the second embodiment of the present invention having a circuit configuration as shown in FIG. 4 will be described.

When the bus clock is normal, a normal data bus output signal is applied to the data input of the driver 45 from the signal line 42.
The output control signal of the driver 45 is supplied to the output control signal of the driver 45 via the output enable signal line 44.

On the other hand, when the bus clock stops, the driver 45
A bus clock stop signal S1 (significant high level) is applied to the data input via the NOR gate 81, and the output control line of the driver 45 receives the output signal of the decode circuit 32 in FIG. Given through 43.

The output signal of the receiver 46 of the data bus line 16 of the common bus 10 is input as a normal data input signal via a signal line 48, and is also input to the priority encoder 34 in FIG. It is configured to: Therefore, the data bus signal line 16 of the common bus 10 functions as a normal data communication line when the bus clock is normal, and functions as a bus clock output right request signal line (17) when the bus clock is stopped. .

Thus, the bus clock output right request signal line (17)
Is multiplexed on the data bus line (16), it is possible to automatically switch the supply source of the bus clock without increasing the number of signals on the common bus 10.

Here, the bus clock output right request signal line (1
Although the configuration in which 7) is multiplexed on the data bus line (16) has been described, the same effect can be obtained by multiplexing it on the address line, control line, etc. of the common bus 10. If the driver of these signal lines is constituted by an open collector, the required level of the bus clock output right can be multiplexed as it is as described above.

Next, a second invention of the data processing device of the present invention will be described. In the second invention, the common bus 10 is configured by a cable or the like, and consideration is given to a case where the common bus 10 may be disconnected due to the addition of a module or an accident.

FIG. 5 is a block diagram showing a system configuration for explaining the necessity of the second invention of the data processing device of the present invention.

In FIG. 5, reference numerals 21, 22, 23,... 2n denote modules having the above-described bus clock generation circuit 110, 61, 62, 6
3 ... 6n-1 are adjacent modules, for example, 21
And 22, 22, 22 and 23 for transmitting a common bus signal.

Now, for example, if the module 21 is a bus clock supply source and a cable disconnection accident occurs at the point "P" in FIG. One module (for example, the module 23) in the module group composed of the modules 23...
Automatically switch to function as a bus clock source. As a result, as shown in FIG. 5, "A" and "B"
In both of the two module groups, the modules 21 and 23 are bus clock supply sources. Then, the fifth
When the cable is connected again at point "P" in the figure, two modules 21 and 23 among the modules 21, 22, 23... The system bus clock is supplied.

From the need to avoid the occurrence of such problems, the sixth
A countermeasure by adopting the configuration of the second invention of the present invention shown in the figure can be considered.

In FIG. 6, reference numeral 60 denotes a bus connection recognition signal line fixed to the ground level at one end of the common bus,
Reference numeral 15 denotes a bus clock signal line of the common bus, and reference numeral 16 denotes a signal line of another common bus. Then, the bus connection recognition signal line 60,
The bus clock signal line 15 and the common bus 16 are actually connected to each module 21 and 2 by a cable 61 as shown in FIG.
2,23 ... 2n.

Further, the modules 21, 22, 23... 2n are connected to the bus connection recognition signal lines 60 via the bus connection recognition circuits 81, 82, 83. The connection order of the modules 21, 22, 23... 2n to the bus connection recognition signal line 60 is from the ground end side of the bus connection recognition signal line 60 to the modules 21, 22, 23. The request levels of the bus clock output right set in the modules 21, 22, 23,... 2n are in the order of the modules 21, 22, 23,.

FIG. 7 is a circuit diagram showing the configuration of each bus connection recognition circuit 81, 82, 83... 8n.

Each of the bus connection recognition circuits 81, 82, 83,... 8n is connected to the bus connection recognition signal line 60 via a diode 91 for preventing backflow, and each of the modules 21, 22, 23,. Connected. And the diode 91 and the receiver 92
And the power supply potential Vcc is applied via a resistor 93.

Therefore, each bus connection recognizing circuit 81, 82, 83... 8n supplies the power supply potential Vcc applied between the diode 91 and the receiver 92 if the bus connection recognizing signal line 60 is normal (not disconnected). Is grounded via the bus connection recognition signal line 60, the output signal of the receiver 92 is at a low level. The output signal of the receiver 92 is the bus connection signal S4, which is provided to the reset terminal R of the T-flip-flop 361 of the clock master signal generation circuit 36 described above.

The operation of the second aspect of the present invention is as follows.

For example, in FIG. 6, it is assumed that the cable 61 is disconnected between the modules 22 and 23 and the bus connection recognition signal line 60 is also disconnected while the module 21 is also a supply source of the bus clock. In this case, the modules 21, 22, 23... 2n are separated into two groups: a group of modules 21 and 22 and a group of modules 23.

Since the bus connection recognizing circuits 81 and 82 of the modules 21 and 22 of one group continue to be grounded via the bus connection recognizing signal line 60, the modules 21 and 22 have respective bus connection recognizing circuits 81 and 82. , 82, the bus connection restoration signal S4 remains at the low level, and the module 21
Supplies the bus clock.

Since the bus connection recognition circuits 83 ... 8n of the modules 23 ... 2n of the other group are disconnected from the ground via the bus connection recognition signal line 60, the bus connection signals S4 of the respective bus connection recognition circuits 83 ... 8n High level. In addition, since the supply of the bus clock to each of the modules 23... 2n is cut off, the module 83 to which the highest bus clock output right is set in the group as described above becomes the bus clock supply source. 2n in the group to supply a bus clock.

By the way, when the cable 61 is once disconnected and then reconnected, the bus connection recognition circuits 83... 8n are grounded again via the bus connection recognition signal line 60 in the group of the modules 23. Therefore, each bus connection signal S4 returns to a low level. As a result, in each of the modules 23... 2n, the low-level bus connection signal S4 is supplied to the reset terminal R of the T-flip-flop 361 of the clock master signal generation circuit 36, so that the output of the clock master signal generation circuit 36 of the module 83 is output. The clock master signal S3, which is a signal, becomes insignificant and stops supplying the bus clock.

By adopting such a configuration, even when a disconnection accident occurs in the middle of the cable and the cable is restored afterwards, only one bus clock supply source is provided on the cable 61 (the common bus 10). The phenomenon that occurs in the configuration shown in FIG. 5 does not occur, and the reliability is improved.

Further, the data processing device of the present invention can adopt the configuration of the third invention as shown in FIG. That is, in the configuration shown in FIG. 8, when a certain module is a clock supply source, each of the internal clock generated by the module for the bus clock and the bus clock on the common bus is used. FIG. 4 is a block diagram of an embodiment showing a circuit configuration for monitoring a disturbance of a bus clock at rising and falling edges.

In FIG. 8, reference numerals 72 to 75 denote JK flip-flops, each of which outputs a clock master signal S3 having a high level only when it is a bus clock supply source via a delay circuit 77. It is provided to a reset terminal R. Therefore, the reset of each JK flip-flop 72-75 is released only when the clock master signal S3 is significant.

The outputs of the JK flip-flops 72 to 75 are input to an OR gate 78, and the output of the OR gate 78 is output via a signal line 76 as a bus clock abnormal signal S5. Therefore, if the output of any one of the JK flip-flops 72 to 75 becomes high level, the bus clock abnormality signal S5 becomes significant (high level).

The J input of the JK flip-flop 72 receives a bus clock from the bus clock signal line 15, and the T input receives an internal clock generated by the oscillation circuit 37 shown in FIG. 2 for the bus clock. Each is input from the signal line 71.

The inverted signal of the bus clock is input to the J input of the JK flip-flop 73, and the inverted signal of the internal clock is input to the T input.

An inverted signal of the internal clock is input to the J input of the JK flip-flop 74, and an inverted signal of the bus clock signal is input to the T input.

The internal clock is input to the J input of the JK flip-flop 75, and the inverted signal of the bus clock is input to the T input.

Further, even if the clock master signal S3 becomes insignificant, the delay circuit 77 detects at least the stop of the bus clock by each module and until the switching of the bus clock supply source is completed, the JK flip-flops 72 to 75. Is delayed so that the clock master signal S3 is not reset.

Each module is connected to the bus clock abnormal signal S5 described above.
Is significant, T- of the clock master signal generation circuit 36, which holds the state of supplying the bus clock,
The configuration is such that the flip-flop 361 is reset, the supply of the bus clock is stopped, and the request for the bus clock output right is not made.

As shown in FIG. 9 (a), the circuit for monitoring the disturbance of the bus clock having such a configuration operates while the bus clock is input to the module with a certain delay time t1, t2 with respect to the internal clock. , JK flip-flops 72 to 75 are all insignificant.

However, as shown in FIG. 9 (b), if the bus clock is disturbed and the phase difference becomes larger than a certain level, the output of the JK flip-flop 74 becomes significant at the rising edge "Q" due to the disturbance of the bus clock. become,
Detects bus clock abnormality. As a result, the supply of the bus clock is stopped, and the switching of the bus clock supply source is performed between the modules that only input the bus clock up to that point. That is, by adopting the configuration using this circuit, the phenomenon of "two bus clock supply sources on the common bus" in the configuration shown in FIG. 5 occurs only instantaneously. The effect on the entire system is virtually ignored. Therefore, the same effect as the configuration using the bus connection recognition signal line 60 described above is obtained.

Further, even when the request level of the bus clock output right having the same value is erroneously set in a plurality of modules, the above-described phenomenon that “two bus clock supply sources are provided on a common bus” occurs. If the configuration shown in FIG. 8 is adopted, it is possible to detect as a disturbance of the bus clock, so that the disturbance can be suppressed to the minimum.

Finally, although not particularly described in the above description, a configuration in which the request level setting circuit for the bus clock output right is also used as a normal bus access request level setting circuit can be adopted. 4 and 8 show one configuration example, and other configuration examples can be adopted.

〔The invention's effect〕

As described in detail above, in the data processing device of the present invention,
In the first invention, even when a module supplying the bus clock fails and the supply of the bus clock is stopped, the bus clock is supplied from the module of the highest rank set in advance among other modules. Therefore, the whole system does not stop. In the case where the common bus that propagates the bus clock is disconnected, the bus clock is also changed from the module that is previously set to the highest order among the modules that have been separated from the module that supplied the clock. Is supplied, so that the whole system does not stop.

Further, in the second aspect, after the common bus is disconnected, each side of the disconnected common bus is supplied with the bus clock of one system, and thereafter the common bus is reconnected. At this point, the module that has become the bus clock supply source later stops supplying the bus clock, so that the problem of continuing to supply two bus clocks after the common bus is connected is resolved.

Furthermore, in the third aspect, the module supplying the bus clock detects the phase difference between the bus clock on the common bus and the clock generated by itself, and supplies the bus clock twice. Is detected, the possibility that two bus clocks are simultaneously supplied due to a failure of the module or an erroneous setting of the bus clock supply order is eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of an embodiment of the first invention of a data processing apparatus according to the present invention. FIG. 2 is a circuit configuration for switching a supply source of a bus clock provided in each module. That is, a block diagram showing a configuration example of a bus clock switching circuit, FIG. 3 is a block diagram showing an internal configuration example of a clock master signal generation circuit, and FIG. 4 is a block diagram showing a second embodiment of the first invention of the present invention. FIG. 5 is a circuit diagram showing the configuration of a main part, FIG. 5 is a block diagram showing a system configuration for explaining the necessity of the second invention of the data processing device of the present invention, and FIG. 6 is a data processing device according to the present invention. FIG. 7 is a block diagram showing a configuration example of an embodiment of the second invention, FIG. 7 is a circuit diagram showing a configuration of each bus connection recognition circuit, and FIG. 8 is a data processing device according to the second invention of the present invention. FIG. 9 is a block diagram showing a configuration example of one embodiment. 8 timing chart for explaining the operation of the second invention of the data processing apparatus of the present invention shown in FIG., FIG. 10 is a block diagram showing an example of the configuration of a conventional data processing apparatus. 10: common bus, 15: bus clock signal line, 17: bus clock output right request signal line, 21, 22, 23 ... 2n: module, 30: bus clock stop detection circuit, 31: request level setting circuit, 32:
33a, 33b, 33c ... 33n: driver, 34: priority encoder, 35: comparison circuit, 36: clock master signal generation circuit, 37: oscillation circuit, 60: bus connection recognition signal line,
72, 73, 74, 75: JK flip-flop, 81, 82, 83 ... 8n: bus connection recognition circuit, 210: bus clock switching circuit, 361: T
-Flip-flop, 363: NOR gate In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (3)

(57) [Claims] 1. A data processing device in which a plurality of modules are connected to a synchronous common bus synchronized with a bus clock, wherein a bus clock monitoring means for monitoring a supply state of a bus clock from the synchronous bus is provided. Order holding means for holding the set order of the bus clock supply, and the order held by the order holding means when the bus clock monitoring means detects that the supply of the bus clock is stopped. Order output means for outputting the order output from the other module, order input means for inputting the order output from another module, and the order input from the order input means and the order held by the own order holding means. A comparison means for comparing, a clock oscillation circuit, and a clock oscillated by the oscillation circuit when the comparison result by the comparison means matches. A data processing device comprising: a bus clock switching circuit having means for outputting to a common bus, at least two of the plurality of modules. 2. A data processing apparatus in which a plurality of modules are connected to a synchronous common bus synchronized with a bus clock, wherein: a bus clock monitoring means for monitoring a supply state of a bus clock from the synchronous bus; Order holding means for holding the set order of the bus clock supply, and the order held by the order holding means when the bus clock monitoring means detects that the supply of the bus clock is stopped. Order output means for outputting the order output from the other module, order input means for inputting the order output from another module, and the order input from the order input means and the order held by the own order holding means. A comparison means for comparing, a clock oscillation circuit, and a clock oscillated by the oscillation circuit when the comparison result by the comparison means matches. A bus clock switching circuit having means for outputting to the common bus; means for stopping output of a clock oscillated by the oscillation circuit to the common bus when a predetermined signal is supplied; Means for detecting a state and providing the predetermined signal to the bus clock switching circuit when the connection is restored, in at least two of the plurality of modules. 3. A data processing device in which a plurality of modules are connected to a synchronous common bus synchronized with a bus clock, wherein a bus clock monitoring means for monitoring a supply state of a bus clock from the synchronous bus is provided. Order holding means for holding the set order of the bus clock supply, and the order held by the order holding means when the bus clock monitoring means detects that the supply of the bus clock is stopped. Order output means for outputting the order output from the other module, order input means for inputting the order output from another module, and the order input from the order input means and the order held by the own order holding means. A comparison means for comparing, a clock oscillation circuit, and a clock oscillated by the oscillation circuit when the comparison result by the comparison means matches. A bus clock switching circuit having means for outputting to the common bus; and a clock oscillated by the oscillation circuit and input from the common bus when a clock is supplied to the common bus by the bus clock switching circuit. Phase comparing means for comparing the phase with a clock; and when the phase comparing means detects a phase difference of a predetermined width or more, the output of the clock oscillated by the oscillation circuit to the common bus is stopped and the bus is stopped. Means for inhibiting operation of the clock switching circuit, at least two of the plurality of modules are provided.