JP2014236478A - Clock signal supply system and standby clock signal output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a highly reliable communication system by multiplexing a clock signal supply source.SOLUTION: A communication system includes: a master node 1 having a main clock generator 10; and a plurality of sub-nodes 2 each having a standby clock generator 20. The master node 1 supplies a clock signal for synchronously operating a plurality of nodes, connected to a communication bus 3, to the communication bus. Each sub-node 2 monitors the presence of absence of a clock signal propagating on the communication bus 3, and supplies a clock signal generated by a clock oscillator 24 to the communication bus 3, on condition that a predetermined reference time elapses in a state that the clock signal on the communication bus 3 breaks.

Description

  The present invention relates to a clock signal supply system that outputs a clock signal for operating a plurality of nodes in synchronization to a communication bus.

  Conventionally, in a communication system using a communication bus, when a clock signal is not transmitted due to a failure of a clock generator (master node) that generates a clock signal for synchronizing a plurality of nodes, a spare clock generator (sub A technique in which a master node) supplies a clock signal on behalf is known (see Patent Document 1). By doing so, it is said that high reliability of the communication system can be realized.

JP2013-30932A

  In the communication system described in Patent Document 1, there is only one sub-master node that can output a clock signal as a proxy for the master node. That is, even if the master node and the sub master node are combined, the supply source of the clock signal can only be duplicated. Therefore, there is room for further improvement in realizing higher reliability.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a technique for realizing higher reliability of a communication system by multiplexing clock signal supply sources.

  A clock signal supply system according to the present invention includes a main clock signal output device that outputs a predetermined clock signal for synchronously operating a plurality of nodes connected to a communication bus to the communication bus, and a plurality of spare clock signal output devices. With. The spare clock signal output device includes a generating unit that generates a clock signal and a control unit. The control means monitors the presence or absence of a clock signal propagating on the communication bus, and determines the clock signal generated by the generation means on the condition that a predetermined reference time has passed with the clock signal on the communication bus being interrupted. Output to the communication bus.

  The clock signal supply system of the present invention includes a plurality of spare clock signal output devices that can be used as spares for the main clock signal output device. The plurality of spare clock signal output devices each monitor the presence or absence of a clock signal propagating on the bus, and output the clock signal to the communication bus when it is determined that the state in which the clock signal has been interrupted has continued for a certain period of time. It is like that. According to such a configuration, not only the main clock signal output device but also the remaining normal spare clock signal output devices even under the situation where the clock signal cannot be output from some spare clock signal output devices. Can output a clock signal. Further reliability of the communication system can be realized by multiplexing clock signal supply sources in the present invention.

1 is a block diagram showing a schematic configuration of a communication system. Explanatory drawing which shows an example of the supply condition of the clock signal in a communication system. The flowchart which shows the procedure of a clock supply start process. The flowchart which shows the procedure of a clock duplication avoidance process.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In addition, this invention is not limited to the following embodiment, It is possible to implement in various aspects.
[Description of configuration of communication system]
The communication system according to the embodiment is mounted on a vehicle. As shown in FIG. 1, the master node 1 and a plurality (1, 2,... N) of sub-nodes 2 are communication paths of the in-vehicle communication network. It is connected to the communication bus 3. The communication bus 3 is connected with a plurality of electronic control devices (ECU, not shown) that control devices provided in the vehicle as communication devices.

  The master node 1 is provided with a main clock generator 10 which is an electronic control device that supplies a clock signal having a predetermined frequency to the communication bus. The clock signal is a reference signal for synchronizing the operations of various ECUs connected to the communication bus 3. The main clock generator 10 outputs a clock signal having a predetermined frequency generated by the clock oscillator 11 to the communication bus. The clock oscillator 11 is a transmission circuit using a vibrator that emits at a stable frequency, such as a crystal vibrator.

  The sub node 2 is provided with a spare clock generator 20 that supplies a clock signal similar to that of the master node 1 to the communication bus as a spare when the clock signal is not supplied to the communication bus due to a failure of the master node 1 or the like. In the following description, when a plurality of subnodes 2 are individually distinguished, numbers such as subnode (1), subnode (2). Note that the master node 1 and the sub node 2 may be provided as dedicated devices for supplying a clock signal, or may be incorporated in a plurality of ECUs that control devices provided in the vehicle. May be.

  The spare clock generation unit 20 includes a control unit 21 and a clock oscillator 24. The control unit 21 is an electronic circuit mainly composed of a microcomputer, for example, and performs various controls related to the supply of a clock signal. The control unit 21 includes a time determination unit 22 that determines the elapsed time and a clock detection unit 23 that detects the presence or absence of a clock signal propagating through the communication bus 3 as functional configurations realized by software or hardware. The clock oscillator 24 is a transmission circuit using a vibrator that emits at a stable frequency, such as a crystal vibrator, and generates a clock signal equivalent to the clock oscillator 11 included in the main clock generator 10.

  The control unit 21 monitors whether or not a clock signal is supplied to the communication bus 3 by the clock detection unit 23. In a normal state, a clock signal supplied from the main clock generator 10 of the master node 1 is detected from the communication bus 3. If the clock signal of the communication bus 3 is interrupted due to some abnormality, the control unit 21 uses the time determination unit 22 to determine the elapsed time when the clock signal is interrupted. Then, the clock oscillator 20 starts to supply the clock signal to the communication bus 3 on condition that a predetermined reference time has passed with the clock signal being interrupted.

  In the first embodiment, different reference times are set in advance in the spare clock generator 20 of each sub-node 2. In this way, the timing at which each sub-node 2 starts supplying the clock signal is intentionally shifted so that the clock signals are not redundantly supplied from the plurality of sub-nodes 2 at the same timing. On the other hand, in the second embodiment, it is assumed that the spare clock generation unit 20 of each sub node 2 sets a random reference time at a predetermined timing. By doing so, the reference time of each sub-node 2 is varied, so that clock signals are not supplied redundantly from a plurality of sub-nodes 2 at the same timing.

[Example of clock signal supply status]
An example of the supply status of the clock signal in the communication system of this embodiment will be described with reference to FIG.

  In the example of FIG. 2, it is assumed that the supply of the clock signal (main clock) by the master node 1 is stopped. At this time, each subnode 2 measures the elapsed time while monitoring the presence or absence of a clock signal propagating through the communication bus 3. In the case of FIG. 2, the reference time at which the subnode (1) starts outputting the clock signal is t1, and the reference time at which the subnode (2) starts outputting the clock signal is t2 (where t1 <t2). .

  Originally, when the reference time t1 has elapsed after the clock signal is no longer detected, the sub-node (1) starts to supply the clock signal instead of the master node 1. However, here, it is assumed that the sub-node (1) cannot supply the clock signal due to some abnormality. When the reference time t2 elapses without detecting the clock signal as it is, the subnode (2) starts supplying the clock signal in place of the master node 1 and the subnode (1). As a result, the clock signal is supplied to the communication bus 3 again. At this time, the other subnode 2 stops counting the elapsed time by restarting the supply of the clock signal, and monitors the supply status of the clock signal on the communication bus 3. As described above, in the communication system according to the present embodiment, as long as there is a sub-node 2 that operates normally even in a situation where the clock signal cannot be supplied not only from the master node 1 but also from some sub-nodes 2. A clock signal can be supplied to the communication bus 3.

[Description of Clock Supply Start Processing (First Embodiment)]
The procedure of the clock supply start process (first embodiment) executed by the control unit 21 of the spare clock generation unit 20 provided in each sub-node 2 will be described with reference to the flowchart of FIG. This process is repeatedly executed at a predetermined control cycle.

  In S <b> 100, the control unit 21 determines whether a clock signal is supplied to the communication bus 3. When the clock signal is supplied to the communication bus 3 (S100: YES), the control unit 21 ends this process. On the other hand, when the clock signal is not supplied to the communication bus 3 (S100: NO), the control unit 21 proceeds to S102.

  In S102, the control unit 21 determines whether or not a predetermined reference time has elapsed since the start of the current clock supply start process. In the first embodiment, it is assumed that a different reference time is registered in advance for each sub-node 2. When the reference time has not elapsed (S102: NO), the control unit 21 returns to S100. When the reference time has elapsed (S102: YES), the control unit 21 proceeds to S104. In S <b> 104, the control unit 21 starts supplying the clock signal generated by the clock oscillator 24 to the communication bus 3.

[Description of Clock Duplication Avoidance Processing (Second Embodiment)]
In the above-described clock supply start process of the first embodiment, the case where a different reference time is preset for each individual sub-node 2 has been described. As a second embodiment different from this, a configuration in which each sub-node 2 independently sets a random reference time may be used. Specifically, when the slave node 2 starts up and performs the initial clock supply start processing, the control unit 21 sets a random reference time, and thereafter starts clock supply based on the set random reference time. Repeat the process. Note that the clock supply start process of the second embodiment is the same as the clock supply start process of the first embodiment described above (see FIG. 2) except that a procedure for setting a random reference time at the first time is included. Therefore, explanation here is omitted.

  However, when each sub-node 2 sets its own random reference time, the timing for starting the supply of the clock signal rarely overlaps between the plurality of sub-nodes 2, and a plurality of supply sources are provided on the communication bus 3. Clock signals may be mixed. In such a case, since the clock signal propagating on the communication bus 3 becomes unstable, it is necessary to take measures to avoid duplication of the clock signal. Therefore, the procedure of the clock duplication start process (second embodiment) executed by the control unit 21 of the spare clock generation unit 20 provided in each sub-node 2 will be described with reference to the flowchart of FIG. This process is repeatedly executed at a predetermined control period when the spare clock generator 20 of the sub node 2 supplies the clock signal to the communication bus 3.

  In S <b> 200, the control unit 21 determines whether or not the clock signal output from the clock oscillator 24 and the clock signal on the communication bus 3 do not match based on the detection result of the clock signal by the clock detection unit 23. To do. The fact that the clock signal output by itself does not match the clock signal on the communication bus 3 means that the clock signal is supplied to the communication bus 3 redundantly from a plurality of clock signal supply sources. . When the clock signals match (S200: NO), the control unit 21 ends this process. On the other hand, when the clock signals do not match (S200: YES), the control unit 21 proceeds to S202.

  In S202, the control unit 21 resets the reference time to a random time. In the next S204, the control unit 21 stops supplying the clock signal to the communication bus 3. In S206, the control unit 21 resets the elapsed time count by the time determination unit 22 and starts measuring the elapsed time. In S208, the control unit 21 determines whether or not the elapsed time measured by the time determination unit 22 is equal to or more than the reference time reset in S202. When the elapsed time is less than the reference time (S208: NO), the control unit 21 repeats S208. When the elapsed time becomes equal to or longer than the reference time (S208: YES), the control unit 21 proceeds to S210.

  In S <b> 210, the control unit 21 determines whether or not a clock signal is supplied on the communication bus 3. When the clock signal is supplied on the communication bus 3 (S210: YES), the control unit 21 ends this process. On the other hand, when the clock signal is not supplied on the communication bus 3 (S210: NO), the control unit 21 proceeds to S212. In S212, the control unit 21 resumes the supply of the clock signal to the communication bus 3, and ends this process.

  In the second embodiment, a random reference time is set in the first clock supply start process, and the reference time is reset only when a clock signal overlap is detected in the clock overlap avoidance process. By resetting the reference time only when the clock signals overlap, the probability that the reference times overlap among the plurality of subnodes 2 can be reduced.

[effect]
The communication system according to the embodiment has the following effects.
By providing a plurality of subnodes 2 including a spare clock generator 20 that can be used as a spare for the main clock generator 10 provided in the master node 1, the clock signal supply sources can be multiplexed to further increase the reliability of the communication system. Can be realized.

  In the first embodiment, since different reference times are set in advance for each of the sub-nodes 2, it is possible to avoid overlapping timings at which clock signal supply is started. Further, in the second embodiment, each sub-node 2 sets a random reference time independently, thereby making it difficult to overlap the timing for starting the supply of the clock signal. In the unlikely event that the supply of clock signals by a plurality of subnodes overlaps, the reference time is reset and the overlap of clock signals can be eliminated.

  DESCRIPTION OF SYMBOLS 1 ... Master node, 10 ... Main clock generation part, 11 ... Clock oscillator, 2 ... Sub node, 20 ... Preliminary clock generation part, 21 ... Control part, 22 ... Time determination part, 23 ... Clock detection part, 24 ... Clock oscillator, 3. Communication bus.

Claims (5)

A main clock signal output device (1) for outputting a predetermined clock signal for synchronously operating a plurality of nodes connected to the communication bus (3) to the communication bus;
A plurality of spare clock signal output devices (2),
The preliminary clock signal output device comprises:
Generating means (24) for generating the clock signal;
Monitoring the presence or absence of the clock signal propagating on the communication bus, and generating the clock generated by the generation means on the condition that a predetermined reference time has passed with the clock signal on the communication bus being interrupted Control means (21) for outputting a signal to the communication bus,
A clock signal supply system characterized by the above. The clock signal supply system according to claim 1,
The reference time is set in advance different time for each spare clock signal output device,
A clock signal supply system characterized by the above. The clock signal supply system according to claim 1,
The preliminary clock signal output device comprises:
The control means determines a random time length as the reference time, and outputs the clock signal to the communication bus on condition that the reference time has passed with the clock signal on the communication bus being interrupted To do,
A clock signal supply system characterized by the above. The clock signal supply system according to claim 3, wherein
The control means monitors the presence or absence of duplication of the clock signal propagating on the communication bus when outputting the clock signal to the communication bus, and detects the duplication of the clock signal, the reference time As described above, the random time length is determined again, and after the output of the clock signal is stopped, the re-determined reference time has elapsed, and the clock signal is not propagated on the communication bus. Resuming the output of the clock signal,
A clock signal supply system characterized by the above.   The said preliminary | backup clock signal output device used for the clock signal supply system of any one of Claim 1 thru | or 4.