JPH0485870A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of punch through and check the effect of hot carrier by using a side wall for an ion protection mask, implanting impurities into a semiconductor layer on the slant, diffusing the ions, and forming a diffusing layer near the side edge of a gate electrode formation region. CONSTITUTION:Out of device formation regions of a semiconductor layer 1 there are formed diffusion layer pullout electrodes 25 to 28 on both sides of a gate electrode formation region. On this side, an insulating side wall is formed, which is used as a protection mask. Impurity ions are slantingly implanted into the semiconductor layer near the side edge of the gate electrode formation region and the ions are diffused so as to form diffusion layers 33 to 36. Even in terms of a MOS transistor which forms the gate electrodes 23 and 24 on a self-matching basis between the pull-out electrodes 25 to 28, this construction makes it possible to implant impurity ions whose concentration or polarity is different into the semiconductor layer 1 near both sides of the gate electrodes 23 and 24, and diffuse the ions and install a diffusion layer, thereby inhibiting the generation of punch through or the effect of hot carrier.

Description

[Detailed description of the invention]

[Overview] MOS with measures against hot carriers and punch-through
) Regarding a semiconductor device having a transistor and its manufacturing method, the purpose is to suppress the hot carrier effect and punch-through effect of a MOS transistor having a structure in which a gate electrode is formed in a self-aligned manner. Diffusion layer extraction electrodes are formed on both sides of the electrode formation region, insulating sidewalls are formed on the sides of the extraction electrodes, and the diffusion layer extraction including the sidewalls is used as an ion protection mask to prevent impurity ions. The structure includes a diffusion layer formed by implanting impurity ions near the side edge of the Ti formation region. [Industrial Field of Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a MOS transistor with countermeasures against hot carriers and punch-through and a method for manufacturing the same. [Prior Art] In a MOS transistor, @ concentration diffusion layers of the opposite conductivity type are provided on the sides of the source layer and drain layer to prevent punch-through, and the source layer and drain layer are A structure is adopted in which a low concentration diffusion layer of the same conductivity type is formed on the side of the drain layer. An example of a process for manufacturing such an element will be explained based on FIG. 2. In this case, a MOS transistor to prevent punch-through is provided on the right side of the figure, and a MOS transistor to suppress the hot soil rear effect is provided on the left side. First, a first gate electrode 53 is formed on a P-well 51 provided in a semiconductor substrate 50 with a gate insulating film 52 interposed therebetween, and a second gate electrode 53 is formed on an N-well 54 with a gate insulating film 55 interposed therebetween. A gate electrode 56 is provided. Then, using the first gate electrode 53 as a mask, N-type impurity ions are implanted into the surface layer of the semiconductor substrate 50 on both sides thereof to form an N-type ion implantation layer 57. Further, using the second gate electrode 56 as a mask, N-type impurity ions are deeply implanted near both side edges of the second gate electrode 56, and an N-type ion layer 58 is provided below the side where the channel is formed. When implanting each impurity ion, regions where implantation is not necessary are covered with a photoresist (not shown). Next, after forming a SiO□ film over the entire surface, this is anisotropically etched to form sidewalls 59.60 on both sides of the two gate electrodes 53.56, as shown in FIG. 2(b). . Then, an oxide film 49 for element isolation, a site wool 59.
60 and the first gate electrode 53,56 as a mask.
N-type impurities are ion-implanted and diffused into the well 51 to form an N-type ion implantation layer 61. In this case, other areas are covered with photoresist. Similarly, P type impurity ions are implanted into the N well 54 to form P type ion implantation layers 62 on both sides of the second gate electrode 56. Next, when the surface of the semiconductor substrate 50 is annealed to activate impurity ions, a N diffusion layer 64 having a low concentration diffusion layer 63 is formed on both sides of the first gate electrode 53, and a N diffusion layer 64 having a low concentration diffusion layer 63 is formed on both sides of the first gate electrode 53. On both sides of the electrode 56, an N- layer 6 is formed at the lower side end.
A P° diffusion layer 66 provided with 5 is formed (FIG. 2(C)
). After this, an interlayer insulating film 67 is formed on the entire surface, and an interlayer insulating film 67 is formed on the entire surface.
61 through each diffusion layer 64.
Connect electrodes 68 and 69 to 66. Through the above steps, an NMOS transistor having a first gate electrode 53 and an N-type scattering layer 64 and a PMO 5) having a second gate electrode 56 and a P-type scattering layer 66 are formed.
A transistor will be formed. And NMOS
In a transistor, a low concentration diffusion layer 6 with an LDD structure is used.
3 suppresses the generation of hot carriers, and P
In the MOS transistor, the N-type layer 65 on the side of the P''-type diffusion layer 66 suppresses the spread of the depletion layer and prevents the occurrence of punch-through. By the way, in the MO3I-transistor, the source layer In order to reduce the junction capacitance between the drain layer and the semiconductor substrate, it is preferable to reduce the area of the diffusion layer. For example, an element having a structure as shown in FIG. 3 has been proposed. As shown in FIG.
A transistor formation region is narrowly defined in the well 81, and a source lead made of polycrystalline silicon containing impurities is formed in the region extending from both sides of the central gate electrode formation fJl region 72.820 onto the selective oxide film 80 for element isolation. Electrode 73.8
3. Form drain lead electrodes 74 and 84. Insulation M75.85 is formed around each source lead-out electrode 73.83 and drain lead-out electrode 74.84 (FIG. 3(a)). Then, a gate electrode 77.87 is formed in the gate electrode formation region 72.82 with a gate insulating film 76.86 interposed therebetween in a self-aligned manner. Thereafter, the source lead electrodes 73.83 and drain lead electrodes 74.84 on the P well 71 and N well 81 are annealed to remove impurities contained therein. It diffuses into the N well 81 and uses the diffusion layer as the source layer 77.87.
, drain layer 78.88 (FIG. 3(b)). After this, the whole is covered with a glabellar insulating film 79, and then,
Glabella insulation WI7 in the area above the selective oxide film 80 for element isolation
By forming a contact hole in 9 and forming a wiring electrode 89 there, the wiring layer 89 is connected to the source layer 77.87 and the drain layer 78.88 via the source extraction electrode 73.83 and the drain extraction electrode 74.84. (FIG. 3(C)). Thereby, the connection region of the wiring electrode 89 can be set on the element isolation selective oxide film 80, and the source layer 77.
87. It is no longer necessary to provide a margin for a contact hole above the drain layer 78.8, making it possible to narrow the diffusion layer. [Problem to be solved by the invention] However, according to such a structure, the problems shown in FIGS. 2(a) and (b)
As shown in , it is not possible to double-implant impurity ions on both sides of the gate electrodes 77 and 87 as a mask.
In addition, source extraction electrode 73.83, drain extraction electrode 7
If ions are implanted vertically using 4.84 as a mask, the ions will be implanted into the entire gate electrode formation region, so measures must be taken to prevent hot carriers and punch-through in semiconductor devices with this structure. There are inconveniences such as disappearing. The present invention has been made in view of these problems, and provides a semiconductor device and method for manufacturing the same that can suppress the hot carrier effect and bunch-through effect of a MOS transistor having a structure in which a gate electrode is formed in a self-aligned manner. The purpose is to capture and provide information. [Means for Solving the Problems] The above-mentioned problems can be solved by forming the semiconductor layer 3 of one conductivity type covered with an insulating film 9.12 on both sides of the gate electrode formation region, as shown on the left side of FIG. the diffusion layer extraction electrode 25.27, the diffusion layer 29.30 of the opposite conductivity type formed in the semiconductor layer 3 below the diffusion layer extraction electrode 25.27, and the diffusion layer 2
9.30, a low concentration diffusion layer 33, 34 of the opposite conductivity type provided on the side near the gate electrode formation region, and an insulating film 19 on the semiconductor layer 3 in the gate electrode formation region.
or a step of forming diffusion layer lead electrodes 25 and 27 on both sides of a gate electrode formation region in one conductivity type semiconductor layer 3. and,
A step of forming an insulating sidewall 12 on the side of the extraction electrode 25, 27, and using the sidewall 12 and the extraction electrode 2527 as an ion implantation protection mask to obliquely impurity ions of the opposite conductivity type. forming an impurity ion implantation layer 16 of the opposite conductivity type in the vicinity of the side edge of the gate electrode forming region; and heating the semiconductor layer 3 to form the impurity ion implantation layer 1
By activating the diffusion layer lead electrode 25.
forming a low concentration diffusion layer of an opposite conductivity type on the side of the opposite conductivity type diffusion layer 29 and 30 formed under the semiconductor layer 3;
A method for manufacturing a semiconductor device, comprising the step of forming a gate electrode 23 in a self-aligned manner through a gate electrode 9, or as illustrated on the right side of FIG. An insulating film 9.1 is formed on both sides of the electrode formation area.
2, a diffusion layer extraction electrode 26 and 28 formed by covering the
Diffusion layers 31 and 32 of one conductivity type formed in the semiconductor layer 4 under the diffusion layer extraction electrode 262B, and the diffusion layer 3
1.32, a low concentration diffusion layer 3536 of the opposite conductivity type provided on the side closer to the gate electrode formation region and under the channel formation region in the surface layer of the semiconductor layer 4;
A semiconductor device comprising a gate electrode 24 formed on the semiconductor layer 4 in the gate electrode formation region via an insulating film 20, or a gate electrode formation region of the one conductivity type semiconductor layer 4. a step of forming diffusion layer extraction electrodes 26.28 on both sides of the extraction electrode 26.28, a step of forming an insulating sidewall 12 on the side of the extraction electrode 26.28, and a step of forming the sidewall 12 and the extraction electrode 26.28. using it in an ion protection mask,
Impurity ions of the opposite conductivity type are implanted obliquely and deeply into the semiconductor layer 1, and the impurity ions of the opposite conductivity type are implanted near the side edge of the gate electrode formation region and below the channel formation region of the semiconductor layer surface layer 4. By forming a layer 1 and heating the inside of the semiconductor layer 4 to activate the impurity ion implanted layer 1, the diffusion layer lead-out N pole 26.2 is formed.
91. one conductivity type diffusion layer formed under B; 32, and forming a gate electrode 24 in a self-aligned manner on the semiconductor layer 4 in the gate electrode formation region via the insulating film 20. This is achieved by a method of manufacturing a semiconductor device having. [Function] According to the present invention, the diffusion layer lead electrodes 25 to 28 are formed on both sides of the gate electrode forming region in the element formation jIM of the semiconductor layer I, and insulating layer lead electrodes 25 to 28 are formed on the sides of the lead electrodes 25 to 28. In addition to forming the sidewall 12, impurity ions are obliquely implanted into the semiconductor layer near the side edge of the gate electrode formation region using the sidewall 12 as an ion protection mass, and are diffused to form the diffusion layers 33 to 33. 36. For this reason, the gate electrodes 23, 24 of the MOS transistor
On both sides of the source, diffusion layers 29.3 are
A low concentration diffusion layer 33.34 of the same s-type as the diffusion layers 29 and 30 is formed above the side edge of 0, or a diffusion layer 31.32 is formed below the diffusion layer 31.32 which becomes the source and drain.
This means that low concentration diffusion layers 35 and 36 of the opposite conductivity type can be formed. Therefore, between the drawers Np125 to 28, the gate voltage FM
Even in a MOS transistor having a structure in which 23 and 24 are formed in a self-aligned manner, it is possible to implant impurity ions with different concentrations and polarities into the semiconductor layer 1 near both sides of the gate electrode 2324 and diffuse them to form a diffusion layer. This makes it possible to suppress punch-through and hot carrier effects. [Example] The details of the present invention will be explained below based on the drawings. (a) Description of the first embodiment of the present invention Fig. 1 is a sectional view showing the formation process of a device according to an embodiment of the present invention. A silicon substrate provided with a film 2, on the top of which
A P well 3 and an N well 4 are formed. In this state, as shown in FIG. 1(a), the element formation region A of the P well 3 and the element formation region B of the N well 4 are each covered with a nitride film 5.6 with a thickness of 1000 to 1500. After that, the N well 4 is covered with a resist mask (not shown), and boron ions (B') for chaffle cutting are implanted into the surface layer of the P well 3. Next, the P well 3 is covered with another resist mask, and phosphorus ions (P') for channel cutting are implanted into the N well 4. After removing the resist mask, the nitride film 5.6 is
The exposed area is thermally oxidized to grow a selective oxide film 7 for element isolation of 4,000 to 6,000 layers (FIG. 1(b)).
. Next, nitride M5.6 and SiO□Wl below it! ! 2 is removed with phosphoric acid and hydrochloric acid, respectively, and then the first
About 3,000 polycrystalline silicon films 8 are laminated, and then about 500 second Si films 9 are laminated by the CVD method (FIG. 1(C)). Then, while covering the polycrystalline silicon film 8 on the N well 4 with a resist mask (not shown), the implantation energy 7 is
Phosphorus ions (P7) are implanted into the polycrystalline silicon film 8 on the P-well 3 under the conditions of 0 keV and a dose of 101 to 105/cd. After this, the resist mask is changed and the P-well 3 is implanted.
The polycrystalline silicon M8 on the N-well 4 is implanted with an energy of 40 keV and a dose of 10'' to 10' while covering the
Boron ions (B) are implanted under the condition of 5/cd. In this case, the SiO□ film 9 on the surface of the polycrystalline silicon film 8 is
The impurity ions do not penetrate into the silicon substrate l. After this, a 540□ film is laminated on the entire surface using the CVD method, and the thickness of the SiO□ film 9 on the polycrystalline silicon film 8 is increased to 10
00 to 2000 people. After applying the first photoresist 10 to the entire surface, it is exposed and developed, as shown in FIG. 1(d).
Gate electrode formation regions C and D of P well 3 and N well 4
At the same time, the SiO□ film 9 located in the area is exposed, and the area from both sides of the gate electrode formation areas C and D to the top of the selective oxide film 7 is covered with a photoresist 10 (FIG. 1(d)).
. After this, etching is performed using a reactive ion etching method (RIE method) or the like to remove the SiO□ film 9 and the polycrystalline silicon film 8 exposed from the photoresist 10 (the first
Figure (e)). Next, after laminating the third SiO□ film 11 over the entire 1000 to 1500 people (see

[)) This 5i02 film 11 is anisotropically etched using the RIE method so that it remains only on the side wall of the polycrystalline silicon M8, and this is used as the side wall 12 (Fig. 1 (g)), and the gate electrode is formed. The surface of the silicon substrate 1 in the P well 3 and N well 4 exposed from regions C and D is oxidized to form 100 to 200 fourth and fifth 5i02 films 13 and 14, respectively. After this, as shown in FIG. 1(h), after covering the N well 4 with a second photoresist 15, the P well 3 is covered with a second photoresist 15.
Phosphorus ions (P) are implanted at an angle θ1 from the upper end of one side wall to the lower end of the other side wall I2 facing each other in the gate electrode forming region C as a mask. A phosphorus ion implantation layer I6 is provided in the P well 3 near the side edge of the P well 3. In this case, the ion implantation energy is 50ekV and the dose is 1 to 3X]01ff/d. Also, if the distance between the sidewalls 12 is Wl and the height of the sidewalls is d, then the ion implantation angle θ1 is:
The size should be close to θH=tan-'W1/d+. Next, after removing the second photoresist 15, the first
As shown in Figure (i), the P well 3 is covered with a third photoresist 17, and the gate of the N well 4 is
The side walls 12 facing each other on the area are used as masks, and the normal angle θ2 from the upper end of one side to the lower end of the other side wall 12 is used as a mask.
The phosphorus ion implantation layer 18 is provided in the N-well 4 near the side edge of the gate electrode formation region by implanting phosphorus ions at a tilt angle. In this case, the ion implantation energy is 100ekV, the dose is 1 to 3×10'3/d, and the phosphorus ion implantation layer 18 is used to form a channel W! Make the depth so that it does not overlap the area. Further, if the distance between the sidewalls 12 is W2 and the height of the sidewalls is d2, the ion implantation angle θ2 is θz
= Make the size close to the tan bow VL'z/dz. After this, thin SiO in the two gate electrode formation regions C and D is
□ After removing the films 13 and 14, the area is thermally oxidized again to form a gate insulating layer layer 9 and 20, and then, after forming the second polycrystalline silicon film 21, its surface is thermally oxidized. Then, the SiO2 film 42 film type 2 is formed. Next, the implantation energy was 70 keV and the dose was 1°I4-
After implanting phosphorus ions into the entire second polycrystalline silicon film 21 under the condition of 10"/cd, the two gate electrode formation regions C and D are covered with a fourth photoresist 22 (see FIG.
)) Then, the exposed polycrystalline silicon film 21 is etched away by RIE or the like, leaving two polycrystalline silicon films below the photoresist 22 (FIG. 1(k)). Then, the second polycrystalline silicon film 21 on the two gate electrode formation regions C and D and the first polycrystalline silicon M8 on both sides thereof are annealed and activated at a temperature of about 1000''C, and the two The second polycrystalline silicon l1lj21 on the gate electrode formation regions C and D are used as first and second gate electrodes 23, 24, respectively, and the polycrystalline silicon film 8 on both sides thereof is used as source extraction electrodes 25. 26 and the drain extraction electrode 27.2 days. Also, by annealing, impurities in the silicon film 8 are diffused into the P well 3 to form an N-type source layer 29 and a drain layer 3o, respectively. Similarly, P' type source layer 31 and drain layer 32 are formed in P-well 3 and N-well 4. At the same time, the ion-implanted layers 16 and 18 in P-well 3 and N-well 4 are thermally diffused. In No. 3, N- layers 33 and 34 are formed at opposing side ends of the source layer 29 and drain layer 30 of the gate electrode 23, resulting in an LDD structure. On the other hand, in the N well 4, P' An N- layer 3536 is formed at the bottom of the opposite side ends of the source layer 31 and drain layer 32 of the mold.After this, as shown in FIG. An insulating film 37 is formed, and then a contact hole 38.3 is formed in the interlayer insulation M37 on the selective oxidation H7.
9 are provided, and further, aluminum wiring electrodes 4041 are formed through contact holes 38 and 39. According to the above device, the source extraction electrodes 25, 26
, the impurities in the drain extraction electrodes 27 and 28 are diffused into the silicon substrate 1 to form the source layers 29 and 31 and the drain layer 30.
．． 1(h). As shown in (+), since impurity ions are implanted obliquely using the sidewall 12 as a mask, the conductive N33 is selectively implanted only under the both side edges of the gate electrode 23 and 24.
~36 can be formed. That is, in the MOS transistor formed in the P well 3, the low concentration diffusion layer 3 is formed in the source layer 26 and the drain layer 27.
3.34 is selectively formed to form an LDD structure. As a result, the electric fields of the source layer 26 and drain layer 27 are increased to N-
The layers 33 and 34 are weakened and suppress the generation of hot carriers. In addition, in the MOS transistor formed in the N well 4, N- layers 35 and 36 of the opposite conductivity type are selectively formed below the side edges of the P4 type source 1i31 and drain layer 32. The expansion of the depletion layer generated from the interface between the layers is suppressed to prevent the occurrence of punch-through. Note that in this device, since the source layer 29.31 and the drain layer 30.32 can be formed narrowly, it is possible to reduce the junction capacitance generated at the junction between them and the silicon substrate 1. (b) Description of other embodiments of the present invention In the embodiments described above, the sidewall 2 was formed by srozM as shown in FIG. 1(f)Ag).
In the state shown in FIG. 1(e), an oxide film with a thickness of about 200 nm is formed on the surface of the silicon substrate 1 in the gate electrode formation regions C and D, and then a semiconductor film such as polycrystalline silicon is formed over the entire surface. By forming and anisotropically etching this using the RIE method, polycrystalline silicon can be left on the sides of polycrystalline silicon 8, and its surface can be thermally oxidized to form a sidewall. Further, in the above embodiment, the extraction electrodes 26.27 and the gate electrodes 23.24 are formed of polycrystalline silicon, but it is also possible to use high melting point metal silicide. It may be formed of metal or other metal. Furthermore, in the above embodiment, a countermeasure against true carriers was taken for the NMOS transistor, and a countermeasure against punch through was taken for the PMOS transistor, but the same effect could be obtained by using a structure in which the P-type and N-type are reversed. It is possible. [Effects of the Invention] As described above, according to the present invention, diffusion layer extraction electrodes are formed on both sides of the gate electrode formation region in the element formation region of the semiconductor layer, and insulating side electrodes are formed on the sides of the extraction electrode. In addition to forming a wall, this sidewall is used as an ion protection mask to implant impurity ions into the semiconductor layer at an angle, and to diffuse them to form a diffusion layer near the side edges of the gate electrode formation region. Therefore, even in a MOS transistor with a structure in which a gate electrode is formed between lead electrodes in a self-aligned manner, impurity ions are doubly implanted into the semiconductor layer near both sides of the gate electrode to form diffusion layers with different concentrations and polarities. can be provided, making it possible to prevent the occurrence of punch-through and suppress the real carrier effect.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the forming process of a device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a first example of the forming process of a conventional device, and FIG. 3 is a cross-sectional view showing the forming process of a conventional device. It is a sectional view showing a second example. (Explanation of symbols) 1... Silicon substrate (semiconductor layer), 2... 5i (h film, 3... P well, 4... N well, 5.6... Nitride film, 7. ...Selective oxide film, 8...Polycrystalline silicon film, 9.11...SiO□ film, 12...Side wall, 13.14...5ifh film, 16.18...Phosphorus ion implantation Layer, 19.20... Gate oxide film, 21... Polycrystalline silicon film, 22... Photoresist, 23.24... Gate electrode, 25.26... Source extraction electrode, 27.2 Day...Drain extraction electrode, 9.31...Source layer (diffusion layer), 0.32...Drain layer (diffusion layer), 3.34...
N− layer (low concentration diffusion layer) 5.36...N゛ layer (high concentration diffusion layer) 2...SiO□ film. Applicant Fujitsu Co., Ltd.

Claims (4)

[Claims] (1) Diffusion layer lead-out electrodes (25, 27) formed on both sides of the gate electrode formation region of the one-conductivity type semiconductor layer (3) and covered with insulating films (9, 12); electrode(
diffusion layers (29, 30) of opposite conductivity type formed in the semiconductor layer (3) below the semiconductor layer (25, 27); and a side portion of the diffusion layer (29, 30) closer to the gate electrode formation region. A low concentration diffusion layer of opposite conductivity type (
33, 34); and a gate electrode (23) formed on the semiconductor layer (3) in the gate electrode formation region via an insulating film (19). (2) forming diffusion layer lead electrodes (25, 27) on both sides of the gate electrode formation region of the one-conductivity type semiconductor layer (3); and forming an insulating layer on the sides of the lead electrodes (25, 27). A step of forming a sidewall (12), and using the sidewall (12) and the extraction electrodes (25, 27) as an ion implantation protection mask, impurity ions of the opposite conductivity type are obliquely implanted into the semiconductor layer (3). ) to form an impurity ion implantation layer (16) of the opposite conductivity type near the side edge of the gate electrode formation region; heating the semiconductor layer (3) to form an impurity ion implantation layer (16) ) of the opposite conductivity type formed under the diffusion layer extraction electrodes (25, 27).
A low concentration diffusion layer (33) of the opposite conductivity type is formed on the sides of the
, 34), and forming a gate electrode (23) in a self-aligned manner in the gate electrode formation region on the semiconductor layer (3) via an insulating film (19). A method for manufacturing a featured semiconductor device. (3) Diffusion layer extraction electrodes (26, 28) formed on both sides of the gate electrode type region of the opposite conductivity type semiconductor layer (4) and covered with insulating films (9, 12); electrode(
a diffusion layer (31, 32) of one conductivity type formed in the semiconductor layer (4) below 26, 28); and a side portion of the diffusion layer (31, 32) closer to the gate electrode formation region. a low concentration diffusion layer (35, 36) of opposite conductivity type provided under the channel formation region in the surface layer of the semiconductor layer (4); and the semiconductor layer (4) in the gate electrode formation region. ) and a gate electrode (24) formed on the semiconductor device with an insulating film (20) interposed therebetween. (4) forming diffusion layer extraction electrodes (26, 28) on both sides of the gate electrode formation region of the opposite conductivity type semiconductor layer (4); and forming an insulating layer on the sides of the extraction electrodes (26, 28). A step of forming a sidewall (12), and using the sidewall (12) and the extraction electrode (26, 28) as an ion protection mask, impurity ions of the opposite conductivity type are obliquely directed into the semiconductor layer (4). forming an impurity ion implantation layer (18) of the opposite conductivity type near the side edge of the gate electrode formation region and below the channel formation region of the surface layer of the semiconductor layer (4); By heating the inside of the semiconductor layer (4) and activating the impurity ion implantation layer (18), one conductivity type diffusion layer (3) is formed under the diffusion layer extraction electrode (26, 28).
1, 32), a low concentration diffusion layer (35,
36); and forming a gate electrode (24) in a self-aligned manner on the semiconductor layer (4) in the gate electrode formation region via an insulating film (20). Production method.