JPH0485856A - Contact hole of semiconductor device - Google Patents
Contact hole of semiconductor deviceInfo
- Publication number
- JPH0485856A JPH0485856A JP19979690A JP19979690A JPH0485856A JP H0485856 A JPH0485856 A JP H0485856A JP 19979690 A JP19979690 A JP 19979690A JP 19979690 A JP19979690 A JP 19979690A JP H0485856 A JPH0485856 A JP H0485856A
- Authority
- JP
- Japan
- Prior art keywords
- contact hole
- oxide film
- silicon oxide
- side wall
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 36
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 36
- 239000012535 impurity Substances 0.000 abstract description 12
- 238000005530 etching Methods 0.000 abstract description 10
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 239000007789 gas Substances 0.000 abstract description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- 229910001882 dioxygen Inorganic materials 0.000 abstract description 2
- 229910000077 silane Inorganic materials 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000005380 borophosphosilicate glass Substances 0.000 description 7
- 239000010410 layer Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- PBXYLMVLLSYZLN-UHFFFAOYSA-N 5beta-Ranol Natural products OC1CC2CC(O)CCC2(C)C2C1C1CCC(C(CCC(O)CCO)C)C1(C)C(O)C2 PBXYLMVLLSYZLN-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 101150092880 DREB1A gene Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 101100166255 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CEP3 gene Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、アルミニウムとアルミニウム、又はアルミ
ニウムと不純物拡散層などのコンタクトホールを有する
半導体装置の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an improvement in a semiconductor device having a contact hole made of aluminum and aluminum, or aluminum and an impurity diffusion layer.
第4図ないし第8図は従来の半導体装置の製造工程に従
って示す半導体装置の断面図である。図において、(1
)はシリコン基板、(2)はフィールド酸化シリコン膜
、(8)は多結晶シリコン膜、(4)は不純物拡散層、
(5)はノンドープ酸化シリコン膜、(6)はボロン、
リンの不純物を含んだ酸化シリコン膜(以下BPSG膜
という) 、 (7)はシラノール酸化シリコン膜、(
8)はレジスト、(9)はコンタクトホール、嶽はアル
ミニウム、σDはくぼみである。4 to 8 are cross-sectional views of a semiconductor device shown in accordance with a conventional semiconductor device manufacturing process. In the figure, (1
) is a silicon substrate, (2) is a field silicon oxide film, (8) is a polycrystalline silicon film, (4) is an impurity diffusion layer,
(5) is a non-doped silicon oxide film, (6) is boron,
(7) is a silicon oxide film containing phosphorous impurities (hereinafter referred to as BPSG film), (7) is a silanol silicon oxide film, (
8) is a resist, (9) is a contact hole, mount is aluminum, and σD is a depression.
次に動作について説明する。まず第4rgJに示すよう
にシリコン基板(1)上に、 6oooX程度の比較
的厚いフィールド酸化シリコン膜(2)を形成し念後図
中にはないが% 200A程度の比較的薄いゲート酸
化シリコン膜を生成し、ゲート電極となる多結晶シリコ
ン膜(8)を約4000A生成する。多結晶シリコン膜
(8)にはリンなどの不純物を熱拡散することによりシ
ート抵抗を約500/口程度にする。次に、通常の写真
製版技術を用いて、レジストをマスクにゲート電極とな
る多結晶シリコン膜(8)およびゲート酸化膜をエツチ
ングし、シリコン基板(1)の一部を露出させる。第4
図は配線として配置された多結晶シリコン膜(8)を示
している。Next, the operation will be explained. First, as shown in the 4th rgJ, a relatively thick field silicon oxide film (2) of about 600X is formed on the silicon substrate (1), and then a relatively thin gate silicon oxide film of about 200A (not shown in the figure) is formed. A polycrystalline silicon film (8) of about 4000 A is formed to become a gate electrode. The polycrystalline silicon film (8) is made to have a sheet resistance of about 500/hole by thermally diffusing impurities such as phosphorus. Next, the polycrystalline silicon film (8) that will become the gate electrode and the gate oxide film are etched using a resist as a mask using a normal photolithography technique to expose a part of the silicon substrate (1). Fourth
The figure shows a polycrystalline silicon film (8) arranged as a wiring.
次にシリコン基板(1)の露出した領域に通常のイオン
注入技術を用いて、シリコン基板(1)と反対の導電型
不純物を注入した後、900°030分程度の熱処理を
施こすことにより不純物拡散層(4)を形成する。次に
第5図に示すように、シランガスト酸素ガスにより約8
0 (1’o程度の温度でノンドープ酸化シリコン膜(
6:をCVD法を用いて約2000λ堆積させる。この
ノンドープ酸化シリコン膜(5)は後述するBPSG膜
(6)などの不純物をシリコン基板(1)等に拡散させ
ない目的で形成する。次に、平坦性を良くする念め液状
の酸化シリコン膜であるシラノール酸化膜(γンを塗布
する。シラノール酸化シリコン膜(7)はある粘度を持
つ九液状の物質である為第5図に示すように段差の低い
所に堆積する。次に800°C程度の熱処理を行うこと
によシシラ/−ル酸化シリコン膜(7)を固めた後、
CVD法を用いてBpsa膜(6)を約800OA堆
積する。、BPSG膜(6)は不純物を含んでいる為、
後の熱処理(900’030分程度)で比較的平坦とな
る。次に第6図に示すように、写真製版技術を用いてレ
ジスト(8)をマスクに、上記層間膜を開孔しコンタク
トホール(9)を設ける。まず20:1=N日4F:T
I’F溶液にてBPSG膜(6)を約4000二ウエツ
トエツチングする。この際第6図に示すようにコンタク
トホール(9)の上部は傾斜を持って横方向にサイドエ
ツチングされる。次に同じレジスト(8)をマスクに残
っているBPSG膜(6)、シラノール酸化シリコン膜
(ア)およびノンドープ酸化シリコy 膜(5! f
OHF 3 +02ガスを用いてプラズマエツチングす
る。この時のエツチングレートはノンドープ酸化シリコ
ン膜(5)およびBPSG模(6)は600〜900λ
、7分である。ンラノール酸化シリコン膜(ア)は15
00 A 、/分程度である。このプラズマエツチング
は異方性エツチングである為、第6e K 示すように
、レジスト(8)のサイズとほぼ同程度の開孔部が設け
られ、その開孔部の側壁は、シリコン基板(1)K対し
てほぼ垂直とな6゜コンタクトホール(9)を開孔した
後、レジスト(8)を除去する。Next, impurities of the opposite conductivity type to the silicon substrate (1) are implanted into the exposed region of the silicon substrate (1) using normal ion implantation technology, and then heat treatment is performed for about 900°030 minutes to remove the impurities. A diffusion layer (4) is formed. Next, as shown in Figure 5, approximately 8
0 (Non-doped silicon oxide film (
6: is deposited to a thickness of about 2000λ using the CVD method. This non-doped silicon oxide film (5) is formed for the purpose of preventing impurities such as a BPSG film (6) to be described later from diffusing into the silicon substrate (1) and the like. Next, a silanol oxide film (γ), which is a liquid silicon oxide film, is applied to improve the flatness.The silanol silicon oxide film (7) is a liquid substance with a certain viscosity, so it is shown in Figure 5. As shown, the silicon oxide film (7) is deposited at a low level.Next, the silicon oxide film (7) is hardened by heat treatment at about 800°C.
A Bpsa film (6) of approximately 800 OA is deposited using the CVD method. , since the BPSG film (6) contains impurities,
After the subsequent heat treatment (approximately 900'030 minutes), the surface becomes relatively flat. Next, as shown in FIG. 6, a contact hole (9) is formed in the interlayer film by using a photolithography technique and using the resist (8) as a mask. First 20:1=N day 4F:T
The BPSG film (6) is wet etched for approximately 4,000 ml using an I'F solution. At this time, as shown in FIG. 6, the upper part of the contact hole (9) is laterally side-etched with an inclination. Next, use the same resist (8) as a mask to mask the remaining BPSG film (6), silanol silicon oxide film (a), and non-doped silicon oxide film (5!f).
Plasma etching is performed using OHF 3 +02 gas. The etching rate at this time was 600 to 900λ for the non-doped silicon oxide film (5) and the BPSG model (6).
, 7 minutes. Ranol silicon oxide film (a) is 15
00 A,/min. Since this plasma etching is anisotropic etching, an opening approximately the same size as the resist (8) is provided as shown in No. 6eK, and the side wall of the opening is formed on the silicon substrate (1). After opening a 6° contact hole (9) substantially perpendicular to K, the resist (8) is removed.
除去の方法は硫酸などの強酸性溶液に浸すことにより行
う。この時不純物拡散層(4)表面が露出している為、
この露出し九表面に酸化シリコン膜が約100A程度生
成されてしまう(図示せず)。従つてアルミニウム叫を
蒸着する前に、フッ酸溶液を用いて少し上記酸化シリコ
ン膜をエツチングする。例えば20:1=NHnF:E
rr溶液の場合、シラノール酸化シリコン膜(テ)は約
2500λ/分、/ンドープ酸化シリコン膜+51およ
びBPSG膜(6)は約400〜500A/分のエツチ
ングレートである。今レジスト(8)を除去する時に生
成された約10OAの酸化シリコン膜を除去するため2
0:1 = NH<F : )IF溶液に30秒浸すと
第7図に示すように、コンタクトホール(9)の側壁部
のシラノール酸化シリコン膜(7)はサイドエツチング
され約0゜17程度のくぼみσひが形成される。次に第
8図に示すごとく、アルミニウム叫を蒸着する。Removal is performed by immersion in a strong acid solution such as sulfuric acid. At this time, since the surface of the impurity diffusion layer (4) is exposed,
A silicon oxide film of about 100 A is formed on this exposed surface (not shown). Therefore, before depositing the aluminum layer, the silicon oxide film is slightly etched using a hydrofluoric acid solution. For example, 20:1=NHnF:E
In the case of the rr solution, the silanol silicon oxide film (Te) has an etching rate of about 2500 λ/min, and the /N doped silicon oxide film +51 and BPSG film (6) have an etching rate of about 400-500 A/min. 2 to remove the silicon oxide film of approximately 10 OA generated when removing the resist (8).
0:1 = NH<F: ) When immersed in the IF solution for 30 seconds, the silanol silicon oxide film (7) on the side wall of the contact hole (9) is side-etched to a depth of approximately 0°17 as shown in Figure 7. A depression σ is formed. Next, as shown in FIG. 8, aluminum is deposited.
従来の半導体装置のコンタクトホールは以上のように構
成されているので、くぼみが形成された状態で、アルミ
ニウムを蒸着した場合第8図に示すように上記くぼみの
部分にアルミニウムが付着せずコンタクトホール内でア
ルミニウムが断線することがあるといの問題点があった
。Contact holes in conventional semiconductor devices are constructed as described above, so when aluminum is deposited with a depression formed, the contact hole does not adhere to the depression as shown in Figure 8. There was a problem in that the aluminum could break inside.
この発明は以上のような問題点を解消するなめになぜ7
′1.念もので、アルミニウムとコンタクトホール側壁
部との接続性の良好な半導体装置のコンタクトホールを
得ることを目的とする。Why did this invention solve the above problems?
'1. The purpose is to obtain a contact hole for a semiconductor device with good connectivity between aluminum and the side wall of the contact hole.
この発明による半導体装置のコンタクトホールは、コン
タクトホール側壁部にエツチングレートの遅い物質を形
成するようにし次ものである。The contact hole of the semiconductor device according to the present invention has a material having a slow etching rate formed on the side wall of the contact hole.
この発明における半導体装置のコンタクトホールは、コ
ンタクトホール側壁部にエツチングレートの遅い物質を
形成したので、コンタクトホール側壁部におけるくぼみ
の発生を抑えることができる。In the contact hole of the semiconductor device according to the present invention, since a material having a slow etching rate is formed on the side wall of the contact hole, it is possible to suppress the formation of depressions on the side wall of the contact hole.
以下にこの発明の一実施例を図について述べる。 An embodiment of the present invention will be described below with reference to the drawings.
第1図ないし第3図は半導体装置の製造工程に従って示
す半導体装置の断面図である。図において、(1)〜(
7)、■は第4図ないし第8図の従来例に示したものと
同等であるので説明を省略する。(L2は酸化シリコン
膜である。次に動作について説明する。まず第7図の従
来例に示したコンタクトホール(9)の側壁部にくぼみ
σDが形成でれた後、第1図に示すように酸化シリコン
膜0をシランガスと酸素ガスを用いて約800°C程度
の高温でOVD法を用いて約2000A堆積する。この
時s o crc程度の比較的高温で生成する為、コン
タクトホールf9+の側壁部のくぼみαDは十分酸化シ
リコン膜fi3で埋まる。次にCBF3+ 02ガスプ
ラズマを用いて酸化シリコン膜azを異方性全面エツチ
ングする。1 to 3 are cross-sectional views of a semiconductor device shown according to the manufacturing process of the semiconductor device. In the figure, (1) to (
7) and (2) are the same as those shown in the conventional examples shown in FIGS. 4 to 8, so their explanation will be omitted. (L2 is a silicon oxide film. Next, the operation will be explained. First, after a depression σD is formed on the side wall of the contact hole (9) shown in the conventional example in FIG. A silicon oxide film 0 is deposited using silane gas and oxygen gas for approximately 2000A using the OVD method at a high temperature of approximately 800°C.At this time, since the silicon oxide film 0 is formed at a relatively high temperature of approximately SO CRC, the contact hole f9+ is The depression αD in the side wall portion is sufficiently filled with the silicon oxide film fi3.The silicon oxide film az is then anisotropically etched over the entire surface using CBF3+02 gas plasma.
このエツチングは異方性である為第2図に示すように酸
化シリコン膜αzVi垂直断差のあるコンタクトホール
(9ンの側壁部のみ形成される。上記ガスプラズマエツ
チングの時間はコンタクトホール(9)底部の不純物拡
散層(4)が露出し、かつ、コンタクトホール(9)側
壁部のシラノール酸化シリコン膜(ア)が露出しないよ
う設定する必要がある。Since this etching is anisotropic, only the side wall of the contact hole (9) with a vertical difference in the silicon oxide film αzVi is formed as shown in FIG. It is necessary to set it so that the impurity diffusion layer (4) at the bottom is exposed and the silanol oxide silicon film (A) on the side wall of the contact hole (9) is not exposed.
次に第3図に示すように従来技術と同様にアルミニウム
面を形成する。この時コンタクトホール(9)内の側壁
はくぼみがない為、コンタクトホール(9ンの側壁には
十分のアルミニウム面の膜厚が得うれる。Next, as shown in FIG. 3, an aluminum surface is formed in the same manner as in the prior art. At this time, since there is no depression on the side wall of the contact hole (9), a sufficient thickness of the aluminum surface can be obtained on the side wall of the contact hole (9).
以上のように構成された半導体装置のコンタクトホール
(9)の側壁部はフッ酸溶液に対してはぼ同程度のエツ
チングがレートを有する為コンタクトホール(9)の側
壁部にくぼみが形成されず、アルミニウム面の接続が容
易で高歩留、かつ信頼性が高くなる。The side wall of the contact hole (9) of the semiconductor device configured as described above has an etching rate of approximately the same level when exposed to a hydrofluoric acid solution, so no depression is formed on the side wall of the contact hole (9). , easy connection of aluminum surfaces, high yield, and high reliability.
なお、上記実施例ではコンタクトホール側壁部にくぼみ
σ11を形成した後、酸(ヒシリコン膜r1zを形成す
る場合について説明したが、当然くぼみqIlが形成さ
れる前に酸化シリコン膜、15を生成しても同様の効果
がある。又、くぼみQl+を埋め込む物質として、酸化
シリコン膜α2を用いた場合を示したが窒化シリコン膜
、又は多結晶シリコン膜のような導電性物質でも良い。In the above embodiment, the case where the acid (arsenic film r1z) is formed after the depression σ11 is formed on the side wall of the contact hole has been described, but of course the silicon oxide film 15 is formed before the depression qIl is formed. Also, although the silicon oxide film α2 is used as the material for filling the depression Ql+, a conductive material such as a silicon nitride film or a polycrystalline silicon film may also be used.
又上記実施例では不純物拡を層(4)とアルミニウム面
のコンタク) ホー ル+91の場合を示したが、その
他のコンタクトホールでも良く、少なくともアルミニウ
ム叫下の層間絶縁膜を開孔するコンタクトホールの場合
は同様の効果がある。又上記実施例ではシラノール酸化
シリコン膜(γ)を用いた場合を示したが、他の物質で
も同様であり層間絶縁膜を多層物質で形成する場合には
同様の効果がある。In addition, in the above embodiment, impurity diffusion is caused by contact hole +91 between the layer (4) and the aluminum surface, but other contact holes may also be used. It has a similar effect. Further, in the above embodiment, a case was shown in which a silanol oxide silicon film (γ) was used, but other materials can be used as well, and similar effects can be obtained when the interlayer insulating film is formed of a multilayer material.
以上のように、この発明によれば半導体装置のコンタク
トホールの側壁部を同一物質で形成するように構成した
ので、アルミニウムの接続が容易で信頼性の高い半導体
装置のコンタクトホールが(lddアルミニウム、 (
1′Jは酸化シリコン膜である。As described above, according to the present invention, the side walls of the contact holes of the semiconductor device are formed of the same material, so that the contact holes of the semiconductor device can easily connect aluminum and have high reliability (ldd aluminum, (
1'J is a silicon oxide film.
なお、図中、同一符号は同一、又は相当部分を示す。In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
膜で形成した半導体装置において、上記層間絶縁膜に開
孔して設けたコンタクトホールの側壁部が同一物質で形
成されたことを特徴とする半導体装置のコンタクトホー
ル。A semiconductor device in which an interlayer insulating film under an aluminum film is formed of a multilayer film of different materials, characterized in that side walls of contact holes formed in the interlayer insulating film are formed of the same material. Device contact hole.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19979690A JPH0485856A (en) | 1990-07-26 | 1990-07-26 | Contact hole of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19979690A JPH0485856A (en) | 1990-07-26 | 1990-07-26 | Contact hole of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0485856A true JPH0485856A (en) | 1992-03-18 |
Family
ID=16413766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19979690A Pending JPH0485856A (en) | 1990-07-26 | 1990-07-26 | Contact hole of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0485856A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100494648B1 (en) * | 1997-12-30 | 2005-09-30 | 주식회사 하이닉스반도체 | Aluminum deposition method with improved step coverage |
-
1990
- 1990-07-26 JP JP19979690A patent/JPH0485856A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100494648B1 (en) * | 1997-12-30 | 2005-09-30 | 주식회사 하이닉스반도체 | Aluminum deposition method with improved step coverage |
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