JPH0485751U - - Google Patents

Info

Publication number
JPH0485751U
JPH0485751U JP12850790U JP12850790U JPH0485751U JP H0485751 U JPH0485751 U JP H0485751U JP 12850790 U JP12850790 U JP 12850790U JP 12850790 U JP12850790 U JP 12850790U JP H0485751 U JPH0485751 U JP H0485751U
Authority
JP
Japan
Prior art keywords
optical semiconductor
mounting piece
lead terminal
semiconductor device
completion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12850790U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12850790U priority Critical patent/JPH0485751U/ja
Publication of JPH0485751U publication Critical patent/JPH0485751U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Description

【図面の簡単な説明】
第１図は本考案の一実施例に係る光半導体装置
のリードフレームの形状を示す図であり、同図ａ
はサイドビユータイプの光半導体装置のワイヤボ
ンド完了時点を示す図、同図ｂはダブルエンドタ
イプの光半導体装置のワイヤボンド完了時点を示
す図、第２図は両タイプの光半導体装置のモール
ド完了時点を示す図、第３図はサイドビユータイ
プの光半導体装置のタイバーカツト完了時点を示
す図、第４図は同じくそのケーシング完了時点を
示す図、第５図は同じく完成品を示す図、第６図
はダブルエンドタイプの光半導体装置のタイバー
カツト完了時点を示す図、第７図は同じくそのケ
ーシング完了時点を示す図、第８図は同じく完成
品を示す図であり、同図ａは正面図、同図ｂは側
面図、第９図は同じくフオーミング完了時点を示
す図であり、同図ａは正面図、同図ｂは側面図、
第１０図は従来の光半導体装置のワイボード完了
時点を示す図、第１１図は同じくそのモールド完
了時点を示す図、第１２図は同じくタイバーカツ
ト完了時点を示す図、第１３図は同じくケーシン
グ完了時点を示す図である。 １０……リードフレーム、１１……光半導体素
子、１５，１６……１次側リード端子、１７……
搭載片、１８，１９……上２次側リード端子、２
０，２１……下２次側リード端子。

Claims (1)

    【実用新案登録請求の範囲】
  1. リードフレームに光半導体素子が搭載され、こ
    れらがモールドされて成る光半導体装置において
    、前記リードフレームは、上下一対の１次側リー
    ド端子と、光半導体素子が搭載される搭載片と、
    搭載片の上端に近接して設けられたボンデイング
    ワイヤ接続用の上２次側リード端子と、搭載片の
    下端に近接して設けられたボンデイングワイヤ接
    続用の下２次側リード端子とから構成され、前記
    搭載片は、上１次側リード端子と下次側リード端
    子とにより両持ち支持されたことを特徴とする光
    半導体装置。
JP12850790U 1990-11-29 1990-11-29 Pending JPH0485751U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12850790U JPH0485751U (ja) 1990-11-29 1990-11-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12850790U JPH0485751U (ja) 1990-11-29 1990-11-29

Publications (1)

Publication Number Publication Date
JPH0485751U true JPH0485751U (ja) 1992-07-24

Family

ID=31875966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12850790U Pending JPH0485751U (ja) 1990-11-29 1990-11-29

Country Status (1)

Country Link
JP (1) JPH0485751U (ja)

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