JPH0485643A - Information processor - Google Patents

Abstract

PURPOSE:To unnecessitate the change of contents stored in a storage means inside the processor at the time of the inspection of peripheral equipment in the storage means of each equipment. CONSTITUTION:More than one processors 22 equipped with central processing units (CPU) and internal storage means 25 storing the programs necessary for at least the control of its own and the inspection, and more than one peripheral equipment 23, 24 equipped with internal storage means 27, 28 storing the program necessary for at least the control of its own and the inspection, are provided. The programs subject to each peripheral equipment 23, 24 are independently stored for equipment 23, 24. Thus, the programs subject to each peripheral equipment 23, 24 are physically separated from the storage means 25 inside the processor 22 and the change and addition of the program subject to the peripheral equipment 23, 24 are performed without changing the programs stored in the storage means 25 inside the processor 22.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an information processing device configured by connecting one or more processor devices consisting of a CPU and its peripheral circuits and one or more peripheral devices to a system bus. 3゜Prior Art Generally, in such an information processing device, programs that depend on each device necessary for inspection and control of each component device are stored in a storage means in a processor device. .This storage means tri, Mjo EP
ROM, EEPROM, FROM, -i or mask RO
It consists of M, etc.

A conventional information processing device will be explained below using figures.

FIG. 3 shows an information processing device configured by connecting a conventional processor device consisting of a CPU and its peripheral circuits, and other peripheral devices to a system bus. In the figure, the connection between the device and the system bus is called a slot. 41 is a first slot, 42 is a second slot, and 43 is a third slot. 4
4 is a signal for address, data, and control. 45 is a processor device, 46 is a main storage device as an example of a peripheral device, 47 is an input/output control device as an example of a peripheral device, and 48 is a storage means in the processor device 46, which is an EPROM in this example. 49 is a CPU of the processor device 45; 401 is a CPU from the first slot 41 to the second slot 4;
2, and 402 is a signal used to access the third node 43 from the first node 41, which together with the address, data, and control signals 44 form the system bus 40. .

Programs and brochure devices dependent on peripheral devices 45
The program 11 that is subordinate to the device is the broker device 45.
It is stored in the EPROM 48, which is a storage means in the internal memory.

Processor unit 46 uses peripheral device dependent programs stored in EPROM 48 to test and control the device.

The inspection operation of the system shown in FIG. 3 will be explained with reference to the flowchart shown in FIG. After resetting, start running the inspection.
Ru. First, in step 1, the processor device 45 is inspected. The CPU 4.9 retrieves instructions and data from the EPROM 4B and tests the processor unit 46. Next, check the storage device 46 of the slurry tube 2e1.
Execute commands and data from PROM 4s. Next, the input/output control device 47 is inspected in the slave block 3 by fetching instructions and data from the EPROM 48.

Similarly, when processing information, 1: storage device 46
When necessary, such as changing the settings of the input/output control device 47, etc., each device is controlled using the program 7 stored in the EPROM 48.

[Problems to be Solved by the Invention] 2. In the conventional configuration, when changing or adding an inspection method of a device, or changing or adding a control method, the method is stored in a storage means in a processor device and is dependent on the device. The program must be changed.

However, even if the hardware conforms to the system bus standard, the program file that is subordinate to the device and stored in the storage means in the processor device is not targeted.
When connecting an information processing device to the system bus of an information processing device, the program subordinate to the device stored in the storage means in the processor device is changed to be inspected and controlled, or the program subordinate to the device of the device is changed. is recorded in secondary storage,
It must be loaded into main memory, inspected, and controlled.

The present invention solves the conventional problem described in -1-, and it is not necessary to change the contents stored in the storage means in the processor device when changing or adding an inspection method of the device or changing or adding a control method. The purpose is to

Means for Solving the Problems In order to achieve the object described in (), the information processing apparatus of the present invention stores programs subordinate to the apparatuses of each apparatus in the storage means of each apparatus. It has a configuration in which a processor device uses a program file subordinate to the device to inspect and control each device.

Function: With this configuration, programs that are dependent on each device are stored independently for each device, so the above program can be created independently of the programs of other devices, and it is possible to change, add, or control the inspection method of the device. When changing or adding a method, it is not necessary to change the contents stored in one stage of storage in the processor device.

Embodiment One embodiment of the invention will be described with reference to the drawings.

FIG. 1(a) is a block diagram of the information processing apparatus of the present invention, mainly showing the system specifications.

11 is an address signal, 12 is a data signal, 13 is ID5
PACE signal, 14 is B I D times 'J, -157d-
'P' are multiple signal lines that control other system buses.

The connection between the device and the system bus is called a slot. .

B1. The D signal 14 has five signals, one for each binary number "c"
Wired to indicate the slot number. 16 is the 1st slot, 17 is the 2nd slot, 1st is the 2nd slot (Db
``This is Sloft J. 19 are the respective devices connected to the system bus.
The system bus has an address space different from the normal address space for accessing the main memory and input/output devices, and is called an ID space. ID5
When PACE credit 3 is valid, access is made to ID space [7]. At this time, 1 of address signal 11
The five signals at - are used to specify the slot number, and by comparing it with the slot number input to the device from the BID signal 14, the device detects that it has been selected. do. Another part of the address signal 11 is j, which is used for addressing in the ID space. In this way, the ID sparse uses the number of each thrower as an offset.
1 assigned to the ζ address, an ID information section 10i in which the device type, name, history of specification changes, etc. are stored, and a progera J that is subordinate to the device are stored in the ID program section 102, which is assigned to the ID space. has been
It is stored in the storage means 103 of each device.

FIG. 1('b) shows the equipment configuration of the information processing device of the present invention (21 is a system 7 to bus, 22t is a processor device, 23 is an example of a peripheral device, and 1 is a storage device. , 24 is an example of a peripheral device, and 25 is an input/output control device F1' for C, and 25 is a memory in the device, a means of
- EFROM as an example, 26 is a medium-heat calculation unit (hereinafter abbreviated as FCPU) of the processor device 22, 2A is an example of a storage means of the storage device 23, and FROM is C; 28 is Ota Rikisei (2) device EEP as an example of 24 storage means 2
I(OM, 29 is an internal memory of the processor device 22.

- A program which is subordinate to each peripheral device and which controls and tests at least one device is stored as an ID program portion in a storage means within each peripheral device. Log files belonging to peripheral devices are not stored in the storage means 25 in the professional storage device 22.

A program that is subordinate to the processor device 7 and controls all its operations is stored in the storage means 26 within the professional processor device 22.

It consists of the above-mentioned constituent elements, and the mutual relationship and operation of each constituent element will be explained and explained with reference to FIG.

FIG. 2 shows a flowchart of an example of the inspection operation of this information processing device. After completing the test, the actual inspection begins. First, in step 1, the processor device 22 (starting from D-inspection M) is executed.
) Access the "D information section of the ID space and store in the internal memory 29 a table showing which devices are connected to which slots. While referring to this table, write the ID program section of the ID space of each device. 10 instructions and data are read into the internal memory 29 and executed.In this embodiment, the main storage device 23 is next checked in the slave 2 by reading the instructions and data from the storage means 2. ” Proceed as in step 2. Then, in step 3, the input/output control (2) device 24 is tested in the same manner.

Similarly, when processing information, this information processing device can change the information in the ID information section and the
Stored in the D program section [at 2].

Use Lograno to control each device.

As described in 1- above, according to this embodiment, the log file subordinate to each peripheral device is stored in the storage means in each peripheral device with ID7'o log file. Mube and [Memories in 7
In addition, the program '7 belonging to vf in the processor device 7 is stored in the storage means 25 in the processor device 22, so that the program dependent on each peripheral device can be stored in the storage means in the processor device. It can be physically separated from the program and logically independent from the program stored in the first stage of memory in the processor, and changes and additions to programs that are dependent on the peripheral device can be made
This can be done without changing the program 1 stored in the storage means in the LI setup device.

(1) In the embodiment, the CPU of the processor device that constitutes the entire information processing apparatus is one; however, the CPU of the 7'rI processor may be present in number.

(2) In the embodiment, the blocks 1-
The number of processing devices is one, but there may be a plurality of processor devices, and there may be five.

(3) In the embodiment, the ID base is provided separately from the normal address space, but it is divided into the normal address space (1
You can leave it. (4) In the embodiment, the internal memory of the processor device is used. 1. Instructions and data may be fetched from the section.

(5) In the first embodiment, a BID signal in which the slot number was converted into a binary number was used to distinguish each slot, but a code for selecting each slot was provided for each slot. You can also divide each slot into address spaces 1 to 11, f=j.

As is clear from the description of the embodiments of the invention, according to the present invention, there are changes, additions, and
1) In the case of a change or addition to the control method, there is no need to change the contents of the storage in the processor device. The programmer attached to the device can be used to control and test the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing device according to an embodiment of the present invention, in which (a) shows the details of the system bus, and (b) shows the details of the equipment configuration. Flowchart-1 showing the inspection operation, FIG. 3 shows the conventional example of block 18.
FIG. 4 is a VI-chart showing the inspection operation of the conventional example. 11... Addressing υ, 12... Data transmission, 13... ID5PACE signal, 14...
・・BID ninυ, 16・・・Other cisdeno・
Control the bus, 16...17.0. ,),
17... Second slot h, 18... Third slot, 19... Device connected to system bus, 101... ID information section, 102... ...I
D7'n-gram unit, 103... Device storage 1 stage, 21... System bus, 22... Processor device, 23... Main storage device, 24 ...
... Input/output control device, 25 ... Storage means in the processor device 22, 26 ... Central processing unit (CPU) of the processor device 22, 27 ... Main memory Storage means in the device 23, 28... Storage means in the input/output control device. Name of agent: Patent attorney Shigetaka Awano and 1 other person11
-11 Apnu New I2---Theta Maki No. 13--/DSPACE Fuku No. 14--EnoD Takira 5 15°-Tatadomari System Minami-Kai 1υnurturing leaf fA -°-
1st slot I7--2nd slot 21--System path--Main processing I by Computer diagram

Claims (2)

[Claims] (1) One or more processor devices having a central processing unit and an internal storage means storing at least a program necessary for controlling and inspecting the processor itself, and storing at least a program necessary for controlling and inspecting the processor itself. 1. An information processing device comprising one or more peripheral devices having internal storage means, and a system bus connecting the processor device and the peripheral devices. (2) Information processing according to claim 1, wherein when a processor device controls or inspects a peripheral device, the central processing unit of the processor device executes the program using a program stored in an internal storage means of the peripheral device. Device.