JPH0484492A - Soldering method for lsi package - Google Patents
Soldering method for lsi packageInfo
- Publication number
- JPH0484492A JPH0484492A JP20046890A JP20046890A JPH0484492A JP H0484492 A JPH0484492 A JP H0484492A JP 20046890 A JP20046890 A JP 20046890A JP 20046890 A JP20046890 A JP 20046890A JP H0484492 A JPH0484492 A JP H0484492A
- Authority
- JP
- Japan
- Prior art keywords
- lsi
- solder
- soldering
- package
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005476 soldering Methods 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims description 18
- 229910000679 solder Inorganic materials 0.000 claims abstract description 57
- 239000000919 ceramic Substances 0.000 claims abstract description 6
- 239000007787 solid Substances 0.000 claims description 3
- 230000007774 longterm Effects 0.000 abstract description 6
- 239000003292 glue Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ディジタル交換機等のＬ Ｓ Ｉ （ｌａｒ
ｇｅＳｃａｌｅ Ｉｎｔｅｇｒａｔｅｄ Ｃ４ｒｃｕｉ
ｔ）実装に使用されるＬＳＩパッケージのリードはんだ
付け方法に関し、特に高信頬性を有するＬＳＩパッケー
ジのはんだ付け方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to LSI (lar
geScale Integrated C4rcui
t) The present invention relates to a lead soldering method for an LSI package used for mounting, and particularly to a method for soldering an LSI package with high reliability.
従来のりフローはんだ付け方法では、ＬＳＩ搭載基板上
に設けられたはんだ接続用パッドに、はんだペーストの
印刷用メタルスクリーンを用いてはんだペーストを１回
スクリーン印刷した後、ＬＳＩを搭載してリフローはん
だ付けを行っていた。In the conventional glue flow soldering method, solder paste is screen printed once on the solder connection pads provided on the LSI mounting board using a metal screen for printing solder paste, and then the LSI is mounted and reflow soldering is performed. was going on.
上述した従来のりフローはんだ付け方法では、バットリ
ードＰＧＡ型ＬＳＩパッケージの端子の端子間隔が一般
に２．７７ｍｍ程度と狭く、端子直径も０．２ｍｍ程度
であり、ＬＳＩ搭載基板上に設けられたはんだ接続用パ
ッドの大きさも０．５〜０．７ｍｍ程度と小さいため、
１端子当りの接続はんだ量が非常に少なくなる。In the conventional glue flow soldering method described above, the terminal spacing of the terminals of the butt lead PGA type LSI package is generally narrow, about 2.77 mm, and the terminal diameter is about 0.2 mm. Because the size of the pad is small, about 0.5 to 0.7 mm,
The amount of connecting solder per terminal is extremely small.
また、バットリードＰＧＡ型ＬＳＩパッケージは、信鱈
性の点からセラミックが用いられることが多く、ＬＳＩ
の搭載基板は一般にガラスエポキシ等の合成樹脂が用い
られることが多い。その搭載基板がＬＳＩ端子先端のは
んだによりはんだ付けされた場合、両者の熱膨張係数の
違いにより周囲に温度変化が生じるため、はんだ接続部
に応力が発生する。そして、１端子当りの接続はんだ量
が少ない場合、その応力の緩和が十分に行われないため
、温度サイクル試験を実施すると、低サイクルではんだ
接続不良が発生する。In addition, ceramic is often used for butt-lead PGA type LSI packages from the viewpoint of reliability.
Generally, synthetic resin such as glass epoxy is often used for the mounting substrate. When the mounting board is soldered with the solder at the tip of the LSI terminal, a temperature change occurs in the surrounding area due to the difference in the coefficient of thermal expansion between the two, and stress is generated in the solder connection portion. When the amount of connecting solder per terminal is small, the stress is not sufficiently relaxed, and therefore, when a temperature cycle test is performed, solder connection failure occurs at low cycles.
さらにＡｕメツキされた端子を有するハントリーＦＰＧ
Ａ型ＬＳＩパッケージでは、はんだ付けの際に、硬い金
属間化合物ＡｕＳｎｘが端子表面とはんだ中のＳｎとの
間に発生し、はんだ量が少ない場合ＡｕＳｎχの濃度が
増してはんだ付け強度が著しく低下する。Huntly FPG with additional Au-plated terminals
In A-type LSI packages, during soldering, a hard intermetallic compound, AuSnx, is generated between the terminal surface and the Sn in the solder, and if the amount of solder is small, the concentration of AuSnχ increases, significantly reducing the soldering strength. .
従って、従来のりフローはんだ付け方法では、１端子当
りのはんだ量の不足により、はんだ接続の長期信頼性を
確保することが難しいという欠点があった。Therefore, the conventional glue flow soldering method has the disadvantage that it is difficult to ensure long-term reliability of solder connections due to the insufficient amount of solder per terminal.
本発明の目的は、この様な欠点を解消し、はんだ接続の
長期信頼性を確保できるＬＳＩパッケージのはんだ付け
方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for soldering LSI packages that can eliminate these drawbacks and ensure long-term reliability of solder connections.
本発明は、ＬＳＩパッケージの搭載基板上のはんだ接続
パッドにＬＳＩをリフローはんだ付けするＬＳＩパッケ
ージのはんだ付け方法において、前記はんだ接続パッド
にはんだ付けする前記ＬＳＩパッケージの１端子当りの
はんだ量を１０ Ｘ １０−２ｗ１ｉ以上とすることを
特徴とする。The present invention provides an LSI package soldering method in which an LSI is reflow soldered to a solder connection pad on a mounting board of an LSI package, in which the amount of solder per terminal of the LSI package to be soldered to the solder connection pad is 10X. It is characterized in that it is 10-2 w1i or more.
また本発明は、無垢のセラミック白基板上にはんだペー
ストをＬＳ）パッケージの端子に合わせてスクリーン印
刷し、ＬＳＩパッケージをはんだペースト上に搭載した
後、リフローはんだしてＬＳＩパッケージの端子に予備
はんだを行う工程を複数回繰り返し、ＬＳＩパッケージ
の端子に十分なはんだ量を与えた後、基板にＬＳＩパッ
ケージをリフローはんだ付けする。Furthermore, in the present invention, a solder paste is screen printed on a solid white ceramic substrate in accordance with the terminals of an LS package, and after the LSI package is mounted on the solder paste, reflow soldering is performed to apply preliminary solder to the terminals of the LSI package. After repeating this process multiple times to apply a sufficient amount of solder to the terminals of the LSI package, the LSI package is reflow soldered to the board.
更に本発明は、上記ＬＳＩパッケージがバットリードＰ
ＧＡ型ＬＳＩパッケージである。Furthermore, the present invention provides that the LSI package has a butt lead P.
It is a GA type LSI package.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は、本発明の一実施例を示すバットリーｒＰＧＡ
型ＬＳＩパッケージにおけるはんだ付け方法の実装フロ
ーチャート図であり、第２図は、実装フローチャート図
に従ってリフローはんだ付けをしたときのはんだ量によ
る断線数を示す図である。FIG. 1 shows a Batley rPGA showing one embodiment of the present invention.
FIG. 2 is a mounting flowchart of a soldering method in a type LSI package, and FIG. 2 is a diagram showing the number of wire breaks depending on the amount of solder when reflow soldering is performed according to the mounting flowchart.
第１図の実装フローチャート図に従って、直径０．２１
１１１１１ Ａ ｔＪメツキ厚７ｍｍ以下の端子を有す
るバットリードＰＧＡ型ＬＳＩパッケージのりフローは
んだ付け方法について説明する。According to the implementation flowchart diagram in Figure 1, the diameter is 0.21 mm.
11111 A tJ A glue flow soldering method for a butt lead PGA type LSI package having terminals with a plating thickness of 7 mm or less will be described.
最初に、無垢のセラミック白基板２上にはんだペースト
１をＬＳＩの端子に合わせてスクリーン印刷しくステッ
プＳＬ）、ＬＳＩをはんだペース上に搭載する（ステ・
７ブＳ２）。搭載後、はんだ接続パッドにリフローはん
だ付けしてＬＳＩの端子に予備はんだを行う。これを数
回繰り返し、ＬＳＩの端子に充分なはんだ量を与える。First, screen print solder paste 1 on a solid ceramic white substrate 2 to match the terminals of the LSI (Step SL), and mount the LSI on the solder paste (Step SL).
7buS2). After mounting, reflow soldering is performed on the solder connection pads and preliminary soldering is performed on the LSI terminals. Repeat this several times to apply a sufficient amount of solder to the LSI terminals.
このことにより、ＬＳＩ端子に充分な予備はんだを行う
。This provides sufficient preliminary soldering to the LSI terminals.
一方、回路基板３にはんだペースト１をスクリーン印刷
する（ステップ３４）。次に、予備はんだを行ったＬＳ
Ｉを、スクリーン印刷した回路基板上に搭載しくステッ
プＳ５）、再びリフローはんだ付けを行い（ステップＳ
６）、回路基板へのＬＳＩの実装を終了する。Meanwhile, the solder paste 1 is screen printed on the circuit board 3 (step 34). Next, the LS with preliminary soldering
I is mounted on the screen printed circuit board (Step S5), and reflow soldering is performed again (Step S5).
6) Finish mounting the LSI on the circuit board.
次に、第１図の実装フローチャート図に従って、ハツト
リードＰＣ，Ａ型ＬＳＩパッケージをリフローはんだ付
けした後、−６５°ＣＯ，５時間、常’／Ｍ ５分。Next, according to the mounting flowchart shown in FIG. 1, the hot lead PC and A-type LSI package were reflow soldered, and then heated at -65°C for 5 hours and at normal temperature for 5 minutes.
１２５°Ｃ０１５時間で４００サイクル実施した温度サ
イクル試験について、ＬＳＩＩ端子当りのはんだ量をパ
ラメータとしたときのはんだ量に対する断線数を第２図
に示す。第２図で示す様に、１端子当りのはんだ量を５
Ｘｌ０−２ｍｍ’では断線数が２本、それ以下だと増
加し、はんだ量を１０×１０−２１１１１１１３だと断
線数が１本以下となる。従って、ＬＳＩの１端子当りの
はんだ量は１０×１０−”ｓｕｎ”以上あれば実用上十
分なはんだ接続の長期信較性が得られることがわかる。Regarding the temperature cycle test carried out for 400 cycles at 125° C. for 15 hours, FIG. 2 shows the number of disconnections versus the amount of solder when the amount of solder per LSII terminal was used as a parameter. As shown in Figure 2, the amount of solder per terminal is 5
At Xl0-2 mm', the number of wire breaks is two, and if it is less than that, the number increases, and when the solder amount is 10×10-21111113, the number of wire breaks is one or less. Therefore, it can be seen that practically sufficient long-term reliability of solder connection can be obtained if the amount of solder per one terminal of the LSI is 10.times.10@-"sun" or more.
以上説明した様に、本発明のバットリードＰＧＡ型ＬＳ
Ｉパッケージのりフローはんだ付け方法は、ＬＳＩのり
フローはんだ付けにおけるＬＳＩの１端子当りのはんだ
量という概念を導入し、実験的に求めた値である１端子
当り１０ Ｘ １０− ”ｍｍ３以上のはんだにより、
ＬＳＩを搭載基板上のはんだ接続パッドにリフローはん
だ付けする方法である。As explained above, the butt lead PGA type LS of the present invention
The I-package glue flow soldering method introduces the concept of the amount of solder per LSI terminal in LSI glue flow soldering, and uses more than 10 x 10-"mm3 of solder per terminal, which is an experimentally determined value. ,
This is a method of reflow soldering an LSI to solder connection pads on a mounting board.
〔発明の効果］
以上説明したように本発明は、ハツトリードＰＧＡ型Ｌ
ＳＩパッケージのりフローはんだ付けにおいて、ＬＳＩ
の１端子当りのはんだ量という概念を導入し、１端子当
り１０×１０−”ｍｍ３以上のはんだ量にてＬＳＩをは
んだ付けすることにより、ＬＳＩのはんだ接続の長期信
転性が確保できるという効果がある。[Effects of the Invention] As explained above, the present invention has the following advantages:
In SI package glue flow soldering, LSI
Introducing the concept of the amount of solder per terminal, and by soldering LSI with a solder amount of 10 x 10-"mm3 or more per terminal, the long-term reliability of LSI solder connections can be ensured. There is.
第１図は、本発明の一実施例を示す実装フローチャート
図、
第２図は、第１図の実装フローチャート図に従ってリフ
ローはんだ付けをしたときのはんだ量による断線数を示
す図である。
１・・・・・はんだペースト
２・・・・・セラミック白基板
３・・・・・回路基板FIG. 1 is a mounting flowchart showing an embodiment of the present invention, and FIG. 2 is a diagram showing the number of disconnections depending on the amount of solder when reflow soldering is performed according to the mounting flowchart of FIG. 1. 1...Solder paste 2...Ceramic white board 3...Circuit board
Claims (3)
ドにＬＳＩをリフローはんだ付けするＬＳＩパッケージ
のはんだ付け方法において、 前記はんだ接続パッドにはんだ付けする前記ＬＳＩパッ
ケージの１端子当りのはんだ量を１０×１０＾−＾２ｍ
ｍ＾３以上とすることを特徴とするＬＳＩパッケージの
はんだ付け方法。(1) In the LSI package soldering method in which the LSI is reflow soldered to the solder connection pads on the mounting board of the LSI package, the amount of solder per terminal of the LSI package to be soldered to the solder connection pads is 10 x 10. ^-^2m
A method for soldering an LSI package, characterized in that it is m^3 or more.
ＳＩパッケージの端子に合わせてスクリーン印刷し、Ｌ
ＳＩパッケージをはんだペースト上に搭載した後、リフ
ローはんだしてＬＳＩパッケージの端子に予備はんだを
行う工程を複数回繰り返し、ＬＳＩパッケージの端子に
十分なはんだ量を与えた後、基板にＬＳＩパッケージを
リフローはんだ付けする請求項１記載のＬＳＩパッケー
ジのはんだ付け方法。(2) Apply solder paste on a solid ceramic white board.
Screen print to match the terminals of the SI package, and
After mounting the SI package on the solder paste, repeat the process of reflow soldering and pre-soldering the terminals of the LSI package several times, and after applying a sufficient amount of solder to the terminals of the LSI package, reflow solder the LSI package to the board. 2. The method of soldering an LSI package according to claim 1, wherein the LSI package is soldered.
パッケージである請求項１または２記載のＬＳＩパッケ
ージのはんだ付け方法。(3) LSI package is butt lead PGA type LSI
The method for soldering an LSI package according to claim 1 or 2, which is a package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2200468A JP2527085B2 (en) | 1990-07-27 | 1990-07-27 | Soldering method for butt lead PGA type LSI package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2200468A JP2527085B2 (en) | 1990-07-27 | 1990-07-27 | Soldering method for butt lead PGA type LSI package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0484492A true JPH0484492A (en) | 1992-03-17 |
| JP2527085B2 JP2527085B2 (en) | 1996-08-21 |
Family
ID=16424821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2200468A Expired - Fee Related JP2527085B2 (en) | 1990-07-27 | 1990-07-27 | Soldering method for butt lead PGA type LSI package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2527085B2 (en) |
-
1990
- 1990-07-27 JP JP2200468A patent/JP2527085B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2527085B2 (en) | 1996-08-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |