JPH04825A - Very high speed separating circuit system - Google Patents

Abstract

PURPOSE:To normally separate respective low-speed data by inputting the low- speed data separated from a received multiple data to a synchronizing detection part, controlling a matrix part by a control part when synchronizing the data, and outputting the respective low-speed data while connecting the data to a designated low-speed channel. CONSTITUTION:In a very high speed separator 2A, the multiple data is received, separated in the ratio 1:16 by a serial/parallel conversion part 10 and inputted to a shift register part 20. A synchronizing detection part 30 detects synchronizing in the low-speed data to be inputted corresponding to a channel CH1 and when synchronizing cannot be detected, the shift register part 20 shifts the data by every one bit until detecting synchronizing. Then, the synchronizing detection is executed at the arbitrary CH. When synchronizing is established, the synchronizing detection part 30 transmits a shift stop signal to the shift register circuit 20 and stops the shift. Simultaneously, a control part 40 connects the respective low-speed data while shifting them for every 4CH. Thus, the low-speed data can be outputted to designated low-speed channels R2, R5 and R10.

Description

[Detailed description of the invention] [Summary] After inserting a frame synchronization signal, inserting a channel identification number, and converting to BSI for each low-speed data on the transmitting side,
Regarding the ultra-high-speed separation circuit method, which performs ultra-high-speed multiplexing processing and transmits the data, and then separates the ultra-high-speed multiplexed data into low-speed data on the receiving side, even if there is a gap in the low-speed channel being transmitted, it will not work properly. The purpose is to provide an ultra-high-speed separation circuit system that can perform multiplexing and demultiplexing.The received multiplexed data is separated into low-speed data by a serial/parallel converter, inputted to a shift register, and then outputted as low-speed data. Data is input to the synchronization detection section, synchronous loading is performed, and when synchronization cannot be achieved, synchronization detection of the data to be shifted at a predetermined timing is performed sequentially, and when synchronization is achieved, the shifting of the shift register section is stopped. , according to the channel identification number of the synchronized low-speed data,
The control section controls the matrix section and is configured to connect each low-speed data to a designated low-speed channel and output it.

[Industrial Application Field] The present invention inserts a frame synchronization signal, inserts a channel identification number (hereinafter referred to as CHID), and converts it into a BSI for each low-speed data on the transmitting side, and then performs ultra-high-speed multiplexing. This invention relates to an ultra-high-speed separation circuit system that processes and transmits data, and separates ultra-high-speed multiplexed data into low-speed data on the receiving side.

FIG. 3 is a diagram illustrating a digital multiplex communication system. On the transmitting side, low-speed data of channels (hereinafter referred to as CH) 1 to CHn are multiplexed by an ultra-high-speed multiplexer 1 and sent to a transmission path.

In the ultrahigh-speed separation device 2, the data input from the transmission line is
By separating the CH low-speed data and outputting it to low-speed CH1~CHn, the corresponding CHI comrades,~CHn
Comrades communicate with each other.

In such digital multiplexed ultra-high-speed communication, low-speed data is further multiplexed with lower-order group data, and the low-speed data has a frame synchronization signal for multiplexing and separating the lower-order group data. ing.

If a frame synchronization signal is inserted after multiplexing such low-speed data, the amount of data will increase accordingly.

Therefore, in order not to increase the amount of data, frame synchronization signals are not inserted after multiplexing, and BSI conversion (Bit
5equence Independence
(e), methods that only use low-speed data are being widely adopted.

The ultrahigh-speed separation circuit used in such a digital multiplex communication system is required to be able to properly synchronize low-speed data after separation even if there is a gap in the transmission channel.

[Conventional technology] FIG. 4 shows a block diagram illustrating a conventional example.

The conventional ultra-high-speed separation device 2B shown in FIG. 4 is a serial/
Parallel converter 0 and serial/parallel converter 10
a synchronization detecting unit 30 that detects synchronization of low-speed data corresponding to CHI outputted from the above, and detects its CHID, and when the synchronization detecting unit 30 detects synchronization of low-speed data corresponding to CHI, detects the CHID, A control unit 40 outputs a control signal so that each low-speed data is output to the low-speed channels R1 to Rn corresponding to the number; This example includes a matrix unit 50 that connects data to designated low-speed channels R1 to Rn, and low-speed channels R1 to Rn that output low-speed data.

In the above configuration, the synchronization detection unit 30
CHI of low-speed data output from the parallel converter 10
Synchronize low-speed data equivalent to . The control unit 40 controls the matrix unit 50 so that the CHID of the synchronized low-speed data is detected and each low-speed data is output to the low-speed channels R1 to Rn corresponding to the number.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

[Problem to be solved by the invention]

In the conventional example shown in FIG. 4 described above, synchronization is achieved using low-speed data corresponding to CHI, but it is not determined what low-speed data is first input to the synchronization detection section 30.

Therefore, even if there is a gap in the implementation, synchronization can be detected when the low-speed data of the implemented channel is input to the synchronization detection unit 50, but when the low-speed data of the unimplemented channel is input to the synchronization detection unit 50, synchronization can be detected. Sometimes, the synchronization detection section 50 attempts to synchronize using this low-speed data, but since no synchronization signal is included, synchronization will never be achieved.

SUMMARY OF THE INVENTION An object of the present invention is to provide an ultrahigh-speed demultiplexing circuit system that can perform normal multiplexing and demultiplexing even if there are gaps in the low-speed channels to be transmitted.

It is a serial/parallel converter that separates high speed data.
20 is a shift register section that shifts low-speed data output from the serial/parallel converter 10 until synchronization is established.

Further, 30 is a synchronization detection section that synchronizes with low-speed data output from the shift register section 20, and 40 is a synchronization detection section 3.
When synchronization is detected with 0, C of low-speed data detected in synchronization.
Identify HID and low speed CHR1~R corresponding to CHID
50 is a control unit that outputs a control signal to be output to a designated low-speed channel R, and 50 is a control unit that outputs a control signal to be output to a designated low-speed channel R.
1 to Rn, inputs the low-speed data obtained by separating the received multiplexed data by the serial/parallel converter 10 to the shift register unit 20, and inputs the output to the synchronization detector 30 for synchronization. When synchronization cannot be achieved, the synchronization of data shifted at a predetermined timing is sequentially detected, and when synchronization is achieved, the shifting of the shift register unit 20 is stopped, and control is performed using the CHID of the synchronized low-speed data. The unit 40 controls the connection of the matrix unit 50 and connects and outputs each low-speed data to designated low-speed channels R1 to Rn, thereby solving this problem.

[For production]

The received multiplexed data is separated into low-speed data by the serial/parallel converter 10, and is input to the synchronization detector 30 via the shift register part 20 to detect synchronization.

If synchronization cannot be detected with the low-speed data initially input to the synchronization detection unit 30, the low-speed data input to the synchronization detection unit 30 is shifted one bit at a time by the shift register unit 20, and synchronization is detected with arbitrary low-speed data. do.

When synchronization is achieved, the synchronization detection unit 30 sends a shift stop signal to the shift register unit 20 to stop shifting, and also controls the control unit to check the CHID of the low-speed data and output it to the corresponding low-speed channel. At step 40, the connection of the matrix section 50 is controlled to connect and output each low-speed data to the designated low-speed channels R1 to Rn, thereby making it possible to normally separate each low-speed data.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a block diagram illustrating the invention in detail.

The embodiment of the present invention shown in FIG. 2 is an example of a 16CH ultra-high-speed multiple bag W1 and an ultra-high-speed separation device 2A.

The ultra high speed multiplexer 1 has low speed channels S2, S5.3.
10 is connected, and the ultra high-speed separation device 2A is connected to the serial/parallel converter 10.
, shift register section 20, synchronization detection section 30, control section 40
and a matrix section 50, to which low-speed channels R2, R5, and R10 are connected.

In the above configuration, the low-speed data of CH2, CH5, and CHIO are multiplexed at a ratio of 16:1 and then sent to the transmission path.

The ultrahigh-speed separation device 2A receives multiplexed data from the transmission line, separates it at 1:16 in the serial/parallel converter 10, and inputs it to the shift register 20.

The synchronization detection unit 30 detects synchronization using input low-speed data equivalent to CHI, and when synchronization cannot be detected, shifts bit by bit until synchronization can be detected in the shift register unit 20, and detects synchronization on any CH. conduct.

For example, if low-speed data of CH3 is first input to the synchronization detection unit 30, since CH3 is not implemented,
Can't get out of sync. Therefore, the shift register section 20 shifts by one bit and inputs the low-speed data of CH4 to the synchronization detection section 30. Here again, since CH4 is not mounted, synchronization cannot be achieved, and the shift register section 20 further shifts by one bit and inputs the low-speed data of CH5 to the synchronization detection section 30.

Since CH5 is installed, it is assumed that synchronization detection is possible on CH5 and synchronization is established.

When synchronization is established, the synchronization detection section 30 detects the shift register section 2.
0 to stop the shift, the control unit 40 sends a shift stop signal to
By instructing the matrix unit 50 that D is CH5 and connecting each low-speed data with a shift of 4 CH, the low-speed data is connected to the designated low-speed channels R2 and R5.
, R10.

In the figure, low speed channels S2, S5.310, R2, R5
, a plurality of arrows inputting and outputting to and from RIO indicate that the low-speed data is composed of a plurality of data of a lower order group.

The synchronization detection unit 30 also has a synchronization protection function,
When out-of-synchronization occurs, synchronization is detected again on an arbitrary channel, and the ultra-high-speed multiplexed data is separated using the above-described procedure and output as low-speed data.

Since the synchronization protection function is a well-known technology, it will not be described here.

Furthermore, it goes without saying that the connection operation by the matrix section 50 can also be performed by a bit shift operation.

With the above configuration, even if there is a gap in the transmission channel, it is possible to synchronize low-speed data after normal separation.

[Effects of the Invention] According to the present invention as described above, even if there is a gap in the transmission channel, synchronization detection is performed on any channel, and low-speed data is transferred to the designated channel based on the CHID of the channel for which synchronization was detected. It is possible to provide an ultra-high-speed separation circuit system that correctly outputs to low-speed channels.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a digital multiplex communication system, and FIG. 4 is a diagram explaining a conventional example. Block diagrams are shown respectively. In the figure, ■ is an ultra-high-speed multiplexer, 2.2A and 2B are ultra-high-speed separators, 10 is a serial/parallel conversion section, 20 is a shift register section, 30 is a synchronization detection section, 40 is a control section, and 50 is a matrix section , S1 to Sn, and R1 to Rn indicate low speed channels, respectively. FIG. 3 is a block diagram explaining the present invention in detail. FIG.

Claims (1)

[Claims] After inserting a frame synchronization signal, inserting a channel identification number, and BSI conversion (suppressing consecutive zero codes) for each low-speed data on the transmitting side, ultra-high-speed multiplexing processing is performed. On the receiving side, a serial/parallel converter (10 ), a shift register section (20) that shifts the low-speed data output from the serial/parallel conversion section (10) until synchronization is established, and one of the low-speed data output from the shift register section (20). When synchronization is detected by the synchronization detection unit (30), the synchronization detection unit (30) identifies the channel identification number of the synchronized low-speed data and selects the low-speed channel (R1 to R1) corresponding to the channel identification number. a control section (40) that outputs a control signal to be outputted to a designated low-speed channel (R1 to Rn), the received multiplexed data is separated into low-speed data by the serial/parallel converter (10), inputted to the shift register part (20), and outputted. Low-speed data is input to the synchronization detection section (30), synchronization detection is performed, and when synchronization cannot be achieved, synchronization detection of the data shifted at a predetermined timing is performed sequentially, and when synchronization is achieved, the shift register section (30) performs synchronization detection. 20), and the control unit (40) controls the matrix unit (50) based on the channel identification number of the synchronized low-speed data, so that each low-speed data is assigned to a designated low-speed channel (R1 to R1). An ultra-high-speed separation circuit system characterized by connecting to Rn) and outputting it.