JP2000151540A - Device and method for detecting apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a circuit configuration by inserting a test pattern generat ed on the basis of a frame timing signal for every frame of an STM-N (synchronous transport module-N) into plural RSOHs separated from a main signal of a received STM-N, separating the test pattern in the main signal after signal processing such as separation multiplexing of the MSOH is performed and detecting an error of the test pattern. SOLUTION: An RSOH separation circuit 1 separates each RSOH(regenerator section overhead) from a main signal of an STM-N, detects an error of a repeater section by a B1 bite of a part of the RSOH and generates a frame timing signal every frame. A test pattern multiplex circuit 2 multiplies the test pattern which a test pattern circuit 6 generates on the basis of the frame timing signal to a time slot of the B1 bite and a signal processing circuit 3 performs signal processing such as separation multiplexing of the MSOH (multiplex section overhead) or the like. A test pattern separation circuit 4 separates a test pattern from a main signal and a test pattern detection circuit 7 detects an error of the test pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SDH (Synchronous
ous Digital Hierarchy) and STM-N (Syn
The present invention relates to a device failure detection device for detecting a device failure in a digital communication system that transmits a chronous Transport Module-N) signal, and a method of detecting the device failure.

[0002]

2. Description of the Related Art In a digital communication system for transmitting an STM-N signal specified by the SDH, if an equipment failure occurs during signal processing, it is necessary to detect the equipment failure and send an alarm. .

FIG. 3 is a block diagram showing an example of a conventional device failure detecting device for detecting such a device failure. That is, the received STM-N main signal is RS
After the separation of each RSOH in the OH (Regenerator Section Overhead) separation circuit 1, the parity of the main signal is calculated in the parity calculation circuit 8. The operation result is sent to the signal processing circuit 9 separately from the main signal as a parity signal.

The signal processing circuit 9 includes a parity operation circuit 8
MSOH (Multiplex Section Overhea)
After performing the demultiplexing and multiplexing of d), the parity recalculation of the main signal according to the change in the content of the MSOH is performed. The result of the parity recalculation is sent to the parity detection circuit 10 as a parity signal separately from the main signal. The parity detection circuit 10 performs parity detection based on the content of the parity signal and the parity result of the main signal to detect a failure of the device.
At the same time, the RSOH multiplexing circuit 5 multiplexes and outputs the parity operation result for monitoring the relay section error and each RSOH.

[0005]

However, in the above-described conventional equipment failure detecting apparatus, in order to detect a failure of the equipment, the apparatus is provided between the parity operation circuit 8 and the signal processing circuit 9 and between the parity detection circuit 10 and the signal processing circuit. It is necessary to provide a parity signal transfer interface with the circuit 9. In the course of signal processing by the signal processing circuit 9, the parity must be recalculated. Because of this, an interface circuit, a circuit for recalculating the parity, and the like are required, which hinders simplification of the circuit.

[0006] The present invention has been made in view of such a situation, and is based on a Synchronous Digital Hierarchy (SDH).
y), the STM-N (Synchronous Transport M
odule-N) It is an object of the present invention to provide a device failure detection device and a detection method thereof that can simplify a circuit configuration for detecting a device failure in a digital communication system that transmits a signal.

[0007]

According to a first aspect of the present invention, there is provided an apparatus for detecting an equipment failure, comprising receiving a received STM-N (Synchronous Transcript).
sport Module-N) Multiple RSOH included in the main signal
(Regenerator SectionOverhead), and performs error detection on the relay section inserted in the B1 byte that is a part of each RSOH.
RSOH separation means for generating a frame timing signal for each frame of TM-N, and a test pattern based on the frame timing signal from the RSOH separation means,
A test pattern insertion unit to be inserted into each of the separated RSOHs and a main signal in which the test pattern from the test pattern multiplexing unit is multiplexed are subjected to MSOH (Multiplex Sequential).
ctionOverhead), a signal processing unit for performing signal processing such as separation multiplexing, an error detection unit for separating a test pattern in a main signal from the signal processing unit and detecting an error in the separated test pattern, and a test pattern separation unit And RSOH multiplexing means for multiplexing the respective RSOHs with the main signal from the RS and multiplexing the parity operation result for monitoring the relay section error in the B1 byte of each RSOH and transmitting the result as an STM-N signal. I do.
Further, the test pattern inserting means includes a test pattern generating means for generating a test pattern inverted for each frame based on a frame timing signal from the RSOH separating means, and a test pattern from the test pattern generating means.
Test pattern multiplexing means for inserting into the B1 byte time slot of each RSOH separated by the OH separation circuit. Further, the error detecting means detects the error of the separated test pattern by detecting the error of the separated test pattern from the test pattern separating means for separating the test pattern from the B1 byte time slot of each RSOH in the main signal from the signal processing means. In some cases, a test pattern detecting means for judging that a device failure has occurred and transmitting an alarm can be provided. The device failure detection method according to claim 4, wherein the received STM-N (Synchr
In addition to separating a plurality of RSOHs (Regenerator Section Overheads) included in the main signal of the onous Transport Module-N, an error of the relay section inserted in the B1 byte which is a part of each RSOH is detected, and further, an STM- A first step of generating a frame timing signal for each frame of N, and a test pattern generated based on the frame timing signal, and each of the separated R
The second step of insertion into the SOH and the MSOH (Multiplex Section Ove)
rhead) for performing signal processing such as separation and multiplexing,
A fourth step of separating the test pattern in the main signal and detecting an error in the separated test pattern, multiplexing each RSOH with the main signal,
A fifth step of multiplexing a parity operation result for monitoring a relay section error in the B1 byte of the SOH and transmitting the result as an STM-N signal. Further, the second step includes a step of generating a test pattern inverted for each frame based on the frame timing signal, and inserting the test pattern into the separated B1 byte time slot of each RSOH. And the step of performing In the fourth step, a test pattern is separated from the B1 byte time slot of each RSOH in the main signal, and an error of the separated test pattern is detected. Determining that there is an alarm and sending an alarm. In the device failure detection device and the detection method according to the present invention, the received STM-N (Synchr
It separates multiple RSOH (Regenerator Section Overhead) included in the main signal of the onous Transport Module-N, generates a frame timing signal for each frame, and generates a test pattern based on the frame timing signal. Insert into each separated RSOH,
The test pattern in the main signal after signal processing such as separation and multiplexing of MSOH (Multiplex Section Overhead) is performed is separated to detect an error in the test pattern.

[0008]

Embodiments of the present invention will be described below. In the drawings described below, portions common to FIG. 3 are denoted by the same reference numerals.

FIG. 1 is a block diagram showing an embodiment of the equipment failure detection device of the present invention, and FIG. 2 is a timing chart for explaining the operation of the equipment failure detection device of FIG.

[0010] In FIG.
OH (Regenerator Section Overhead) separation circuit 1, test pattern multiplexing circuit 2, signal processing circuit 3, test pattern separation circuit 4, RSOH (Regenerator Section Overhea)
d) A multiplexing circuit 5, a test pattern generation circuit 6, and a test pattern detection circuit 7 are provided.

The RSOH separation circuit 1 receives the received STM-
N (Synchronous Transport Module-N), each RSOH included in the main signal is separated,
The error detection of the relay section is performed by the B1 byte which is a part of H. The test pattern multiplexing circuit 2 inserts a test pattern into each B1 byte time slot.
The signal processing circuit 3 performs signal processing such as separation and multiplexing of MSOH (Multiplex Section Overhead) on the main signal into which the test pattern has been inserted. The test pattern separation circuit 4 separates a test pattern from the input main signal.

The RSOH multiplexing circuit 5 multiplexes the output main signal of the test pattern separation circuit 4 with the parity operation result for monitoring the error of the relay section by B1 and each RSOH and outputs the result. The test pattern generation circuit 6 uses the STM-N
A test pattern inverted so as to take both 0 and 1 states is generated for each frame. The test pattern detection circuit 7
Detects the presence or absence of a failure in the equipment failure monitoring section.

The device failure detecting device having such a configuration performs the following operation. First, the RSOH separation circuit 1 separates each RSOH signal from the input STM-N signal, and detects an error in the relay section due to the B1 byte that is a part of the RSOH. Further, the RSOH separation circuit 1 generates a frame timing signal for each frame and sends it to the test pattern generation circuit 6. The test pattern generation circuit 6 generates an inverted test pattern for each frame based on the input frame timing signal, and sends the inverted test pattern to the test pattern multiplexing circuit 2. The test pattern multiplexing circuit 2 converts the input test pattern into each B
The signal is multiplexed into a 1-byte time slot and sent to the signal processing circuit 3. The signal processing circuit 3 performs signal processing such as MSOH separation and multiplexing, and outputs a main signal to the test pattern detection circuit 4.

The test pattern detection circuit 4 separates the test pattern from the input main signal and outputs the separated test pattern and frame timing signal to the test pattern detection circuit 7.
To send to. Further, the test pattern detection circuit 4 sends the main signal to the RSOH multiplexing circuit 5. The test pattern detection circuit 7 detects an inverted test pattern for each frame, and if the test pattern is incorrect, determines that a device failure has occurred and sends an alarm. RSOH multiplexing circuit 5
Indicates that each RSOH besides the B1 byte for detecting a transmission line error
Is transmitted.

Next, a specific operation of the device failure detection apparatus according to the present embodiment will be described with reference to the timing chart of FIG. Here, the main signal STM-N (Sync
An example will be described in which a hronous Transport Module-N) signal is converted into eight columns.

That is, the input main signals of eight columns are R
The SOH separation circuit 1 establishes frame synchronization. Next, a frame timing signal indicating the beginning of the STM-N frame is sent to the test pattern generation circuit 6. When separating each RSOH, the RSOH separation circuit 1 detects an error in the relay section due to the B1 byte that is a part of the RSOH. The test pattern generation circuit 6 calculates R
Based on the frame timing signal from the SOH separation circuit 1, the test pattern is inverted for each frame and transmitted to the test pattern multiplexing circuit 2.

Here, at time t1, "110010"
Assuming that the pattern “10” is generated, at time t2, the inverted pattern “001110101” is generated.After time t3, “11001” is generated.
010 "and" 00110101 "are repeatedly generated.

The test pattern multiplexing circuit 2 inserts the test pattern from the test pattern generation circuit 6 into a B1 byte time slot. Thereby, B of each main signal data sequence
A pattern that changes between 0 and 1 is inserted into a 1-byte time slot.

Since the B1 byte has been converted into eight columns, one bit is assigned to each column. Signal processing circuit 3
Performs signal processing such as MSOH separation and multiplexing on the main signal to which the test pattern from the test pattern multiplexing circuit 2 has been multiplexed, and sends it to the test pattern separation circuit 4.

The test pattern separation circuit 4 separates the test pattern from the B1 byte time slot and sends it to the test pattern detection circuit 7 together with the frame timing signal. The test pattern detection circuit 7 detects whether or not the test pattern separated from the test pattern separation circuit 4 is incorrect. If there is an error, it is determined that a device failure has occurred, and an alarm is transmitted. The RSOH multiplexing circuit 5 multiplexes each RSOH with the main signal from the test pattern separation circuit 4, multiplexes a parity operation result for monitoring a relay section error into the B1 byte, and transmits the result as an STM-N signal.

As described above, in the present embodiment, a plurality of RSOHs (Regenerator Section Ovs) included in the received STM-N (Synchronous Transport Module-N) main signal.
erhead), generates a frame timing signal for each frame, generates a test pattern based on the frame timing signal, inserts the test pattern into each of the separated RSOHs, and generates an MSOH (Multiplex Section Over).
The test pattern in the main signal after signal processing such as separation / multiplexing of the head is performed is separated to detect an error in the test pattern. Therefore, even in a case where insertion of a test pattern of one time slot per frame is limited, insertion of an inverted test pattern of a previous frame over a plurality of frames eliminates the need to provide a large number of time slots for device failure detection. Since a device failure can be detected, the detection circuit configuration can be simplified.

In the present embodiment, B of STM-N
The case where a test pattern is inserted into one byte has been described. However, the present invention is not limited to this example, and it is also possible to insert a test pattern into an unused one-byte portion of each RSOH.

[0023]

As described above, according to the device failure detection apparatus and the method for detecting the same according to the present invention, the received STM-N (Sy
A plurality of RSOHs (Regenerator Section Overheads) included in the main signal of the nchronous Transport Module-N are separated, a frame timing signal for each frame is generated, and a test pattern is generated based on the frame timing signal. Since the test pattern in the main signal after signal processing such as separation and multiplexing of MSOH (Multiplex Section Overhead) is performed is inserted into each of the separated RSOHs, and a test pattern error is detected. STM-N (Synchronous Transport Module-N) defined by SDH (Synchronous Digital Hierarchy)
A circuit configuration for detecting a failure of a device in a digital communication system for transmitting a signal can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a device failure detection device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the device failure detection device of FIG.

FIG. 3 is a block diagram illustrating an example of a conventional device failure detection device.

[Explanation of symbols]

Reference Signs List 1 RSOH (Regenerator Section Overhead) separation circuit 2 Test pattern multiplexing circuit 3 Signal processing circuit 4 Test pattern separation circuit 5 RSOH (Regenerator Section Overhead) multiplexing circuit 6 Test pattern generation circuit 7 Test pattern detection circuit

Claims (6)

[Claims] The received STM-N (Synchronous Tran
sport Module-N) Multiple RSOH included in the main signal
(Regenerator Section Overhead), an RSOH that detects an error in a relay section inserted in the B1 byte that is a part of each RSOH, and further generates a frame timing signal for each frame of the STM-N. Separating means, a test pattern inserting means for generating a test pattern based on a frame timing signal from the RSOH separating means and inserting the test pattern into each of the separated RSOHs, and a test pattern from the test pattern multiplexing means. The MSOH (Multiplex Section Ov)
signal processing means for performing signal processing such as separation and multiplexing of erhead); an error detection means for separating a test pattern in a main signal from the signal processing means and detecting an error in the separated test pattern; The respective RSOHs are multiplexed on the main signal from the separating means, and the respective RSOs are
RS that multiplexes the parity operation result for relay section error monitoring into the B1 byte of H and transmits the result as an STM-N signal
An apparatus failure detection device comprising: an OH multiplexing unit. 2. The test pattern insertion unit, comprising: a test pattern generation unit configured to generate a test pattern inverted for each frame based on a frame timing signal from the RSOH separation unit; From the respective RSOs separated by the RSOH separation circuit.
2. The apparatus failure detecting apparatus according to claim 1, further comprising: a test pattern multiplexing unit that inserts the test pattern into a time slot of B1 byte of H. 3. The method according to claim 2, wherein the error detecting means includes a RSOH in the main signal from the signal processing means.
Test pattern separating means for separating a test pattern from a B1 byte time slot, detecting an error in the separated test pattern, and when there is an error, judging that a device failure has occurred and sending an alarm, and detecting an error. The device fault detecting device according to claim 1, further comprising means. 4. The received STM-N (Synchronous Tran
sport Module-N) Multiple RSOH included in the main signal
(Regenerator Section Overhead), an error detection of the relay section inserted in the B1 byte which is a part of each RSOH, and a frame timing signal for each frame of the STM-N. A second step of generating a test pattern based on the frame timing signal and inserting the test pattern into each of the separated RSOHs; and an MSO for the main signal on which the test pattern is multiplexed.
A third step of performing signal processing such as separation multiplexing of H (Multiplex Section Overhead), a fourth step of separating a test pattern in the main signal and detecting an error in the separated test pattern; A signal is multiplexed with the respective RSOHs, and a parity operation result for relay section error monitoring is multiplexed into the B1 byte of the respective RSOHs, and the STM-
And a fifth step of transmitting as an N signal. 5. The method according to claim 5, wherein the second step includes: generating a test pattern inverted for each frame based on the frame timing signal;
5. The method according to claim 4, further comprising the step of: inserting in a time slot of B1 byte of H. 6. The fourth step includes: separating a test pattern from a B1 byte time slot of each RSOH in the main signal; detecting an error in the separated test pattern; 5. The method according to claim 4, further comprising a step of determining that a device failure has occurred and sending an alarm.