JPH0481947A - Method and device for controlling buffer storage - Google Patents

Abstract

PURPOSE:To avoid the overhead of an address conversion buffer mechanism by accessing an address array and a buffer storage device by a physical address obtained by the previous address conversion. CONSTITUTION:A buffer storage device (BS) address, and an address array (AA) are constituted of a physical address 27 read out of a displacement field 26 and an address conversion buffer mechanism (TLB) 21. In such a state, the overhead of the TLB 21 is avoided by accessing the AA 22 and the BS 23 by the physical address obtained by the previous address conversion without accessing them by the physical address 27 read out of the TLB 21. In such a way, the overhead of the address conversion buffer mechanism to an access time of a buffer storage device can be avoided.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method and apparatus for controlling a buffer storage device having a capacity exceeding a page size in a virtual storage system, and in particular to a method for controlling a buffer storage device having a capacity exceeding a page size, and in particular to a method for controlling a buffer storage device having a capacity exceeding a page size. The present invention relates to a buffer storage control method that makes it possible to avoid the overhead of referencing an address translation buffer mechanism, and a device therefor.

[Prior Art] Conventionally, in a virtual memory system, in order to speed up access to a buffer storage device, a displacement field (real address part) of a logical address is used as a reference address of the buffer storage device, and an address translation buffer is used. A method was adopted in which it operated in parallel with the mechanism. However, in this case, there is a limitation that the capacity of the buffer storage device is less than the page size.

On the other hand, for buffer storage devices whose capacity exceeds the page size, methods have been taken to reduce the overhead of accessing the buffer storage device by increasing the speed of the address translation buffer mechanism.

Regarding the control method of the buffer storage device when the page size is made variable, for example, Japanese Patent Publication No. 60-499
A technique disclosed in Japanese Patent No. 44 is known. This technique shows a method of modifying the address of a buffer storage device with the most significant physical address read from an address translation buffer mechanism to avoid degeneration of the buffer storage device.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into consideration the point of avoiding the overhead of address translation buffer mechanism access corresponding to the buffer storage device access when the capacity of the buffer storage device exceeds the page size. This had the problem of causing performance deterioration.

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the conventional technology, and to access the buffer storage device in parallel with the address translation buffer mechanism. It is an object of the present invention to provide a buffer storage control method and a device for the same, which make it possible to avoid the overhead of an address translation buffer mechanism with respect to the access time of a buffer storage device.

[Means to solve the problem]

The above object of the present invention is to provide an address conversion function for converting a logical address into a physical address, an address conversion buffer mechanism for associating a physical address from a logical address, a buffer storage device for holding a part of data in a main storage device, and an address conversion function for converting a logical address into a physical address; In a virtual storage system having an address array that maintains the correspondence between the main storage device and the buffer storage device, a part of the physical address obtained in the previous address translation is retained, and the retained contents and the current address translation buffer are A buffer storage control method, or the above-mentioned virtual storage system, characterized in that the content of the buffer storage is compared with the contents of the memory, and the hit determination of the address array and the access timing of the buffer storage device are changed based on the result of the comparison. means for holding a part of the physical address obtained in the previous address translation; and means for comparing the contents held in the holding means with the contents of the current address translation buffer mechanism;
This is achieved by a buffer storage control device characterized in that it is provided with means for changing the hit determination of the address array and the access timing of the buffer storage device based on the comparison result by the comparison means.

[Effect]

In the buffer storage control method and device according to the present invention,
The conversion itself from a logical address to a physical address is performed using the well-known method of searching the segment table from the segment field and the page table from the segment table entry and page field to obtain the physical address from the page table entry. do. Here, the address translation buffer mechanism is an associative memory for reading physical addresses from logical addresses that holds a portion of a copy of a page table entry, and the address array and buffer storage address are the displacement fields of the logical addresses. with the displacement field of the physical address and address translation buffer mechanism equal to the bit width exceeding
Access address arrays and buffer storage.

As mentioned above, in the conventional method, the physical address read from the address translation buffer mechanism is always used here, so the access to the address translation buffer mechanism becomes an overhead of the access to the address array and the buffer storage device. Ta. In contrast, in the buffer storage control method according to the present invention, the address array and the buffer storage device are not accessed using the physical address read from the address translation buffer mechanism, but using the physical address obtained from the previous address translation. This allows access using physical addresses and avoids the overhead of an address translation buffer mechanism.

That is, a portion of the physical address obtained in the previous address translation held in the holding means is compared with the contents of the current address translation buffer mechanism, and based on the result of this comparison, the address array is By changing the hit determination and the access timing of the buffer storage device, the comparator determines the value of the contents of the address conversion buffer mechanism corresponding to the same position as the previously held address, and It guarantees the data in the array and buffer storage so that it will not malfunction.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

Figure 2 shows logical addresses and buffer storage (hereinafter referred to as
rBSJ) address, address array (rBSJ) address, address array (rBSJ)
11 is a segment field of a logical address, 12 is a same page field, 13 is a same displacement field, and 14 is an address field of AA and BS. Note that the address is a double word boundary (4 bytes).

Further, FIG. 3 is a diagram showing the relationship between the above-mentioned address translation buffer mechanism (hereinafter referred to as [TLBJ), AA and BS, where 21 indicates TLB 122 is AA.

23 indicates a BS, 24 a logical address, 25 a TLB reference address, and 26 a displacement field.

27 is part of the physical address read from TLB,
The AA, BS address is the displacement field 26 and T
It is composed of the physical address 27 read from the LB21.

To convert a logical address to a physical address, use the well-known method of searching the segment table from the segment field 11, searching the page table from the segment table entry and page field, and finding the physical address from the page table entry. . TLB2
Reference numeral 1 denotes an associative memory for reading out the physical address 27 from the logical address 24, which holds a part of the copy of the page table entry. Physical address 27 equal to width and displacement field 2 of TLB
6, AA22. Access B523.

As mentioned above, in the conventional method, TLB2 is always
In order to use the physical address 27 read from 1,
TLB21 access is AA22. This was an overhead for B523 access. On the other hand, in the buffer storage control method according to the present invention, AA22.
B523 is not accessed using the physical address 27 read from the TLB 21, but accessed using the physical address obtained in the previous address conversion, thereby making it possible to avoid the overhead of the TLB 21.

FIG. 4 is a configuration diagram showing an embodiment of the present invention. In the figure, 3I is the aforementioned TLB, 32 is AA, and 33 is BS.
, 34 is a register that stores the obtained physical address after address conversion, 35 is a register that stores the physical address used for the addresses of AA32 and B533 mentioned above,
36.37.38 is a comparator (CP), 39 is the above-mentioned B5
33, a timing control circuit that provides data fetch timing and a select signal 51 for the physical address multiplexer 41; 42, a selector; 43, a NAND gate; 44, a driver; 52, a logical address input; 53, a BS fetch timing signal; It shows read BS data. Note that the number beside each signal line indicates the number of bits of the address line.

The operation of this embodiment will be described below based on the operation flow of the timing control circuit 39 shown in FIGS. 4 and 1. Note that PAR in FIG. 1 is the above-mentioned AA32. B5
33 is the register 35 that stores the physical address used for the address.

In response to an access request to the logical space, the TLB 31 is referenced from the logical address 52, and at the same time, the AA32. B533 starts accessing. Here, register 35 contains AA3 in the previous access.
2. The upper address 58 used in B533 is stored,
Multiplexer 41 connects output line 50 of register 35 to
is selected.

AA32. The 14 addresses input to B533 correspond to the lower physical addresses, and B533 is 2”
It has a byte capacity of 4 bytes (32 bits) = 64. On the other hand, AA32 uses 12 of the 14 addresses, excluding the lowest two, and 2"=4
has an entry depth of . In other words, the 12-bit output data of AA32 corresponds to the upper part of the physical address, and the memory is divided into 14 lines + A corresponding to the address of B533.
A total of 26 pieces, including 12 pieces of A32.

Addressing. Also, one entry in AA32 points to four data entries in B533. Note that the above-mentioned update of AA32 is executed at the time of block transfer of B533.

Now, the TLB directory data 48 read from the TLB 31 is processed by the comparator 36 at logical address 4.
9 and the comparison result is reported to timing control circuit 39 via line 54. At the same time, T L B31
A comparator 37 compares the physical address 62 corresponding to the register 35 of the physical address 45 read from the data portion of the register 35 with the data in the register 35, and the result is reported to the timing control circuit 39 via a line 55.

The timing control circuit 39 determines the comparison result between lines 54 and 55 at a predetermined timing, and performs the processing shown in FIG. 1.

(1) The comparison result output on line 54 is "match",
If the comparison result output on line 55 is "match" (step 71), multiplexer 41 retains the selection on line 50 and outputs NAND on line 61.
The input of the gate 43 is set to 1". On the other hand, the data 57 read from the AA 32 is compared with the physical address 40 by the comparator 38 (step 72), and if they match, the input of the NAND gate 43 is set to 1". The input of ~ is “l”
These turn on NAND gate 43, opening driver 44 via line 56 and sending BS data 59 onto the bus.

Then, data is fetched at the optimum time using the BS fetch timing signal 53 sent from the timing control circuit 39 (step 73). If the comparator 38 does not match (step 72), block transfer of the BS is performed in the same manner as before (step 74).
).

(2) The comparison result output on line 54 is [match J,
If the comparison result outputted to line 55 is "non-coincidence" (step 7), the multiplexer 41 is switched to the data of TLB 32 by line 51, and the AA
32. Re-access B533 (step 76), AA
If the comparison result between the data at 32 and the physical address 4o matches (step 72), the NAND gate 43 opens the driver 44, the BS data is sent to the bus, and the timing control circuit 39 outputs the BS fetching timing signal 53. , the data is fetched after a certain time delay (step 73). At the same time, the value of register 35 is also updated via line 58.

(3) If the comparison result output to the line 54 is "not a match" (step 71), address conversion is performed (step 75), and the obtained physical address is stored in the register 3.
4 and write to TLB11, the multiplexer 41 is switched to line 45, and AA32°B
533 and updates the register 35.

FIG. 5(a) is a diagram showing the timing when the comparison result output to line 54 in (1) above is "match" and the comparison result output to line 55 is "match". The symbol PAR in this figure refers to the register 35, ``rPAR hit'' is the signal of the output 55 of the comparator 37, ``rTLB hit'' is the signal of the output 54 of the comparator 36,
"FAA hit" respectively refer to the output of comparator 38.

In FIG. 5(a), after the logical address is determined, the PAR hit and TLB hit are determined within one clock, and if both are hits, the AA hit is determined by the next clock. If so, the BS data is fetched using the BS fetch trigger in two clocks.

Further, FIG. 5(b) shows the timing when the comparison result outputted to line 54 in the above (2) is "1 match" and the comparison result outputted to line 55 is "no match". It is a diagram. Here, after the PAR mishit is confirmed,
AA32. The address of B533 is retransmitted, and the timing of AA hit and BS fetch trigger is delayed by one clock.

According to the above embodiment, the address array and buffer storage device are accessed not by the physical address read from the address translation buffer mechanism, but by the physical address obtained by the previous address translation. In addition, the overhead of the address translation buffer mechanism can be avoided.

It should be noted that the above-mentioned example shows an example of the present invention, and it goes without saying that the present invention should not be limited thereto.

〔Effect of the invention〕

As described in detail above, according to the present invention, the present invention includes an address translation function that translates a logical address into a physical address, an address translation buffer mechanism that associates a physical address from a logical address, and a part of data stored in the main memory. In a virtual storage system having a buffer storage device that stores the data, and an address array that stores the correspondence between the main storage device and the buffer storage device, a part of the physical address obtained in the previous address conversion is stored, and the stored address array is stored. The contents are compared with the contents of the current address translation buffer mechanism, and the hit judgment of the address array and the access timing of the buffer storage device are changed based on the result of the comparison, so that the access time of the buffer storage device is changed. This has the remarkable effect that it is possible to realize a buffer storage control method and a device therefor that can avoid the overhead of the address translation buffer mechanism.

[Brief explanation of drawings]

FIG. 1 is an operation flowchart of a timing control circuit of a buffer storage control device showing an embodiment of the present invention, FIG. 2 is a diagram showing the correspondence between bit positions of logical addresses, BS addresses, and AA addresses, and FIG. TLB and AA and B
FIG. 4 is a diagram showing the overall configuration of the embodiment, and FIG. 5 is a timing chart for explaining the operation. 21.31: T, LB, 22,32: AA,
23, 33: BS, 24°52=logical address,
34, 35: Physical address storage register (PAR), 3
6, 37, 38: Comparator (CP), 39° timing control circuit, 41: Multiplexer, 42: Selector, 4
3: NAND gate, 44: driver, 51: select signal, 52: logical address input, 53: BS fetch timing signal, 59: read BS data. Figure Figure Figure Figure Figure (Part 1) (a) BS fetch trigger

Claims (1)

[Scope of Claims] 1. An address conversion function that converts a logical address into a physical address, an address conversion buffer mechanism that associates a physical address from a logical address, and a buffer storage device that holds a part of data in a main storage device; In a virtual storage system having an address array that maintains the correspondence between the main storage device and the buffer storage device, a part of the physical address obtained in the previous address conversion is held, and the held content and the current address conversion are 1. A buffer storage control method, comprising comparing the contents of a buffer mechanism and changing the hit determination of the address array and the access timing of the buffer storage device based on the result of the comparison. 2. simultaneously using the retained address to access the address array and buffer storage;
A comparison result between the held address and the corresponding contents of the address translation buffer mechanism matches;
2. The buffer storage control method according to claim 1, further comprising executing data processing in the address array and buffer storage device at an optimal time if a physical address exists in the address translation buffer mechanism. 3. If the result of the comparison between the held address and the corresponding contents of the address translation buffer mechanism is a mismatch, and a physical address exists in the address translation buffer mechanism, the held address 3. The buffer storage control method according to claim 1, further comprising switching the contents of the address translation buffer mechanism to the corresponding contents of the address translation buffer mechanism, and delaying the processing timing of data in the address array and the buffer storage device by a certain period of time. 4. An address conversion function that converts a logical address into a physical address, an address conversion buffer mechanism that associates a physical address from a logical address, a buffer storage device that holds a part of data in a main storage device, and the main storage device and the In a virtual storage system having an address array that retains correspondence between buffer storage devices, means for retaining a part of physical addresses obtained in the previous address translation, and the contents retained in the retaining means and the current address translation buffer. 1. A buffer storage control device, comprising: means for comparing the contents of the memory with the contents of the memory; and means for changing the hit determination of the address array and the access timing of the buffer storage device based on the comparison result by the comparison means.