JP2650789B2 - Cache memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a set associative cache memory device used as a high-speed local memory of an electronic computer.

[0002]

2. Description of the Related Art FIG. 9 shows a schematic configuration diagram of a conventional cache memory device. Here, a 3-way set associative cache memory will be described.

In FIG. 9, reference numeral 10 denotes an address register for holding an address 11 corresponding to a tag required by a cache memory and an address 12 required for selecting one entry from the tag; The first set of tag portions, the second set of tag portions, the third set of tag portions, 30, 31, and 32 are respectively the first set of data portions, the second set of tag portions, and the second set of tag portions.
Data part of the set, Data part of the third set, 40, 41, 42
Are the first set of comparators, the second set of comparators, and the third set of comparators for comparing the address input to the cache memory with the tag section, respectively, 50, 51, and 52 are output from the data section, respectively. A first set of output circuits, a second set of output circuits, and a third set of output circuits for controlling data to be output, and 60 are data for transferring data output from the output circuits 50, 51, and 52 to the arithmetic unit. It is a bus.

[0004] The operation of the conventional cache memory device thus configured will be described below. One block is selected from the tag sections 20, 21, and 22 of the cache memory based on the address 12, and the read tag and address are selected.
11 is compared by comparators 40, 41 and 42. This comparison is performed in parallel for each set, and if they match in one set, the hit signals 70, 71, 72 corresponding to that set are asserted. These hit signals 70, 71, 72 are output circuit 5
0, 51, and 52 are input to the data section 3 of the cache memory.
Control the data output from 0, 31, 32
Output to

[0005] This process will be described with reference to the timing chart of FIG. Here, the clocks are two-phase clocks ph1 and ph2. Address (address) of address register 10 is ph1
Is input to the cache memory, and one block is selected from the tag part of the cache memory by the address 12 and the tag is selected.
Read (tag). This tag is read with a delay from the address. The read tag and the address 11 are compared by the comparators 40, 41, 42. This comparison is performed in parallel for each set. If a hit occurs, a hit signal 70 (hit (set0)) of the first set or a hit signal 71 (hit (set1)) of the second set, which is a hit signal corresponding to each set. Alternatively, the third set of hit signals 72 (hit (set2)) is asserted with a delay from the tag. The data output from the data portion of the cache memory by the hit signal is output to an output circuit 50,
Control is performed by 51 and 52, and data (data) is output to the data bus 60. This data is output with a delay from the hit signal. For example, it indicates that the data n corresponding to the tag hit in the first set corresponding to the address n is output with a delay until the cycle of ph2.
Similarly, after a hit signal is asserted in one set, data is output with a delay.

[0006]

However, the above configuration has a problem that a time lag occurs in data reading because a hit signal is asserted after tag comparison and data is output after that. That is, the address of the address register 10 is input to the cache memory, one block is selected from the tag units 20, 21, and 22 of the cache memory, and the tag is read. This tag is read with a delay from the input address, and since the read tag and the input address are compared in parallel in each set, it is determined that a hit has occurred in one of the sets. Until the hit signal is not asserted. This hit signal causes the data part of the cache memory
Since data from 30, 31, and 32 is output to the data bus, a time lag of data reading becomes an extremely serious problem as the capacity of the cache memory increases.

An object of the present invention is to provide a high-performance cache memory device in which a time lag is reduced in data reading in consideration of such points.

[0008]

In order to solve the above problems, a cache memory device according to the present invention is a set associative type cache memory, in which an address inputted from the outside to the cache memory and held inside the cache memory. An address comparator for comparing with a tag unit, a storage unit for storing a flag indicating that the data unit was accessed immediately before using a hit signal output from the address comparator as an input, and a signal output from the storage unit or An output circuit for controlling outputs from a plurality of sets of data portions of the cache by a hit signal.

Further, a cache memory device according to the present invention
In a set associative cache memory, cache information that indicates recently accessed sets
A storage unit that stores each entry of the tag unit of the memory; an address comparator that compares an address input from the outside to the cache memory with a tag unit held inside the cache memory; and a hit that is output by the address comparator. An output circuit for controlling output from a plurality of sets of data portions of the cache by a signal or the information.

Further, in the cache memory device of the present invention, in an address translation device and a physical cache memory of a set associative system using a physical address output from the address translation device, each entry of a tag section of the address translation device is provided. An address translator that adds information indicating that the corresponding physical address is mapped to a specified set in the cache memory to each entry; a physical address translated by the address translator and held in the cache memory And an output circuit for controlling outputs from a plurality of sets of data portions of the cache according to a hit signal output from the address comparator or the information. .

According to the present invention, with the above-described configuration, the access immediately before the hit signal is output from the address comparator for comparing the address input from the outside into the cache memory with the tag section held in the cache memory is performed. Using a flag indicating that the data part accessed immediately before was set using the hit signal of, or using the information indicating that the recently accessed and set data part was stored corresponding to each entry of the cache memory. Or
Alternatively, by using information from the address translator added to each entry information indicating that the physical address corresponding to each entry of the tag portion of the address translator is mapped to the specified set in the cache memory, Before the hit signal is output, the data from the data section of the cache memory can be output to the bus, and the time lag of data reading can be reduced.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a cache memory device according to a first embodiment of the present invention. Here, a 3-way set associative cache memory will be described.

In FIG. 1, reference numeral 10 denotes an address 11 corresponding to a tag required by the cache memory and an address 1 required to select one entry from the tag.
2 are stored in the first and second sets of tag units, 20, 21 and 22, respectively.
The tag portions of the set, 30, 31, and 32, are the data portion of the first set, the data portion of the second set, and the data portion of the third set, respectively. A first set of comparators, a second set of comparators, a third set of comparators, 50, 51, and 52 for comparing data with a first set of outputs controlling data output from the data unit, respectively. Circuit, second
Set of output circuits, third set of output circuits, 80, 8
Reference numerals 1 and 82 denote a first set of storage units, a second set of storage units, and a third set of storage units, respectively, each storing a flag indicating that a data unit accessed immediately before using a hit signal by the immediately preceding access is set. , 60 are output circuits 50,
This is a data bus for transferring data output from 51 and 52 to the arithmetic unit.

The schematic configuration of the storage unit is shown as a first set of storage units.
FIG. 2 shows 80 as an example. In FIG. 2, reference numeral 110 in the storage unit 80 is a latch circuit for holding a hit signal. Other configurations are the same as those in FIG.

The operation of the thus configured cache memory device of this embodiment will be described below. Here, the clocks are two-phase clocks ph1 and ph2. Tag part 20, 2 of the cache memory by address 12.
One block is selected from 1 and 22, and the read tag and the address 11 are compared by the comparators 40, 41 and 42. This comparison is performed in parallel for each set, and if a match is found in one set, hit signals 70, 71, 72 corresponding to that set are set.
Is asserted. A flag indicating that the data section accessed immediately before is set using the hit signal is set to the first flag.
The data is stored in the set storage unit 80, the second set storage unit 81, and the third set storage unit 82. For example, in the storage unit 80, the hit signal 70 is stored in the latch circuit 110 with the clock ph2,
The stored signal is ANDed with the clock ph1 to generate a flag signal 90. The load signal 100 is generated by ORing the hit signal 70 and the flag signal 90. This load signal 100 is input to the output circuit 50, and the data 30
And outputs the data to the data bus 60. Therefore, after the hit signal 70 is asserted, data from the data portion of the cache memory is transferred to the data bus 60.
Or hit signal from previous access
The data from the data section 30 of the cache memory is output to the data bus 60 prior to the hit signal by the flag signal 90 indicating the set of the data section accessed immediately before using the 70. Similarly, the load signals 101 and 102 are output circuits, respectively.
Input to 51 and 52 and data part 31 and 32 of cache memory
And outputs the data to the data bus 60.

This process will be described with reference to the timing chart of FIG. Address (address) of address register 10 is ph1
Is input to the cache memory, and one block is selected from the tag part of the cache memory by the address 12 and the tag is selected.
Read (tag). This tag is read with a delay from the address. The read tag and the address 11 are compared by the comparators 40, 41, 42. This comparison is performed in parallel for each set, and if a hit occurs, a hit signal 70 (hit (set0)) of the first set or a hit signal 71 (hit (set1)) of the second set, which is a hit signal corresponding to each set. Or third
The set hit signal 72 (hit (set2)) is asserted with a delay from the tag. In the storage unit 80, the hit signal is stored in the latch circuit 110 with the clock ph2, and the stored signal is ANDed with the clock ph1, and the flag signal 90 is stored.
(Flag (set0)) is generated. Similarly, in the storage units 81 and 82, a flag signal 91 (flag (set1)) and a flag signal
Generate 92 (flag (set2)). The hit signal and the flag signal are ORed, and the load signal 10
0 (load (set0)), load signal 101 (load (set1)) and load signal 102 (load (set2)) are generated. This load signal is input to the output circuits 50, 51, and 52 for each set, controls data output from the data units 30, 31, and 32 of the cache memory, and outputs data to the data bus 60 . This data is output with a delay from the load signal.

In FIG. 3, for example, in the first cycle, a flag signal flag (set1) A indicating that the data accessed immediately before is set by a hit signal generated immediately before the hit signal hit (sel1) B is set. If it exists, the data from the data portion of the cache memory corresponding to the address n is stored in the flag signal flag generated in the second set.
(set1) A tag n before hit signal hit (sel1) B
Data n is output to the data bus at the same timing as. Next, the data from the data portion of the cache memory corresponding to the address n + 1 is given by a flag signal flag (set1) C generated by hitting immediately before in the second set.
The data (invalid) is output to the data bus at the same timing as the tag n + 1 before the next hit signal hit (sel2) D, but the data pre-reading actually fails and hits in the third set. As a result, the data n + 1 is output to the data bus as valid data later than the hit signal hit (sel2) D. Similarly, for each set in the cache memory, data is pre-read according to a flag signal generated by holding information indicating the set accessed immediately before. If data read-ahead fails, valid data is output according to a load signal generated by a hit signal from a hit set.

As described above, according to the present embodiment, a hit signal is output before a hit signal is output according to a flag signal generated by holding information indicating a set accessed immediately before for each set in the cache memory. Data from the data section of the cache memory can be output to the data bus. Therefore, it is possible to reduce a time lag of data reading due to an increase in the capacity of the cache memory.

FIG. 4 is a schematic block diagram of a cache memory device according to a second embodiment of the present invention. Here, a 3-way set associative cache memory will be described.

In FIG. 4, reference numeral 10 denotes an address 11 corresponding to a tag required by the cache memory and an address 1 required to select one entry from the tag.
2 are stored in the first and second sets of tag units, 20, 21 and 22, respectively.
The tag portions of the set, 30, 31, and 32, respectively, are the data portion of the first set, the data portion of the second set, the data portion of the third set, 40, 41, and 42 are the address 11 and the tag input to the cache memory, respectively. A first set of comparators, a second set of comparators, a third set of comparators, 50, 51, and 52 for comparing data with a first set of outputs controlling data output from the data unit, respectively. Circuit, second
A set of output circuits and a third set of output circuits. 9
0, 91, and 92 indicate information indicating that they have been recently accessed and set, and the tag section 20 of each set in the cache memory.
This is a flag signal stored for each of the entries 21 and 22.

The operation of the thus configured cache memory device of the present embodiment will be described below. Tag part 2 of cache memory by address 12
One entry from 0, 21, 22 is selected, and the read tag and address 11 are compared with the comparators 40, 41, 42.
To compare. This comparison is done in parallel for each set,
If there is a match in one set, the hit signals 70, 71, 72 corresponding to that set are asserted. The hit signals 70, 71, and 72 are stored as information indicating that they have been recently accessed and set, for each entry in the tag section of each set in the cache memory. In the first set, the load signal 100 is generated by ORing the hit signal 70 and the flag signal 90. The load signal 100 is input to the output circuit 50, and the data section 30 of the cache memory is
And outputs the data to the data bus 60. Therefore, after the hit signal 70 is asserted, data from the data portion of the cache memory is transferred to the data bus 60.
Or the data from the data portion of the cache memory is output to the data bus 60 prior to the hit signal by the flag signal 90 generated from the information indicating that the access has been set recently. Similarly, load signal 1
Numerals 01 and 102 control the data input to the output circuits 51 and 52 and output from the data units 31 and 32 of the cache memory, and output the data to the data bus 60.

This process will be described with reference to the timing chart of FIG. Here, the clocks are two-phase clocks ph1 and ph2. If the address of the address register 10 is ph1
, And one entry is selected from the tag portion of the cache memory according to the address 12, and the tag is read. One entry by address 12
And a flag signal 90 (flag (set
0)), or a flag signal 91 (flag (set1)) or a flag signal 92 (flag (set2)). On the other hand, the read tag and the address 11 are compared by the comparators 40, 41 and 42. This comparison is performed in parallel for each set. If a hit occurs, a hit signal 70 (hit (set0)) of the first set or a hit signal 71 (hit (set1)) of the second set, which is a hit signal corresponding to each set. Alternatively, the third set of hit signals 72 (hit (set2)) is asserted with a delay from the tag. The hit signal and the flag signal are ORed, and a load signal 100 (load (set0)), a load signal 101 (load (set1)), and a load signal 102 (load
(set2)). The load signal is input to the output circuits 50, 51, and 52 for each set, controls data output from the data units 30, 31, and 32 of the cache memory, and outputs data to the data bus 60. This data is output with a delay from the load signal.

In FIG. 5, for example, in the first cycle, the flag signal flag (s) of the entry of the tag unit of the second set is set.
et1) E is generated, the data from the data portion of the cache memory corresponding to the address n is converted to the hit signal hit by the flag signal flag (set1) E generated in the second set.
(set1) Data n at the same timing as tag n before F
Is output to the data bus. Next, in response to address n + 1, a hit signal hit is generated by a flag signal flag (set0) G generated from the recently accessed first set of entries.
(set1) is data (invalid) is outputted to the data bus at the same timing as the tag n + 1 before the H, actually failed previously read data, the hit signal hit by hit in the second set ( data n + 1 is output to the data bus as valid data later than set1) H. Similarly, for each entry in the tag section of each set of the cache memory, data is prefetched in accordance with a flag signal generated by holding information indicating that the set has been accessed recently. If data read-ahead fails, valid data is output according to a load signal generated from a hit signal from a hit set.

As described above, according to the present embodiment, for each entry of the tag portion of each set of the cache memory, a hit is performed in accordance with the flag signal generated by holding the information indicating that it has been accessed and set recently. Before the signal is output, data from the data portion of the cache memory can be output to the data bus. Therefore, the time lag of data reading due to the increase in the capacity of the cache memory can be reduced.

The reference numerals 90, 91 and 92 indicate flag signals obtained by holding information indicating the recently accessed set for each entry of the tag section of each set in the cache memory, but indicate the recently accessed set. Information may be stored in one place for each entry .

FIG. 6 is a schematic configuration diagram of a cache memory device according to the third embodiment. Here, a 3-way set associative cache memory will be described. In FIG. 6, reference numeral 10 denotes an address register for holding an address 11 corresponding to a tag unit required in the cache memory and an address 12 required for selecting one entry from the tag unit. Tag part of the set, tag part of the second set, tag part of the third set, 30,
31 and 32 are a first set of data, a second set of data, and a third set of data, respectively. 40, 41 and 42 are for comparing the address 11 and the tag, respectively, inputted to the cache memory. A first set of comparators, a second set of comparators, a third set of comparators, 50, 51 and 52, respectively, a first set of output circuits for controlling data output from the data portion, a second set of outputs Circuits, a third set of output circuits,
120 is an address translator, 130 is an address translator 120
The address translator 120 decodes information indicating that the physical address corresponding to each entry of the tag section is mapped to a specified set in the cache memory. Has been added.

FIG. 7 shows the address translation device 120 and the decoder 13
FIG. In FIG. 7, reference numeral 140 denotes bit information indicating that the physical address of the data section corresponding to each entry of the tag section of the address translator 120 is mapped to a specified set in the cache memory. The case where bit information of 00 corresponding to the set, 01 corresponding to the second set, and 10 corresponding to the third set is shown. 150 is bit information 140
And outputs flag signals 90, 91 and 92 for data reading in synchronization with the clock ph1.

The operation of the thus configured cache memory device of the present embodiment will be described below. Here, the clocks are two-phase clocks ph1 and ph2. Tag part 20, 2 of the cache memory by address 12.
One block is selected from 1 and 22, and the read tag and the address 11 are compared by the comparators 40, 41 and 42. This comparison is performed in parallel for each set, and if a match is found in one set, hit signals 70, 71, 72 corresponding to that set are set.
Is asserted. On the other hand, information mapped to the address translator 120 is decoded by the decoder 130,
Flag signal 90 corresponding to the first set, flag signal 91 corresponding to the second set, flag signal 92 corresponding to the third set
Generate For example, in the first set, the load signal 100 is generated by ORing the hit signal 70 and the flag signal 90. The load signal 100 is input to the output circuit 50, controls data output from the data section 30 of the cache memory, and outputs the data to the data bus 60. Therefore, after the hit signal 70 is asserted, the data from the data portion of the cache memory is output to the data bus 60 or is generated from the bit information 140 indicating that the data is mapped to the specified set in the cache memory. The flag signal 90 outputs data from the data portion of the cache memory to the data bus 60 before the hit signal. Similarly, the load signals 101 and 102 are input to output circuits 51 and 52, respectively, and control the data output from the data units 31 and 32 of the cache memory and output them to the data bus 60.

This process will be described with reference to the timing chart of FIG. Address (address) of address register 10 is ph1
Is input to the cache memory, and one block is selected from the tag part of the cache memory by the address 12 and the tag is selected.
Read (tag). At the same time, a flag signal 90 (flag) corresponding to each set is obtained from bit information 140 indicating that the physical address of the data section corresponding to each entry of the tag section of the address translator 120 is mapped to the specified set in the cache memory. (set0)), flag signal 91 (flag (set
1)) or one of the flag signals 92 (flag (set2)). The tags read from the cache memory and the address 11 are compared by the comparators 40, 41, and. This comparison is performed in parallel for each set, and if a hit occurs, a hit signal 70 (hit) of the first set, which is a hit signal corresponding to each set.
(set0)) or hit signal 71 of the second set (hit (set1))
Alternatively, the hit signal 72 (hit (set2)) of the third set is asserted with a delay from the tag. OR the hit signal and the flag signal, and load signal 100 (load (set0)), load signal 101 (load (set1)) for each set,
A load signal 102 (load (set2)) is generated. The load signals are input to the output circuits 50, 51, and 52 for each set, control the data output from the data units 30, 31, and 32 of the cache memory, and output data to the data bus 60. This data is output with a delay from the load signal.

In FIG. 8, for example, address n
The flag signal flag (set1) I obtained from the bit information 140 indicating that the data is mapped to each set of the cache memory corresponds to the same timing as the tag n before the hit signal hit (set1) J. Outputs data n from the data portion of the cache memory to the data bus. Next, the flag (set0) K obtained from the bit information 140 corresponding to the address n + 1 causes the data portion of the cache memory to be generated at the same timing as the tag n + 1 prior to the hit signal hit (set0) L. Output data n + 1 to the data bus. Similarly, data is pre-read according to a flag signal obtained from the bit information of the address translation device indicating that the data is mapped to the specified set in the cache memory.

As described above, according to the present embodiment, information indicating that the physical address corresponding to each entry of the tag section of the address translator is mapped to the specified set in the cache memory is included in each entry. According to the flag signal generated by the information of the added address translator, data from the data portion of the cache memory can be output to the data bus before the hit signal is output. This pre-reading of data is all successful if the cache memory hits. Therefore, it is possible to reduce a time lag of data reading due to an increase in the capacity of the cache memory.

As described above, according to the present invention, immediately before the hit signal is output from the address comparator that compares the address input from the outside to the cache memory with the tag section held in the cache memory, Using a flag indicating that the data part accessed immediately before was set using a hit signal due to the access of the cache memory, or information indicating that the most recently accessed data part was set corresponding to each entry of the cache memory. Or use
Alternatively, by using information from the address translator added to each entry information indicating that the physical address corresponding to each entry of the tag portion of the address translator is mapped to the specified set in the cache memory, Before the hit signal is output, data from the data section of the cache memory can be output to the bus. Therefore, the time lag of data reading accompanying the increase in the capacity of the cache memory can be reduced, and its practical effect is great as a high-speed local memory in a computer with a high clock frequency.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a cache memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a storage unit according to the first embodiment.

FIG. 3 is a timing chart of the first embodiment.

FIG. 4 is a schematic diagram of a cache memory device according to a second embodiment of the present invention.

FIG. 5 is a timing chart of the second embodiment.

FIG. 6 is a schematic configuration diagram of a cache memory device according to a third embodiment of the present invention.

FIG. 7 is a schematic configuration diagram of an address translation device according to a third embodiment.

FIG. 8 is a timing chart of the third embodiment.

FIG. 9 is a schematic configuration diagram of a conventional cache memory device.

FIG. 10 is a timing chart of a conventional cache memory device.

[Explanation of symbols]

 10 Address register 20, 21, 22 Tag section 30, 31, 32 Data section 40, 41, 42 Comparator 50, 51, 52 Output circuit 60 Data bus 70, 71, 72 Hit signal 80, 81, 82 Storage section 90, 91, 92 Flag signal 100, 101, 102 Load signal 110 Latch circuit 120 Address converter 130 Decoder 140 Bit information 150 2-bit decoder

Claims (3)

(57) [Claims] In a set associative cache memory, an address comparator for comparing an address externally input to the cache memory with a tag held in the cache memory, and a hit signal output from the address comparator. And a storage unit for storing a flag indicating that the data unit has been accessed immediately before, and an output for controlling the output from the data units of the plurality of sets of the cache by a signal output from the storage unit or the hit signal. And a circuit. 2. A set associative cache memory, comprising: a storage unit for storing information indicating a recently accessed set in each entry of a tag unit of the cache memory; an address externally input to the cache memory; And an output circuit for controlling the output from the data section of the plurality of sets of the cache according to a hit signal output from the address comparator or the information. A cache memory device characterized by the above-mentioned. 3. An address translator and a set associative physical cache memory using a physical address output from the address translator, wherein a physical address corresponding to each entry of a tag section of the address translator is stored in the cache memory. An address translation device that adds information indicating that it is mapped to a specified set in each entry to each entry is compared with a physical address translated by the address translation device and a tag portion held in the cache memory. An address comparator;
An output circuit for controlling outputs from a plurality of sets of data portions of the cache according to a hit signal output from the address comparator or the information.