JPH0481905B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a packet switching system, and in particular, to a packet switching node that transmits the packet to a subsequent exchange or a receiving terminal before receiving the entire packet. This invention relates to a semi-storage type packet switching system that allows transmission to begin.

(Prior Art) FIG. 5 shows an example of a packet structure in conventional packet switching. In the configuration example shown in this figure, a start flag indicating the beginning of a packet is followed by a header section containing a logical channel number for packet routing, a code indicating the packet type, a sequence number, etc., and a header section containing information exchanged between communicating users. an error check code for detecting transmission errors on the transmission path, and finally an end flag indicating the end of the packet.

When a pocket with such a configuration is exchanged by semi-storage, the packet exchange node determines the output destination route and line from the logical channel number contained therein after receiving the packet header part, and then uses the logical channel number. After converting the packet into an outgoing logical channel number based on pre-registered information, transmission of the packet is started. However, since the error check code is placed immediately before the end flag, even if a transmission error occurs in the header, it will not be detected when the header is received, and for example, the logical channel number may be received incorrectly. If the packet is sent to its original destination,
The packet will be sent out not on the line but on another route or line, and as a result, a terminal that is not the intended destination will receive the packet.

Another example of the structure of packets in conventional packet switching is shown in FIG. In the configuration example shown in this figure, an error check code for detecting a transmission error in the header section follows the start flag and the header section.
Further, an error check code for detecting transmission errors in the information section is provided following the information section.

When exchanging packets with such a configuration in a semi-storage manner, the packet exchange node receives the packet header section and the header section error check code, and only if it confirms that there is no transmission error in the header section, will the packet be included in the header section. The output destination route and line are determined from the logical channel number received, and after exchanging the outgoing logical channel number based on the information registered in advance, transmission of the packet is started. Become. If a transmission error is detected in the header section, the packet switching node discards the packet being received.

(Problem to be Solved by the Invention) By configuring the packet as shown in FIG. 6, it becomes possible to accurately transfer the packet to the terminal that should receive it, but Since it is necessary to insert a header error check code between the header and the header, an internationally standardized packet format such as that shown in CCITT Recommendation Q,921 cannot be applied. Therefore, when using internationally standardized packet formats between users and networks or between different networks such as between international networks, it is necessary to exchange formats at subscriber line switching nodes or international gateway stations. .

The purpose of the present invention is to solve the above-mentioned problems and to use an internationally standardized packet format.
Furthermore, the purpose is to realize semi-storage type packet exchange in which packets are accurately transferred to the destination to which they should be received.

(Means for Solving the Problems) A feature of the present invention for achieving the above object is to receive a packet including at least a header section, an information section, and an error check code, and to determine the output route and the output path according to the header section. In a packet switching system in which an outgoing line is determined and the packet is transmitted to a subsequent exchange or receiving terminal, a header part error check code for checking errors only in the header part is placed first in the reception and transmission order of the packet. Next, the header section is placed, and when the header section is received, the header section is checked for errors. If there is an error in the header section, the packet being received is discarded, and if there is no error, the header section is Follow the directions,
It is a semi-storage type packet switching system that determines the outgoing line and starts sending the packet to the determined outgoing route and outgoing line without waiting for the entire packet to be received.

(Structure and operation of the invention) FIG. 1 shows the structure of a packet showing the principle of the invention. In this configuration, a header error check code for detecting transmission errors in the header section is provided following the start flag, followed by header section, information section, and all packet error check codes. The all-packet error check code is an error check code for detecting transmission errors in a portion including both a header section and an information section, as in the configuration example shown in FIG. In the packet structure shown in FIG. 1, an internationally standardized packet format can be applied to the header section, information section, and all packet error check code sections.

When exchanging packets with the configuration shown in Figure 1 in a semi-storage manner, the packet exchange node receives the header error check code and the packet header, and then
Only when it is confirmed that there are no transmission errors in the header section, the output destination route and line are determined from the logical channel number included in the header section, and the logical channel number is determined from the output terminal based on the pre-registered information. After exchanging logical channel numbers, the transmission of the packet will begin. If a transmission error is detected in the header section, the packet switching node discards the packet being received. in this way,
Similar to the configuration example shown in FIG. 6, it is possible to accurately forward a packet to its destination.

When packets having the structure of the present invention are used, for example, between exchanges in a network, and packets having an internationally standardized structure are used between an interface network between a user and the network, the packets are transferred at a subscriber line switching node or an international barrier station. There is no need to perform automatic conversion. In addition, when the entire packet is once received and then sent for a certain packet group, and when half storage/exchange is performed for another packet group, the packets configured according to the present invention are used, and the entire packet should be stored once. For packets, by gradually setting the error check code in the header section at the input section of the exchange node, the packet having the configuration shown in Fig. 1 can be used in both exchange modes (full accumulation mode and half accumulation mode). .

(Example) Next, an example of the present invention will be described using the drawings.

FIG. 2 shows an embodiment of a packet switching node that implements the semi-storage type packet switching system according to the present invention. In Figure 2, IC ₁ , IC ₂ ... IC _o connect the incoming lines to the packet switching node, and HC ₁ , HC ₂ ... HC _o
represents the header part analysis circuit, DC ₁ , DC ₂ ... DC _o represents the header part analysis circuit HC ₁ , HC ₂ ... HC _o and the below-mentioned
Dual port memory that can be accessed from both CPUs, CPU rewrites the packet header section, and dual port memory DM ₁ , DM ₂ ...
DM _o and dual port memory DM ₁₁ described below,
DM ₁₂ ... MB is a central control unit that controls packet transfer between memories between DM _n , and MB is a CPU that controls DM ₁ ,
DM ₂ ... DM _o and DM ₁₁ , DM ₁₂ ... the memory bus for accessing DM _n . DM ₁₁ ,
DM ₁₂ ... DM _n is a dual port memory that can be accessed from both the CPU and packet transmission control circuits SC ₁ , SC ₂ ... SC _n to be described later, and SC ₁ , SC ₂ ...
SC _n is the packet transmission control circuit, OC ₁ , OC ₂ ...
OC _n indicates the outgoing line from the packet switching node.

In this embodiment, when the packet shown in FIG. 1 is transferred on the incoming line, for example, IC ₁ , the header section analysis circuit HC ₁ transfers it to the header section when the header section error check code and the header section are received. Check for errors. If there is a transfer error, the contents of the packet are not written to the dual port memory _DM1 , and the contents of the packet received up to the end flag of the packet are discarded. If there is no transfer error in the header section, transfer the contents of the header section to the dual port memory.
Write to DM ₁ .

The CPU has dual port memory DM ₁ , DM ₂ ...
...The contents of DM _o are periodically scanned through the memory bus MB, and when it is detected that the contents of the header part have been written to DM ₁ , DM ₂ ...DM _o , this contents is read by referring to table TBL. Determines the outgoing route, outgoing line number, and header value to be used on the outgoing line, and rewrites it to the header to be used on the outgoing line of the packet switching node.At the same time, the outgoing line number and packet forwarding request are sent. Remember in TBL that there is. For example, when it is detected that a header has been written in DM ₁ , it sets the packet transfer request presence/absence flag in the table TBL corresponding to DM ₁ to "Yes", and stores the output line number. put.

FIG. 3 shows the processing operations of the central control unit CPU on the memory bus MB. The CPU uses dual port memory every certain period (cycle time).
DM ₁ , DM ₂ ... Repeat scanning of DM _o , reading DM ₁ and DM ₂ sequentially, and writing the contents to dual port memory DM ₁₁ , DM ₁₂ ... DM _n corresponding to the output line to be output. .

As an example, the operation when a packet sent on input line IC ₁ is transferred to output line OC ₂ will be described below. As described above, if the header part is received by the header analysis circuit and there is no transfer error, the contents of the header part are written into the dual port memory _DM1 . When scanning DM ₁ to DM _o , the CPU
It detects that the packet to be transferred to DM ₁ has started to be written, and at the same time, the header section is rewritten to the value to be used on the outgoing line OC ₂ according to the contents of table TBL, and at the same time, the packet to be transferred to DM ₁ is written to TBL. Remember that the content exists and that the outgoing line is OC ₂ . The scanning period ends,
When the read cycle starts from DM ₁ , the CPU reads the contents of the packet in DM ₁ by one unit (e.g., 8 pits), referring to the contents of the read TBL,
Dual port memory compatible with outgoing line OC ₂
Write in DM ₁₂ . The contents of the packets sent on the input line IC ₁ are sequentially written into DM ₁ by the header analysis circuit HC ₁ , and the CPU repeats the above-mentioned operation at the read period from DM ₁ during each cycle time. Sequentially writes the contents of the packet into _DM12 . The transmission control circuit SC ₂ corresponding to the outgoing line OC ₂ is
When the contents of the packet are written into the DM ₁₂ , a header error check code is generated when the header is written, and the header error check code and the header begin to be sent on the outgoing line OC ₂ in this order. When the CPU repeats this operation and detects the packet end flag when reading the packet contents from DM ₁ , it writes it to DM ₁₂ and at the same time writes the packet transfer request from DM ₁ stored in the TBL. Set the flag indicating presence to “absence”. When HC ₁ detects the packet end flag,
After writing this to DM ₁ , DM ₁ will not be accessed until the start flag of the next packet is received. Similarly, when the SC ₁₂ finishes transmitting the packet end flag, it sends the idle pattern to the outgoing line OC ₂ until the next packet header is written to the DM ₁₂ .
Send upward.

In the above example, if outgoing line CO ₂ is in use when packet transmission is attempted, the contents of the packets being received are sequentially written to DM ₁ , and when OC ₂ becomes free, DM is Transfer from DM ₁ to DM ₁₂ and sending of packets will begin.

In this example, the cycle time shown in FIG.
The transfer time for the packet contents of the pits is the same.

FIG. 4 shows the processing flow of the packet switching node according to the present invention from the start of packet reception to the end of packet transmission. FIG. 6 also shows the correspondence with devices that perform each operation in the above embodiment.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize semi-storage type packet exchange with high reliability by using the internationally standardized packet format as is. Also, in cases where semi-storage type and full storage type packet switching communication are mixed,
This means that packets of the same format can be applied.

[Brief explanation of the drawing]

FIG. 1 shows the structure of a packet showing the principle of the present invention. FIG. 2 shows an embodiment of the invention. FIG. 3 shows the processing cycle in the embodiment of FIG.
FIG. 4 is a flowchart of processing in a packet switching node based on the present invention. FIG. 5 shows an example of a packet configuration in conventional packet exchange. FIG. 6 shows another example of the structure of packets in conventional packet switching.

Claims (1)

[Claims] 1. Receive a packet including at least a header section, an information section, and an error check code, determine an output path and an outgoing line according to the header section, and transmit the packet to a subsequent exchange or receiving terminal. In the packet switching system, the order of reception and transmission of the packet is such that a header error check code for checking errors only in the header section is placed first, then the header section is placed, and the time when the header section is received. The header section is checked for errors, and if there is an error in the header section, the packet being received is discarded.If there is no error, the output path and output line are determined according to the header section, and the entire packet is received. A semi-storage type packet switching system characterized by starting to send the packet to a determined output path or outgoing line without waiting.