JPH048129U - - Google Patents
Info
- Publication number
- JPH048129U JPH048129U JP4626290U JP4626290U JPH048129U JP H048129 U JPH048129 U JP H048129U JP 4626290 U JP4626290 U JP 4626290U JP 4626290 U JP4626290 U JP 4626290U JP H048129 U JPH048129 U JP H048129U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- detection circuit
- turned
- voltage detection
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 24
- 230000000903 blocking effect Effects 0.000 claims 5
- 238000012544 monitoring process Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 2
Description
第１図及び第２図は夫々本考案の一実施例の回
路図及びその動作タイミングチヤート、第３図及
び第４図は夫々従来の一例の回路図及びその動作
タイミングチヤートである。
１……システム電源、２，３……電圧検出回路
、４，１３……アンドゲート、６……電源投入タ
イミング回路、７……ＣＰＵ、８……電源端子、
１１……リセツト端子、１４……レギユレータ、
Ｔｒ１〜Ｔｒ３……トランジスタ、Ｒ１，Ｒ２…
…抵抗、Ｄ……ダイオード。
1 and 2 are a circuit diagram and an operation timing chart of an embodiment of the present invention, respectively, and FIGS. 3 and 4 are a circuit diagram and an operation timing chart of an example of the conventional art, respectively. 1... System power supply, 2, 3... Voltage detection circuit, 4, 13... AND gate, 6... Power-on timing circuit, 7... CPU, 8... Power terminal,
11...Reset terminal, 14...Regulator,
T r1 to T r3 ... transistors, R 1 , R 2 ...
...Resistance, D...Diode.
Claims (1)
上限電圧を越えた場合にのみオンとなる第１の電
圧検出回路と、該システムの電源電圧が該ＣＰＵ
動作保証範囲の下限電圧未満になつた場合にのみ
オフとなる第２の電圧検出回路と、該第１の電圧
検出回路の出力端子に制御端子を接続されて上記
システム電源電圧が上記上限電圧を越えた場合に
のみオンとなる第１のスイツチング素子と、シス
テム電源と該第１のスイツチング素子との間に接
続された抵抗と、該第１のスイツチング素子と該
抵抗との間に制御端子を接続され、上記第１の電
圧検出回路のオフ及び上記第２の電圧検出回路の
オンによりオン、上記第１及び第２の電圧検出回
路のオンによりオフ、上記第１及び第２の電圧検
出回路のオフによりオフとなるように該制御端子
を制御されてＣＰＵに上記システム電源電圧を印
加する第２のスイツチング素子と、上記システム
電源電圧が上記下限電圧未満になつた場合にＣＰ
Ｕにリセツトをかける回路とを有するコンピユー
タの電圧監視回路において、 前記第２の電圧検出回路の出力端子と、前記抵
抗と前記第１のスイツチング素子との接続点との
間に、前記システム電源電圧が前記上限電圧を越
えたときに前記第２の電圧検出回路の出力電流が
前記第１のスイツチング素子を介してアースされ
ないように阻止する電流阻止回路を接続し、 前記リセツトをかける回路として、前記第２の
電圧検出回路の出力端子と上記電流阻止回路との
接続点と、前記ＣＰＵのリセツト端子との間に信
号経路を設けてなるコンピユータの電圧監視回路
。 (2) システム電源電圧がＣＰＵ動作保証範囲の
上限電圧を越えた場合にのみオンとなる第１の電
圧検出回路と、該システムの電源電圧が該ＣＰＵ
動作保証範囲の下限電圧未満になつた場合にのみ
オフとなる第２の電圧検出回路と、該第１の電圧
検出回路の出力端子に制御端子を接続されて上記
システム電源電圧が上記上限電圧を越えた場合に
のみオンとなる第１のスイツチング素子と、シス
テム電源と該第１のスイツチング素子との間に接
続された第１の抵抗と、該第１のスイツチング素
子と該第１の抵抗との間に制御端子を接続され、
上記第１の電圧検出回路のオフ及び上記第２の電
圧検出回路のオンによりオン、上記第１及び第２
の電圧検出回路のオンによりオフ、上記第１及び
第２の電圧検出回路のオフによりオフとなるよう
に該制御端子を制御されてＣＰＵに上記システム
電源電圧を印加する第２のスイツチング素子と、
上記システム電源電圧が上記下限電圧未満になつ
た場合にＣＰＵにリセツトをかける回路とを有す
るコンピユータの電圧監視回路において、 前記第２の電圧検出回路の出力端子と、前記第
１の抵抗と前記第１のスイツチング素子との接続
点との間に、前記システム電源電圧が前記上限電
圧を越えたときに前記第２の電圧検出回路の出力
電流が前記第１のスイツチング素子を介してアー
スされないように阻止する電流阻止回路を接続し
、 前記リセツトをかける回路として、前記第２の
電圧検出回路の出力端子と上記電流阻止回路との
接続点と、前記ＣＰＵのリセツト端子との間に信
号経路を設け、更に、前記第１の電圧検出回路の
出力端子と前記第１のスイツチング素子との間に
第２の抵抗を接続し、 前記システム電源と前記ＣＰＵの電源端子との
間で前記第２のスイツチング素子と並列に、前記
第１の電圧検出回路の出力によつてオン、オフ制
御されるレギユレータを接続してなるコンピユー
タの電圧監視回路。[Claims for Utility Model Registration] (1) A first voltage detection circuit that turns on only when the system power supply voltage exceeds the upper limit voltage of the guaranteed CPU operation range;
A second voltage detection circuit that turns off only when the voltage falls below the lower limit voltage of the guaranteed operation range, and a control terminal connected to the output terminal of the first voltage detection circuit so that the system power supply voltage exceeds the upper limit voltage. a first switching element that turns on only when the voltage is exceeded; a resistor connected between the system power supply and the first switching element; and a control terminal connected between the first switching element and the resistor. connected, turned on when the first voltage detection circuit is turned off and the second voltage detection circuit turned on, turned off when the first and second voltage detection circuits are turned on, and the first and second voltage detection circuits are turned on. a second switching element that applies the system power supply voltage to the CPU by controlling the control terminal so as to be turned off when the system power supply voltage is turned off when the system power supply voltage becomes lower than the lower limit voltage;
In the voltage monitoring circuit for a computer, the system power supply voltage is connected between the output terminal of the second voltage detection circuit and a connection point between the resistor and the first switching element. a current blocking circuit is connected to prevent the output current of the second voltage detection circuit from being grounded via the first switching element when the voltage exceeds the upper limit voltage; A voltage monitoring circuit for a computer, wherein a signal path is provided between a connection point between the output terminal of the second voltage detection circuit and the current blocking circuit, and a reset terminal of the CPU. (2) A first voltage detection circuit that turns on only when the system power supply voltage exceeds the upper limit voltage of the guaranteed CPU operation range;
A second voltage detection circuit that turns off only when the voltage falls below the lower limit voltage of the guaranteed operation range, and a control terminal connected to the output terminal of the first voltage detection circuit so that the system power supply voltage exceeds the upper limit voltage. a first switching element that turns on only when the voltage is exceeded; a first resistor connected between the system power supply and the first switching element; and a first switching element and the first resistor. The control terminal is connected between
When the first voltage detection circuit is turned off and the second voltage detection circuit is turned on, the first and second voltage detection circuits are turned on.
a second switching element that applies the system power supply voltage to the CPU by controlling the control terminal so as to be turned off when the voltage detection circuit is turned on and turned off when the first and second voltage detection circuits are turned off;
A voltage monitoring circuit for a computer including a circuit for resetting a CPU when the system power supply voltage becomes less than the lower limit voltage, the output terminal of the second voltage detection circuit, the first resistor and the first resistor. between the connection point and the first switching element so that the output current of the second voltage detection circuit is not grounded through the first switching element when the system power supply voltage exceeds the upper limit voltage. A signal path is provided between a connection point between an output terminal of the second voltage detection circuit and the current blocking circuit, and a reset terminal of the CPU, as a circuit for connecting a current blocking circuit for blocking and applying the reset. Further, a second resistor is connected between the output terminal of the first voltage detection circuit and the first switching element, and the second switching element is connected between the system power supply and the power supply terminal of the CPU. A voltage monitoring circuit for a computer comprising a regulator connected in parallel with the element to be turned on and off by the output of the first voltage detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4626290U JP2522689Y2 (en) | 1990-04-27 | 1990-04-27 | Computer voltage monitoring circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4626290U JP2522689Y2 (en) | 1990-04-27 | 1990-04-27 | Computer voltage monitoring circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH048129U true JPH048129U (en) | 1992-01-24 |
| JP2522689Y2 JP2522689Y2 (en) | 1997-01-16 |
Family
ID=31561189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4626290U Expired - Lifetime JP2522689Y2 (en) | 1990-04-27 | 1990-04-27 | Computer voltage monitoring circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2522689Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4871750A (en) * | 1971-12-29 | 1973-09-28 | ||
| JP2012003565A (en) * | 2010-06-18 | 2012-01-05 | Hitachi Ltd | Electrical apparatus and method for diagnosing the same |
-
1990
- 1990-04-27 JP JP4626290U patent/JP2522689Y2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4871750A (en) * | 1971-12-29 | 1973-09-28 | ||
| JP2012003565A (en) * | 2010-06-18 | 2012-01-05 | Hitachi Ltd | Electrical apparatus and method for diagnosing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2522689Y2 (en) | 1997-01-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |