JPH0480964A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize an electron wave interference effect so as to enable a semiconductor to be easily manufactured by a method wherein N-type semiconductor regions disposed at intervals of electron de Broglie wavelengths are formed just under a gate electrode on the surface of a carrier feed layer, the length of the gate electrode in a source-drain direction is set smaller than an electron inelastic scattering length, and a Schottky electrode is formed on the rear side of a semiconductor substrate. CONSTITUTION:A Schottky electrode (back gate electrode) 8 is formed on the rear side of a non-doped GaAs substrate 1 through evaporation. A source electrode 6S and a drain electrode 6D are formed on an N-type GaAs layer 5 through evaporation and subjected to an alloy treatment so as to come into ohmic contact with external leads. A region of the N-type GaAs layer 5 surrounded with the source electrode 6S and the drain electrode 6D is partially removed through an electron beam lithography method to form a stripe pattern where N-type GaAs fine wires which are 300Angstrom or so in width, disposed at intervals of 300Angstrom or so, and whose longitudinal direction extends in a source-drain direction. Gage electrodes (Schottky electrodes) 7 500Angstrom or so in gate length are formed on a stripe pattern composed of N-type GaAs fine lines through an EB lithography method.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to the structure of a semiconductor device that utilizes the interference effect of electron waves, and particularly relates to the structure of a semiconductor device that makes it possible to simplify the manufacturing method thereof. .

(Prior Art) FIG. 6 is an element structure diagram of a semiconductor device according to the prior art. Such semiconductor devices are stored in journals and
of Applied Physics (J, Appl.

Phys, ), Volume 62, No. 4, Page 1492, 198
It was reported in 2007. In the figure, 60 is an n collector layer, 61 is a p collector layer, 62 is an in-plane superlattice layer (grating layer), 63 is a p base layer, and 64 is a p emitter layer.
Barrier layer 65 is an n emitter layer, 66 is an emitter electrode, 6
7 is a ground electrode, 68 is a base electrode, 69 is an absorber electrode, and 70 is a collector electrode. The in-plane superlattice layer 62 is formed of a structure in which two types of materials having different electron affinities are alternately arranged at a constant period in the in-plane direction. Such an in-plane superlattice layer is called a grating layer because it functions similar to a diffraction grating in light for incident electrons.

FIG. 7 shows the potential and profile in the direction from the emitter electrode 66 toward the n collector layer 60 of the semiconductor device shown in FIG. Electrons injected beyond the emitter barrier layer 64 are separated by the grating layer 62 into a transmitted component that reaches the collector layer 60 and a diffracted component that does not reach the collector layer 60. The diffracted component is absorbed by the absorber electrode 69, and the transmitted component flows into the collector electrode 70. When the number of grating periods is sufficiently large, electrons directly incident on the grating are diffracted to an angle φ given by the following equation.

where d is the period of the grating and λ is the de Broglie wavelength of the electron. Since the diffraction angle≠ is a periodic function with respect to the electron wavelength λ, by changing λ, the diffraction angle becomes
The effective collector arrival rate (a) can be modulated. Here, λ is given as a function of the injection energy E of incident electrons as shown in the following equation.

nJ where h is the Planck constant and m# is the electron effective mass. Therefore, by changing the base potential, E
By changing lnj, it is possible to modulate the collector arrival rate α.

(Problems to be Solved by the Invention) In order to obtain sufficient electron velocity in a semiconductor device with such a structure, the de Broglie wavelength λ of electrons must be several hundred Å or less, and the period of the grating must also be approximately λ or less. That is, it needs to be several hundred λ or less. Therefore, the grating layer 62 having a period of about several hundred holes is connected to the collector layer 61 and the base layer 63.
It is necessary to build in between. Moreover, in order to cause the interference effect of electron waves, it is essential to obtain a perfect crystal without lattice defects that would cause electron scattering at the base-grating interface, grating-collector interface, and within the grating. , it is extremely difficult to realize such an embedded structure of in-plane superlattices using current mechanical engineering techniques.

Furthermore, in order to cause electron wave diffraction in a semiconductor device having such a structure, the entire area including the rating layer 62 for controlling electron waves and the p base layer 63 must be within a size of about L or less. It must be made. Here, L depends considerably on temperature and electron mobility, but for n-type QaAs glue, L is 0.1 at 4.2K. am
At a level of 77, it is about 0.01 □m. That is, 10
In a multilayer structure having a film thickness and bottom area of about 0λ or less, it is necessary to expose the base layer 63 and collector layer 61 by etching and make contact with them.
This is also difficult.

The present invention provides a structure of a semiconductor device that can be easily manufactured by realizing an electron wave interference effect with a simple structure.

(Means for Solving the Problems) A semiconductor device of the present invention has a semiconductor layer structure in which a non-doped channel layer and a carrier supply layer doped with an n-type impurity are sequentially stacked on a semiconductor substrate, and a source electrode and a drain electrode are formed on the surface of the semiconductor layer structure. , a semiconductor device in which a gate electrode is formed,
Immediately below the gate electrode on the surface of the carrier supply layer, an n-type semiconductor region is formed with a period approximately equal to the de Broglie wavelength of electrons, and the length of the gate electrode in the source/drain direction is determined by inelastic scattering of electrons. A Schottky electrode is formed on the back surface of the semiconductor substrate.

(Function) The buried superlattice structure is not only difficult to fabricate, but also
For example, it is extremely difficult to obtain good crystals free of lattice defects using current processing techniques because the manufacturing process requires epitaxial growth → etching → regrowth. Therefore, in such devices fabricated using current processing technology, lattice defects that occur in the buried superlattice induce scattering of electrons, destroying the phase information of the electrons, making it almost impossible to observe the interference phenomenon of electron waves. Met. These difficulties could be avoided if a superlattice-like potential could be created in the region where electrons travel using electric field effects via electrodes formed on the semiconductor surface. Possible methods for achieving this are two methods for the structure of semiconductor devices.
In a two-dimensional electron gas field effect transistor (2DEGFET or HEMT) structure, n-type semiconductor regions are arranged in a periodic manner immediately below the gate on the surface of the electron supply layer. In such a structure, if the gate voltage is appropriately selected, an electron accumulation layer and a depletion layer are periodically formed in the channel due to the difference in interfacial potential between the electron supply layer and the gate metal and the n-type semiconductor region. , it is possible to realize a state in which depletion layer islands are lined up at regular intervals in a sea of two-dimensional electron gas (2DEC). Here, the channel directly under the gate, where electron storage regions and depletion regions are arranged alternately, has a conduction region and a potential.

This is a 2DEG since it constitutes a periodic structure in the barrier region.
It acts as a one-dimensional grating for Also,
In the present invention, since the gate electrode is coupled to the electron storage region through the n-type semiconductor layer, changing the gate voltage can change not only the depletion layer width of the depletion region but also the electron concentration in the electron storage region. This makes it possible to reliably generate an electron storage region by adjusting the gate voltage, regardless of the thickness of the electron storage layer, and improves device design.

Here, the period of the grating may be about several hundred, which is about the same as the electron wavelength. The inelastic scattering length of 2DEG is 77
Also in K 1. Since the point is about am long, the size of this point φ pole is small enough to obtain an ideal electron wave interference effect. Furthermore, by inserting a non-doped spacer layer at the interface between the carrier supply layer and the channel layer, the influence of elastic scattering (ionized impurity scattering) can also be eliminated.

Next, a method of modulating the electronic wavelength λ will be described. In conventional technology, an emitter barrier layer is provided between the base layer and the emitter layer, and the de Broglie wavelength of electrons injected into the grating is modulated by changing the potential of the emitter barrier layer via a ground electrode. . FE like the present invention
In the T structure, the energy spectrum of the electron flow (=number of electrons x electron velocity) passing through the grating has a steep peak near the Fermi level, so the electrons involved in conduction have a de Broglie wavelength corresponding to the Fermi energy EF. It may be considered that it has. However, the drain and source voltage V
Therefore, the electron injection energy s depends not only on EF7'4 but also on Vds, and since the Fermi level is a function of the sheet electron concentration n, in the semiconductor device according to the present invention, changing n Depending on this, the electron wavelength can be modulated. In the present invention, since the gate electrode is used to configure a one-dimensional grating, it is possible to easily modulate the electron wavelength by providing a back gate electrode on the substrate side and changing the substrate potential.

Further, since the semiconductor device according to the prior art has a so-called vertical transistor structure in which electrons flow in a direction perpendicular to the semiconductor layer, a process of making contact with each semiconductor layer of a multilayer structure of about 100 people was required. In the present invention, F
By adopting the ET structure, such difficulties can be avoided because the electrodes can be removed from the surface.

Furthermore, by using 2DEC with high electron mobility as a carrier, the mean free path of electrons and the inelastic scattering length can be significantly increased, so the restrictions on miniaturization of the device size φ are relaxed, making device fabrication even easier. becomes easier. In other words, it is thought that if elements of the same size are manufactured, it will be possible to operate at higher temperatures than before.

(Example) FIGS. 1(a) and 1(b) show the element structure of a semiconductor device according to an example of the present invention. FIG. 1(a) is a perspective view, and FIG. 1(b) is a sectional view along the longitudinal direction of the gate electrode. Such an element is manufactured as follows. On a non-doped GaAs substrate 1, the following epitaxial layer structure, 2,000 layers thick, a non-doped GaAs layer 2, 100 layers thick.
Human non-doped Alo, 2Gao, sAs spacer layer 3
, 200 nm thick n-type A1°, 2 Gao8 AS layer (doping concentration 3X10/cm) 4, 300 nm thick
type GaAs cap layer (doping concentration 5X10/c
m) Grow 5 in sequence.

A Schottky electrode (back gate electrode) 8 is formed on the back surface of the non-doped GaAs substrate 1 by vapor deposition. A source electrode 6S and a drain electrode 6 are provided on the n-type GaAs layer 5.
After forming D by vapor deposition, ohmic contact is established by alloying. In addition, by partially removing the n-type GaAs layer in the region sandwiched between the source electrode 6S and drain electrode 6D of the n-type GaAs cap layer 5 using electron beam (EB) lithography, the width of the n-type GaAs cap layer 5 is reduced to 300 mm. It is a striped structure in which n-type GaAs thin wires are arranged at a period of about 300 with their longitudinal direction facing the source and drain.
form a pattern. In addition, in this example, n-type GaA
In order to block the conduction in the s-layer 5 and extract only the electron conduction in the high-purity GaAs2, the n-type GaAs5 in the gate part constituting the stripe and pattern regions is insulated from the source and drain regions by removing a portion of it by etching. has been done. A gate electrode (Schottky electrode) 7 having a gate length of about 500 degrees is formed on this stripe pattern of n-type GaAs thin lines by EB lithography.

Figures 2(a) and 2(b) show the potential hand distribution directly under the gate. Figure 2 (a) is a potential distribution diagram between the gate and channel (between Xl and 71 in Figure 1 (b)) in the part where the gate electrode directly contacts the electron supply layer, and Figure 2 ( b) is a potential distribution diagram between the gate and channel (between X2 and 72 in FIG. 1(b)) in a portion where an n-type GaAs layer is interposed below the gate. As shown in Figure 2(a), the Schottky barrier height of n-type AlGaAs is as high as approximately 1 eV, so where the gate electrode directly contacts the electron supply layer, the conduction band of the channel is lifted and depleted. become On the other hand, as shown in Figure 2(b),
In a place where there is an n-type GaAs layer under the gate, the increase in the interfacial potential due to the jockey barrier increases the n-type GaAs layer.
Because it is absorbed within the As layer, n-type GaAs in the electron supply layer
The conduction band at the interface with 5 is lowered and an electron storage layer is formed.

In this way, as shown in FIG. 1(b), when an appropriate potential is applied to the gate, an electron storage layer is formed in the part of the n-type GaAs layer directly below the Schottky gate electrode 7.
There is a depletion region in the part where there is no As layer, and 1
A periodic structure of an electron storage layer and a depletion layer forms.

FIG. 3 shows the channel layer (near the hetero interface with the spacer layer 3 in the non-doped GaAs layer 2) when the drain is positively biased with respect to the source in the embodiment shown in FIG. FIG. 2 is a schematic diagram of eight potential bands in . Directly below the gate, a periodic potential is generated in the longitudinal direction of the gate, forming a one-dimensional grating. Electrons behave two-dimensionally between the source and the gate and between the source and the gate, and chemical potentials are connected under the gate through periodically arranged point contacts.

As can be easily seen from FIG. 3, electrons having Fermi energy EF at the source electrode have the following kinetic energy E3. have.

nJ Here, the Fermi level EF is a function of the substrate voltage Vb, ()' voltage applied between the gate electrode and the source electrode. It is clear from equations (1), (3), and (4) that by changing the back gate voltage V, the diffraction angle φ can be modulated to the electron wavelength, and therefore the drain arrival rate α can be changed. I can do it.

FIG. 4 is a wiring diagram showing the operating state of the semiconductor device according to the present invention. That is, when the source is grounded, the drain electrode 6
A positive voltage ds is applied to D, and an appropriate voltage ds is applied to gate electrode 7.
Apply. Here, the gate voltage Vg5s is for realizing a grating structure. If the voltage applied to the substrate electrode 8 is V, g, then V, g (7
) can change the sheet electron concentration, that is, the electron wavelength λ. As can be seen from equation (1), the electron diffraction angle φ, that is, the drain arrival rate. Since is a periodic function of the electron wavelength λ, the drain current I exhibits current-voltage characteristics as shown in FIG. As reported by Okiya, φ
Since is a steep function with respect to λ8, it is expected that a large current amplification can be obtained with a minute voltage change, and it is thought that an extremely high mutual conductance can be obtained.

In the above embodiments, the present invention was explained using an AlGaAs/GaAs FET, but the present invention is of course applicable to AlGaAs/GaAs FETs.
As/InGaAs strained system and AlInAs/GaInAs
It is also applicable to FETs made of other materials such as

(Effects of the Invention) As is clear from the above detailed description, according to the present invention, it is possible to realize a semiconductor device that can utilize the electron wave interference effect with a simple structure. By adjusting the grating, the shape of the grating can be changed, and the design of the device can be improved.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are diagrams showing the device structure of an embodiment according to the present invention, and FIGS. 2(a) and (b) are potential and hand diagrams between the gate and channel in the embodiment. , Figure 3 is a schematic diagram of the source-drain potential band in this example, Figure 4 is a wiring diagram showing the operating state of this example, and Figure 5 is the current and voltage characteristics in this example. 6 is a diagram showing the element structure of a semiconductor device according to the prior art, and FIG. 7 is a potential profile diagram between the emitter and the collector in the conventional example. In the figure, 1... non-doped GaAs substrate, 209
．． Non-doped GaAs layer, 3... non-doped AlGa
As layer, 4. n-type AlGaAs layer, 5-n-type GaAs layer, 68.6D-6, ohmic electrode, 7,8... Schottky electrode, 60... n-type collector layer, 61, p-type collector layer, 62. ...Grating layer, 63...
p-type base layer, 64...p-type emitter barrier layer, 65
... n-type emitter layer, 66 ... emitter electrode, 67
... ground electrode, 68 ... base electrode, 69 ... absorber electrode, 70 ... collector electrode.

Claims (1)

[Claims] A semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on the surface of a semiconductor layer structure in which a non-doped channel layer and a carrier supply layer doped with an n-type impurity are sequentially laminated on a semiconductor substrate, the carrier supply layer Immediately below the gate electrode on the layer surface, an n-type semiconductor region is formed with a period approximately equal to the de Broglie wavelength of electrons, and the length of the gate electrode in the source and drain directions is equal to or less than the inelastic scattering length of electrons. A semiconductor device, further comprising a Schottky electrode formed on the back surface of the semiconductor substrate.