JPH048017A - Ad converter - Google Patents

Abstract

PURPOSE:To employ a digital circuit only for circuit control switching resolution by providing an integration circuit to replace a measured voltage into time and using a time signal obtained by an integration circuit so as to control a counter. CONSTITUTION:When a voltage inputted to an integration circuit 11 rises gradually, a gate time of a counter 14 gets longer in proportion to the input voltage and the count of the counter is increased in proportion to the gate time. When the increased count reaches a setting value 1000, the clock given to the counter is replaced into a frequency-divided clock. Thus, the count is 100 which is 1/10 of the setting value 1000 and the resolution is similarly decreased to 1/10. When the input voltage is decreased, the count of the counter is decreased in response to the input voltage and when the count reaches a setting value 90 and the clock is replaced into a clock not subject to frequency division, the counter reaches 900 being a multiple of 10 and the resolution is increased by a multiple of 10 with the same input voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resolution switching method in a double-integration type AD converter.

[Prior Art] In a conventional double-integration type AD conversion circuit, when attempting to obtain n-times resolution, the input resistance of the integrator is n-fold lower than the resistance value during normal measurement during the first integration period. By multiplying by 1, the voltage at the end of the first integration reaches the same voltage as during normal measurement with 1/n of the input voltage during normal measurement. By performing second integration under the same conditions during normal measurement and high-resolution measurement, results with the same number of counts can be obtained. The weighting of the least significant digit at this time is 1/n of the normal measurement value when the first integration is performed with an input resistance of 1/n, and therefore the resolution is n times higher. Become.

The method using input resistance switching has been described above, but
Similar results can be obtained by switching the integrating capacitor.

[Problems to be Solved by the Invention] However, in such a conventional method, since the analog circuit system is switched, when the resistance is switched, the input impedance of the integrating circuit changes, and the input impedance It is connected in series with the voltage error due to the bias current that occurs due to the change in the input resistance, and the input resistance. Errors occur due to the resistance of the semiconductor or mechanical switch. Similarly, even when the capacitor is switched, the resistance of various switches connected in series with the capacitor causes problems such as the generation of a dead zone near zero input.

The object of the present invention is to provide an AD converter that eliminates such problems and enables resolution switching without causing errors.

[Means for Solving the Problems] As shown in the circuit diagram of FIG. 1, the resolution switching method in the AD converter of the present invention includes an integrating circuit 11 for measuring the voltage to be measured in terms of time, and a reference clock 12. , a frequency dividing circuit 13 for converting the reference clock to an arbitrary frequency.
, a counter 14 controlled by a time signal obtained by the integrating circuit, and the circuit control for switching the resolution is performed only by a digital circuit.

[Function] According to the above configuration of the present invention, when the input value of the AD conversion circuit gradually increases, the gate time increases in proportion to this value, and the number of clocks passing through the gate increases. will also increase proportionately.

Here, by setting the number of clocks to an arbitrary value and dividing the clock and giving it when the number of clocks reaches the set value, the number of clocks will decrease by the division ratio, and the resolution will increase by that amount. will change.

Furthermore, when the input value gradually decreases, it is possible to obtain a resolution twice the frequency division ratio by stopping frequency division and directly applying a clock when an arbitrary clock is reached.

[Examples] Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 is a circuit configuration diagram in an embodiment, where 1] is a double integration type integrating circuit, 12 is a reference clock, and 13 is a frequency dividing circuit for dividing the frequency of the reference clock. Assume that the frequency is divided by l/10. 14 is a counter controlled by the time signal obtained by the integration circuit. Here, select an arbitrary value for resolution switching (
The operation will be described below, assuming that the count number is 1000, the resolution town value is 1000, and the resolution increase value is 90.

When the voltage input to the integrating circuit 11 gradually increases, the gate time of the counter 14 becomes longer in proportion to the input voltage, and the value of the counter increases in proportion to the gate time. The reference clock at this time is set so that an undivided clock is given.) When the increasing counter value reaches the set value i ooo, the clock given to the counter is divided. By switching to , the counter value becomes 100 of 1/lO.
becomes. From then on, the counter value increases in proportion to the increase in input, but the rate of increase is 1/10 of that before the clock was switched, and the resolution is also ]/10. From this state, As the input value is lowered, the value of the counter decreases according to the input value (When the value of the counter reaches the set value of 90, the clock given to the counter is switched to one that does not divide the frequency. in,
The value of the counter is 10 times higher, 900, which means that the resolution has increased 10 times for the same amount of human power. From then on, as the input decreases, the counter value also decreases.
As a result, a two-range automatic gain switching type AD converter can be constructed.

Applying this, the caraton up value and countdown value can be set to arbitrary values, and by changing the gate time and the maximum count number, the width (optimum value for various measurements can be set).

Further, in the above-mentioned embodiment, frequency division switching is performed in two stages, but by setting these to 3 Pl and 41B, switching of multiple ranges can be made possible.

Also, as another method, by setting the frequency division ratio to an arbitrary value, for example, if you set the frequency division ratio to a value that will display l after 254 counts, you can convert 25.4 mm to 1 inch. is also possible.

[Effects of the Invention] As described above, according to the present invention, since there is no circuit switching of the double integral analog circuit system, the input impedance seen from the input side can always be kept constant. Therefore, even if the resolution of the double integration circuit is changed, errors due to bias current etc. appear quantitatively, so it can always be dealt with with constant correction. In other words, there is no need for correction every time the resolution is switched.

Also, since there is no change in series resistance of the capacitor,
There is no change in the dead zone near zero input when the resolution is switched.

Furthermore, since the input resistance and the integrating capacitor are always constant, even when the resolution is switched, the response speed of the analog circuit system does not change and can always be kept constant.

As a result of the above effects, even in the circuit connected to the AD converter, correspondence to input impedance changes and response speeds of the AD converter does not have to be changed for each condition, resulting in overall simplification of the circuit.

Cause.

Cause.

Figure 2 shows Circuit structure of conventional AD converter ]1.21...Integrator circuit 12.22...Reference clock 13... Frequency divider circuit 14.24...Counter 15.25...Control circuit 16.26... Gate Applicant: Seiko Epson Corporation Agent: Patent attorney Kisanbe Suzuki (1 person)

[Brief explanation of drawings]

Claims (1)

[Claims] In a double integration type AD conversion circuit, a comparator operates in synchronization with the second integration period, and a circuit that counts clocks passing through a gate circuit controlled by the comparator, the frequency of the clock passing through the gate. An AD converter characterized in that the resolution of an AD conversion result can be switched by changing the .