JPH0479585A - Television system conversion circuit - Google Patents

Abstract

PURPOSE:To convert a television system to a different one with simple constitution by prohibiting unrequired information to be written on a memory means by a mask in a second television system out of first and second television systems in output with the second television system or system conversion. CONSTITUTION:The mask means 22 which masks a first clock to be applied to the write clock input of the memory means 20 at a prescribed timing is provided. The read/write of the memory means 20 is performed by the first clock when the output with the first television system is issued. The write on the memory means 20 is performed by the first clock masked by the mask means 22 when the output with the second television system is issued, and also, readout from the memory means 20 is performed by a second clock. Thereby, television system conversion to obtain the video signals of plural television systems from one image pickup device can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television format conversion circuit for obtaining video signals of a plurality of television formats from one imaging device.

[Prior art] Television systems include NTS C system, PAL system,
There are SECAM systems, etc., and these have different video synchronization signal standards. For example, as shown in FIG.
The standard has 625 scanning lines and a horizontal scanning period of 64 μs, whereas the NTSC standard has 525 scanning lines and a horizontal scanning period of 635 μs. Because of these differences, video equipment, such as movie cameras, electronic still cameras, and video recording and playback equipment, are manufactured based on a single television system. The device did not allow different types of video signal output.

However, in recent years, as people have become more mobile, there has been a demand for inexpensive video equipment and format conversion devices that can output from multiple television formats.

Therefore, it is an object of the present invention to provide a television format conversion circuit for obtaining video signals of a plurality of television formats from one imaging device.

[Means for Solving the Problems] A television format conversion circuit according to the present invention converts an image taken by an imaging means having a number of pixels corresponding to a first television format into a first television format and the first television format. In an imaging device capable of selectively outputting a video signal of a second television system having a smaller number of pixels than that of the first television system, the first television system comprises a memory means capable of storing an image taken by the imaging means; masking means for masking the first clock applied to the write clock input of the memory means at a predetermined timing when the second television system outputs the first clock; When the first television system is output, the first clock is used to write and read data into the memory means, and when the second television system is output, the first clock masked by the mask means is used to write and read data into the memory means. At the same time, the second
It is characterized in that the reading from the memory means is carried out using the clock.

[Operation] - According to the grasping means, when outputting the second television system or converting the system, unnecessary pixel information in the second television system of the first television system is removed by the masking means. Writing to the memory means is prevented, and stored data is read from the memory means using a continuous second clock. The circuit configuration is simple because it only requires clock switching and masking.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention applied to a video camera. 10 is a photographing lens, 12 is a solid-state image sensor, and 14 is a sample hole (S/I-1
) circuit, 16 is automatic gain adjustment circuit (AGC), 18 is A
/D converter, 20 is memory, 21 is r'AL/N specifying the output television system (PAL or NTSC)
Input of TSC mode signal: ^1 child, 22 is a clock generation circuit, 26 is a D/A converter that converts the digital signal read from the memory 20 into an analog signal, 28 is a brightness processing circuit, 30 is a color processing circuit circuit, 32 is the brightness processing circuit 2
8 and the output of the color processing circuit 30 to an NTSC television system component [...an NT that forms and outputs a video signal].
The SC encoder 34 is a PAL encoder that forms and outputs a PAL television system composite video signal from the outputs of the brightness processing circuit 28 and color processing circuit 30.

In general, the sampling frequency of the image sensor should be set to an integer multiple of the color subcarrier frequency fsc so that the beat disturbance between the summing clock and the color video signal is minimized, and the sampling frequency of the image sensor It is easier to perform image processing if the sample points of the images match vertically and horizontally as well as between frames.

Therefore, the sampling frequency is often set to an even multiple of fsc. For example, when the sampling frequency is 4fsc, in the PAL method widely used in Europe,
The frequency of the color subcarrier f psc = 4.43 MHz is 4 f psc = 17.73 MHz. On the other hand, in the NTSC system used in Japan, the United States, etc., the frequency of the color subcarrier f n5c = 3.58 MHz. 4fnsc=14.43MHz is selected for. Therefore, the number of horizontal pixels for P A L and NTSC systems is 4 f pscX 64 μs = 1], 35, and 4, respectively.
f n5cX63.5μs = 910, and the number of vertical scanning lines is 625 (PAL) and 525 (NTS
C). The total number of pixels is 135X for PAT one system.
625, 910x525 in the NTSC system, and as shown in FIG. 2, the PAL system is more common. This implementation =
6 For example, an image sensor 12 having a PAL pixel count may be used, and the NTS
It is also possible to obtain a C-type output signal.

FIG. 3 shows a specific circuit example of the clock generation circuit 22. An oscillator 40 generates a clock with a frequency four times the subcarrier frequency fpsc of the PAL system, and an oscillator 42 generates a clock four times the frequency of the color subcarrier frequency fnsc of the NTSC system.

44 is a counter for generating a mask signal Vmask that masks the output clock of the oscillator 40 in the vertical direction when outputting the N'FS C method, and 46 masks the output clock of the oscillator 40 in the horizontal direction when outputting the N'rS C method. A counter for generating the mask signal I-Tmask, 48 an AND gate, 50 PAL/NTS
This is a switch that is switched by a C mode signal. The switch 50 is connected to the a contact when specifying the PAL/NTSC mode signal or the PAL system, and is connected to the b contact when specifying the NTSC system. In Figure 3, P
A L I (sync is the horizontal synchronization signal of the PAL system, and PAL Vsync is the vertical synchronization signal of the PΔI system.

First, the operation when it is desired to obtain a PAL system output using the apparatus shown in FIG. 1, that is, when specifying a PAL/NTSC mote signal input to the input terminal 21 will be described. The image sensor 12 converts the optical image formed by the photographing lens 10 into an electrical signal, and the electrical signal is read out in accordance with a sampling clock SCK having a frequency of 4 fpsC from a clock generation circuit 22. The S/H circuit 14 samples and holds the output of the image sensor 12 using the clock SCK, and the AGC circuit 16 automatically adjusts the output level of the S/I (circuit 14 to an appropriate value).
is the AGC according to the sampling clock SCK.
The output signal of circuit 16 is converted into a digital signal.

In the PAL mode, the switch 50 in FIG. 3 is connected to the a contact side, and the read clock WCK generated by the clock generation circuit 22 has a frequency of 4 f p
This is the sc clock. The output data of the A/D converter 18 is transferred to the memory 20 according to this write clock WCK.
will be written to. The read clock RCK generated by the clock generation circuit 22 is also a clock with a frequency of 4 f psc from the PAL oscillator 40, and the data stored in the memory 2o is read out by this read clock RCK, and the data stored in the memory 2o is read out. The converter 26 converts it into an analog signal.

That is, the output signal of the D/A converter 26 is
6. substantially corresponds to the output signal of 6.

The output signal of the D/A converter 26 is subjected to luminance processing by a luminance processing circuit 28, color processing is performed by a color processing circuit 80, and P
A L is converted into a FAT composite video signal by an encoder 34.

Next, the operation of the NTSC mote will be explained with reference to FIGS. 4 and 5. FIG. 4 shows a horizontal timing diagram, and FIG. 5 shows a vertical timing diagram. Image sensor 1
2 to A/D converter 18 are the same as a double PAL mote. Since the A/D converter 18 operates with a sampling clock compatible with PAL, the time position of the synchronization signal is shifted. The temporal position shift of this synchronization signal is 1135 clocks per horizontal scanning period in the PAL system.
In contrast, the number of horizontal pixels in the NTSC system is 910 (63,5
μs), i.e. 4 f psc and 9
It is sufficient to write to the memory 20 for 10 clocks (51.4 μS) and stop writing to the memory 20 for the remaining 225 clocks (126 μs at 4 fps).

In addition, the vertical synchronization signal is 625/2 in the PAL system.
1-I, NTSC system, it occurs every 525/21-I, so similarly, PAL system's 525/2
Writing to the memory 20 is allowed only during the scanning period of T-1, and during the remaining scanning period of 100/2H, the writing to the memory 201-(
All you have to do is stop writing.

A simple explanation of the operation in Figure 3 in NTSC mode is as follows:
The counter 44 receives a PAL vertical synchronization signal V5sync.
It starts counting the horizontal synchronizing signal l-l5ync of the PAL system in synchronization with , and when the number of horizontal scanning lines (263) of one field of the NTSC system has been counted, a Vmask signal (low) is output. By inputting the next vertical synchronization signal, V m
The ask signal becomes high, and after resetting the counter value = 10-, counting of the horizontal synchronization signal I-Tsync is started. In this way, as shown in FIG. 5(3), a vertical mask signal Vmask is obtained which masks a period of 100/21 (period).

Further, the counter 46 receives the horizontal synchronization signal J of the PAL system.
- In synchronization with Tsync, start counting the output clock (frequency 4fpsc) of the PAI oscillator 40, and count the number of horizontal pixels in the NTSC system (910 for 4fnsc).
After counting the same number (514 μS at frequency 4 f psc), the Hmask signal (low) is output. The input of the next horizontal synchronization signal causes the 1-■mask signal to go high, and after resetting the counter value, the horizontal synchronization signal H
Start counting sync. In this way, the fourth
As shown in Figure (3), 225 (= 1135-91
0) Horizontal mask signal I-Tmas that masks the clock
k is obtained.

The mask signal Vmask I- obtained in this way
1mask and the output clock of the PAL oscillator 40 are input to the AND gate 48, and from the output of the AND gate 48, only the signal portion of the output of the image sensor 12 necessary for constructing an NTSC screen is output. , memory 20
A write clock WCK for writing can be obtained.

In this way 1. The image data written to the memory 20 by the write clock WCK obtained by
f nsc read clock R, CK (, Fig. 4 (
4)), and the D/A converter 26 converts it into an analog signal using the read clock RCK as a sampling clock. The output of the D/A converter 26 is subjected to brightness processing and color processing in a brightness processing circuit 28 and a color processing circuit 30.
The NTSC encoder 32 converts the signal into an NTSC composite video signal.

In the above configuration, the aspect ratio is 1 in PAL mode.
:1.202, whereas in the NTSC mode it is 1:1.248, resulting in an error of about 46%.

However, it is hardly noticeable on the screen, so it is not a problem.

In the above embodiment, by masking the latter half of the horizontal scanning period and vertical scanning period of the PAL signal, the
Although an attempt was made to obtain a signal of the C method, such a configuration uses a certain portion of the imaging surface of the image sensor 12, that is, the photoelectric conversion surface.

To deal with this, the counters 44 and 46 are configured with a plurality of counter stages (11 to 11) to generate horizontal mask signals on the right and left sides of the horizontal scanning period, and generate horizontal mask signals on the right and left sides of the horizontal scanning period.
If a vertical mask signal is generated at the second and lower sides,
Any part of the video signal can be converted from PAL to NTSC. FIG. 6 shows a vertical timing diagram comparing before and after such a change, and FIG. 7 shows a horizontal timing diagram.

For example, in the case of a vertical synchronization signal, as shown in FIG. 6 (3), the field blanking period (25 I
-1), the first vertical mask signal Vmaskl is generated for a certain period, and then, after a period of 238H, the second vertical mask signal ■mask2 is generated. The total mask period of the first and second vertical mask signals is set to 50 I]. By adjusting the distribution of each mask period of the first and second vertical mask signals,
On the imaging surface of the image sensor 12, the position of the area used for the NTSC system can be arbitrarily set up or down between 0 and 50)T. Note that the first vertical mask signal Vmaskl is generated during the field blanking period (20
It may also be started after counting 201 (count) from the vertical synchronizing signal of the PAL system.

In this case, the total mask period with the second vertical mask signal V mask2 is set to 55H. At this time, on the imaging surface of the image sensor 12, the position of the area used for the NTSC system can be arbitrarily set between 0 and 50 I-I. It can be set arbitrarily between 5H and 5H.

Similarly to the horizontal synchronizing signal, as shown in FIG. 7(3), after counting the horizontal blanking period (212 clocks), the first horizontal mask signal Hmaskl for a certain period is generated, and then after 698 counts, the first horizontal mask signal Hmaskl is generated. , generates a second horizontal mask signal Hmask2. Then, the total mask period of the first and second horizontal mask signals is set to be 225 clocks, as in the case described with reference to FIG. By adjusting the allocation of each mask period of the first and second horizontal mask signals, the position of the area used for the NTSC method on the imaging surface of the image sensor 12 can be adjusted between 0 and 225 clocks. You can set it to the left or right as you like.

In the second embodiment, PAL mode and N'T''
In both SC modes, a frequency four times the frequency of each color subcarrier is used as the sampling frequency, so the aspect ratio of one pixel is not 1:1. In fields that do not need to handle composite video signals, such as image processing and still cameras (so-called card cameras) that digitally record captured image signals on memory cards, the sampling frequency is set to the color subcarrier frequency. There is no need to multiply it by an integer. Moreover, from the viewpoint of image processing, it is easier to handle when the aspect ratio of one pixel is 11. Next, an embodiment in which the aspect ratio of pixels is maintained at 1:1 will be described.

In the case of the NTSC system, the vertical blanking period is 20I-1, so the number of effective scanning lines is 485 (-525-20X2
), and since the aspect ratio on a normal TV screen is 3:4, the effective number of horizontal pixels is 485×4/3. Therefore, the total number of pixels in the horizontal direction is 485X 4/ 3X 63.5/ (63,5-10
,9) becomes #780. This relationship is illustrated in FIG. This changes the sampling frequency to 780/63.
When 5μ5=12.294MHz, the aspect ratio of the second pixel on the screen becomes 1:1.

In the case of the PAL method, the vertical retrace period is 258, so the number of effective scanning lines is 575 (= 625-25X 2
), and since the aspect ratio on a normal TV screen is 3:4, the effective number of horizontal pixels is 575x 4/3.

Therefore, the total number of pixels in the horizontal direction is 12μ during the horizontal blanking period.
If it is s, then it becomes 575X4/3X64/ (64-12) #943. This relationship is illustrated in FIG. This reduces the sampling frequency to 943/64μs = 14.74
When set to MHz, the aspect ratio of one pixel on the screen becomes 1.1.

From the following relationship, in NTSC mode, P as shown in Figure 3.
The oscillation frequency of the AL oscillator 40 is 14,74MHz.
At the same time, the oscillation frequency of the N780 oscillator 42 is set to 12
．． 29MHz, and its output clock is shown in Figure 10 (2).
Memory 2 is controlled by the clock masked with the mask signal shown in
When writing to 0 and reading from the memory 2o, if the output clock of the N780 oscillator 42 is supplied to the memory 2o as a read clock, the output of the memory 20 or the D/Δ converter 26 will have approximately the same aspect ratio. Almost finished:
1, an image signal conforming to the NTSC system can be obtained. 625/525# 1.19 in vertical direction, 14 in horizontal direction, 74MHz Noah 80 clock is 52.94μs
Therefore, 63.5152.94 = 1.199,
The aspect ratio of one pixel is approximately 1:1.

In this way, since the sampling clock is set to a frequency other than an integer multiple of the color subcarrier frequency, in order to obtain a composite video signal from this, the encoder 32, 34
However, when recording on a recording medium in the form of luminance and color difference signals or RGB signals, the encoders 28 and 30 are not necessary, and other luminance and color difference inputs or RGB inputs are required. A composite video signal can be obtained using a composite output device.

In the following, conversion from PAL system to NTSC system has been explained, but conversion from SECAM system to NTSC system can also be realized in the same way.

[Effects of the Invention] As can be easily understood from the above description, according to the present invention, conversion to different television formats is possible with a simple configuration.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the configuration of an embodiment of the present invention, Fig. 2 is a screen comparison diagram of NTSC and PAL systems, and Fig. 3 is a block diagram of an embodiment of the present invention.
An example of the clock generation circuit 220 in the figure, Figure 4 is NT
Horizontal timing diagram in SC mode, Figure 5 is NT
Vertical timing diagrams in SC mode, Figures 6 and 7 are vertical and horizontal timing diagrams, respectively, for an example of changing the memory write mask position in NTSC mode, and Figure 8 is a timing diagram for an example with an aspect ratio of 1. FIG. 9 is a screen configuration diagram of the NTSC system that satisfies the aspect ratio of 1:1, FIG. 9 is a screen configuration diagram of the PAL system that satisfies the aspect ratio of 1:1, and FIG. 10 is a timing chart for obtaining pixels with an aspect ratio of 1.1. 10: Shooting lens 2: Image sensor 14: Sample/hold circuit 16: Automatic gain adjustment circuit (AGC)
18: A/D converter 20/memory 21: P
AL/NTSC mode signal input terminal 22; clock generation circuit 26 + D/A converter 28: brightness processing circuit 3
0: Color processing circuit 32NTSC encoder 34:PA
L encoder 40: PAL oscillator 42: NTSC oscillator 4446: Counter 48: AND gate 50
·switch

Claims (1)

[Claims] An image captured by an imaging means having a number of pixels corresponding to the first television system is used as a video signal of the first television system and a second television system having a smaller number of pixels than the first television system. An imaging device capable of selectively outputting images includes: a memory means capable of storing images captured by the imaging means; a first clock having a frequency corresponding to the first television system; and a first clock corresponding to the second television system. a clock generating means for generating a second clock having a frequency of 1, and a masking means for masking the first clock applied to the write clock input of the memory means at a predetermined timing when outputting in the second television format. When the first television system is output, writing and reading are performed in the memory means using the first clock, and when the second television system is output, the memory means is written and read using the first clock masked by the masking means when outputting the second television system. A television system conversion circuit characterized in that it writes data into the memory means and also reads data from the memory means using a second clock.