JPH047871A - Gate spreading system gate array - Google Patents

Abstract

PURPOSE:To obtain a cell capable of changing function and characteristics of the cell only by changing a first aluminum wiring in the cell, by using gate isolation. CONSTITUTION:Contacts 13, through holes 14, and second aluminum wirings 16 are all arranged in the same positions; a NAND gate is constituted of transistors PTr1, PTr2, NTr1, and NTr2; transistors PTr0, PTr4, NTr0, and NTr4 are used as gate isolation. When the function as a NAND gate is required, transistors PTr3 and NTr3 are unnecessary; by using a first aluminum wiring 15, a contact C5 is connected with a power supply 17b, and a contact C6 is connected with ground 18b; transistors PTr3 and NTr3 are turned into OFF- transistors and a gate isolation is constituted. Thereby the logic can be inverted from a NAND gate to an AND gate, only by changing the first aluminum wiring 15.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a gate array with a gate filling method, and in particular, by using gate isolation, the function of a cell can be improved.
The present invention provides a gate array using a gate filling method whose characteristics can be changed.

[Conventional technology] Semi-custom LSIs are LSIs that are developed according to the specifications and performance requirements of specific users, but are manufactured by partially standardizing the manufacturing process for a wide variety of products.A typical example of this is gate arrays. There is.

FIG. 12 is a plan view schematically showing the chip structure of the gate array.

In the figure, (1) is an LSI chip, (2) is an internal logic section, and (3) is a buffer circuit section. Internal logic section (2) configured at the center of this LSI chip (1)
The transistors are formed in an array, and constitute a logic circuit. Depending on the arrangement of the transistors in the internal logic section (2), gate arrays can be divided into two types: a gate-covering method and an oxide film separation method.

FIG. 13 is a partially enlarged view showing a part of the transistor array in the internal logic section (2) of the gate-stuffed CMOS gate array. In the figure, (4) is the gate of a transistor, which is spread throughout the internal logic section (2) in the gate array of the gate spreading method.

FIG. 14 is a schematic plan view showing a part of the structure of a cell formed in the internal logic section (2) of a MOS gate array using the conventional gate filling method. In the figure, (5) is P
Channel transistor row, (6) is N-channel transistor row, (7) is power supply, (8) is ground, (9) is contact, (lO) is through hole, (11) is first aluminum wiring, (12) indicates the second aluminum wiring, which constitutes a two-manpower NAND gate circuit. However, in this gate array method, the power supply (7
) Two glands (8) each, (71),
They are arranged as (72), (81), and (82).

The latch-up resistance can be increased by arranging the power supply (72) and ground (82).

FIG. 15 is a transistor circuit diagram of a conventional CMO52 manual NAND gate. In Figures 14 and 15,
P-channel transistors PTrl, PTr2, N-channel transistors NTrl, NTr2, input bin A-
B and output pin Y correspond to each other.

In FIG. 14, the gates of P-channel transistors PTrO and PTr3 at both ends of the cell are connected to a power supply (71) through contacts CI and C2, respectively. Similarly, N-channel transistors NTrO and NTrO, N
Tr3 is also grounded (
81). These contacts C+, C
2, C3, and C4 are transistors PTrO and PT, respectively.
r3゜NTrO, NTr3 is an off transistor, 2
The inside and outside of the human-powered NAND cell are separated.

In this manner, in the gate array of the gate filling type, the cell and the transistors on both sides are separated using off transistors. And transistors PTrO, PTr3
．． Off-state transistors such as NTrO and NTr3 are particularly referred to as gate isolation.

In addition, in a gate array, a pair of one P-channel transistor and one N-channel transistor is called a basic cell, but the number of basic cells from one side of the cell to the front of the other side is the number of basic cells in the cell. It is called the number of constituent basic cells. The number of basic cells constituting the cell in FIG. 14 is three.

[Problems to be Solved by the Invention] Since the conventional gate-covering type gate array is configured as described above, it is difficult to determine the pattern within the cell, that is, the contact, through hole, first aluminum wiring, and second aluminum wiring. There was only one type of placement information. In other words, one cell could only have one function or characteristic.

For this reason, if the desired functions and characteristics could not be obtained, it was necessary to replace the cell with another cell. This is especially
This has become a problem when it is not desired to change the location of cells within an LSI chip or the wiring between cells for reasons such as critical paths.

This invention was made in view of the above-mentioned problems, and it provides a gate array using gate isolation, whose functions and characteristics can be easily changed by simply changing the wiring within the cell. The purpose is to obtain.

[Means for Solving the Problems] The gate array according to the present invention provides gate isolation, and by using this gate isolation, the functions and characteristics can be easily changed by simply changing the wiring within the cell. The present invention is intended to obtain a gate array using a gate-covering method, which is equipped with cells that can perform the following steps.

[Function] The cell of the gate array type gate array according to the present invention is configured to have a plurality of pieces of information on the arrangement of the first aluminum, and the arrangement of the contacts, through holes, and second aluminum wiring is fixed, and the arrangement of the first aluminum wiring is fixed. This is achieved by using gate isolation to create cells that differ only in their arrangement.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a gate-covering method CM according to an embodiment of the present invention.
FIG. 2 is a plan view showing the configuration of a two-man powered NAND gate circuit of the OS gate array, and FIG. 2 is a plan view showing the configuration of the two-man powered AND gate circuit. In the figure, (13) is a contact, (14) is a through hole, (15) is the first aluminum wiring, (16) is the second aluminum wiring, and (17) is (17a).
) (17b), (18) is (18
The ground consists of two wires a) and (18b).

FIG. 3 is a transistor circuit diagram of a CMO52 manual AND gate.

In the CMO5 circuit, the AND gate circuit is composed of a NAND gate circuit and an inverter circuit. Two-person AND in Figure 3
The gates are connected to transistors PTrl, PTr2 . NTr
l.

It consists of a two-power NAND gate made up of NTr2 and an inverter made up of transistors PTr3 and NTr3.

In FIGS. 1, 2, and 3, P-channel transistors PTrl, PTr2 . PTr3, N-channel transistors NTrl, tLTr2. NTr3, input pin A
, B, and output bin Y correspond to each other.

In FIGS. 1 and 2, the contact (13), through hole (14), and second aluminum wiring (16) are all arranged at the same position. In other words, the first aluminum wiring (
15) in Figure 1 and the first aluminum wiring (15) in Figure 2.
) to convert the NAND gate to AND
A contact (13), a through hole (14), and a second aluminum wiring (16) are arranged so that the logic can be inverted, such as from a gate or an AND gate to a NAND gate. In addition, transistors PTrl, P
Tr2. NTrl, NTr2 are used to configure a NAND gate, and transistors PTrO, PTr4,
NTrO.

NTr4 is used as gate isolation.

When you want this cell to function as a NAND gate, use the transistor PTr3. NTr3 is unnecessary.

Therefore, contact C5 is connected to the power supply (17b), contact C6 is connected to the ground (18b), and the first aluminum wiring (15
), transistors PTr3 and NTr3 are turned off and gate isolated.

Therefore, even if an extra transistor is inserted inside the cell, that transistor is used to isolate it from the cell, so there is no extra load.

In a gate array using a gate lining method, the vertical wiring between cells passes between the gates of transistors. Therefore, even if it is inside the cell, the second aluminum wiring (16)
The area between the gates where no gate is placed is used as a wiring area. For example, in this cell, transistors PTr2.
A wiring region is between NTr2 and the gates of transistors PTr3 and NTr3. That is, in the cell according to this embodiment, the second aluminum wiring (16) is fixed, so the wiring area does not change.

Further, the contact (13) is also fixed. That is, since the contacts C+, Cz, (:3.C4) constituting gate isolation on both sides of the cell are also fixed, the number of basic cells constituting the cell is also the same, which is 4 in this case.

In this way, by using gate isolation, it is possible to obtain a cell whose logic can be inverted simply by changing the first aluminum wiring.

Further, in the above embodiment, the case of a cell whose logic can be inverted has been described, but it is also possible to construct a cell whose drive ability can be changed.

FIGS. 4, 5, 6, and 7 are plan views showing the structure of an inverter circuit of a CMOS gate array of a gate filling type according to another embodiment of the present invention. These cells are transistor circuits as shown in FIGS. 8, 9, 1O, and 11, respectively. That is, when the drive capability of the cell in FIG. 4 is set to 1, the drive capabilities in FIGS. 5, 6, and 7 are each 2.3.4 times larger.

In this embodiment as well, by using gate isolation, the contact through hole and the second aluminum wiring are fixed, and the drive capability can be changed only by changing the first aluminum wiring.

[Effects of the invention] As described above, according to this invention, by using gate isolation, it is possible to obtain a cell whose functions and characteristics can be changed by simply changing the first aluminum wiring within the cell. . In addition, since this can be achieved by changing only the first aluminum wiring within the cell, the number of basic cells in the cell configuration and the wiring area within the cell remain unchanged, so the position of the cell within the LSI chip and the cell There is no need to change the wiring between the cell and the cell. Further, the present invention has the advantage that the mask only needs to be revised in the first aluminum wiring process.

[Brief explanation of the drawing]

FIG. 1 shows a gate filling method C according to an embodiment of the present invention.
A plan view showing the configuration of a two-man powered NAND gate circuit of a MOS gate array, FIG. 2 is a plan view showing the configuration of a two-man powered AND gate circuit according to an embodiment of the present invention, and FIG. 3 is a CM
4, 5, 6, and 7 are the transistor circuit diagrams of the O52 manual AND gate; Figures 8, 9, 10, and 11 are transistor circuit diagrams of the cells in Figures 4, 5, 6, and 7, respectively, and Figure 12 is a schematic diagram of the chip structure of the gate array. FIG. 13 is a partially enlarged view showing a part of the transistor array in the internal logic section of a gate-stuffed CMOS gate array, and FIG. FIG. 15 is a schematic plan view showing a part of the configuration of a cell made by the above-described method, and FIG. 15 is a transistor circuit diagram of a conventional CMO52 manual NAND gate. In the figure, (13) is a contact, (14) is a through hole, (15) is the first aluminum wiring, (16) is the second Fulumi wiring, and (17) is a power supply consisting of two wires (17a) and (17b). , (18) indicates a ground consisting of two wires (18a) and (18b). In addition, the same symbols in the figures indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 AB Y Figure 2 AB γ Figure 3ffI-a Mrhr NTrz NThJ A/T)
4NTh II'Tn Ann /ns NTp=aN
T and J, NfkJ: N+yani J full F: J shimey 1st
Figure 3

Claims (1)

[Claims] This gate array is characterized by having gate isolation and cells whose functions and characteristics can be easily changed by simply changing the wiring inside the cells by using gate isolation.