JPH0476960A - Pressure detector - Google Patents

Pressure detector

Info

Publication number
JPH0476960A
JPH0476960A JP19129890A JP19129890A JPH0476960A JP H0476960 A JPH0476960 A JP H0476960A JP 19129890 A JP19129890 A JP 19129890A JP 19129890 A JP19129890 A JP 19129890A JP H0476960 A JPH0476960 A JP H0476960A
Authority
JP
Japan
Prior art keywords
layer
gold
diffused resistors
polysilicon layer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19129890A
Other languages
Japanese (ja)
Inventor
Yuji Hase
長谷 裕司
Mikio Bessho
別所 三樹生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP19129890A priority Critical patent/JPH0476960A/en
Publication of JPH0476960A publication Critical patent/JPH0476960A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make stable operation possible even under high atmospheric temperature by providing with gold wirings connecting between diffused resistors on a semiconductor diaphramg insulation layer and electrode pads, those connecting between diffused resistors, those connecting the electrode pads and lead posts and homogeneous gold conductors. CONSTITUTION:A silicon oxide underlayer (SiO2) 12 is accumulated on the N-type silicon (Si) substrate 11, and polysilicon layer 15 is accumulated on the insulation layer 14. When the polysilicon layer is scanned by argon laser from upper part, it becomes molten and then recrystallized as a single crystal. Polysilicon layer 15, except for parts to be used as diffused resistors, is removed by etching. Non-etched polysilicon layer parts 5 are formed as diffused resistors 15a-15d by implanting some impurity. Protection layer 20 is established with glass coating over the whole surface area gold wiring 19 being formed in the front and parts other than gold wiring 19 corresponding to wiring area as well as resist layer 24 being removed by etching.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は例えばエンジンの排気圧等の圧力を検出する
圧力検出装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pressure detection device for detecting pressure such as engine exhaust pressure, for example.

〔従来の技術〕[Conventional technology]

第4図は従来の圧力検出装置を示す平面図、第5図はそ
の断面図である。図において、1はシリコン基板の中央
部を欠除して薄肉部1aとした半導体ダイヤフラム、2
は半導体ダイヤフラム1の表面に形成した絶縁層、3は
絶縁層2上に形成した多結晶シリコン層、4は多結晶シ
リコン層3の一部に不純物(ポロン)を注入して形成し
た複数の拡散抵抗、5は多結晶シリコン層3の表面に形
成した絶縁層、6は絶縁層5を貫通して拡散抵抗4と電
極パッド間および拡散抵抗4の相互間を接続するアルミ
ニューム配線、8は電極パッド7とリードポスト9間を
接続する金線である。
FIG. 4 is a plan view showing a conventional pressure detection device, and FIG. 5 is a sectional view thereof. In the figure, 1 is a semiconductor diaphragm in which the central part of the silicon substrate is removed to form a thin part 1a; 2 is a semiconductor diaphragm;
3 is an insulating layer formed on the surface of the semiconductor diaphragm 1, 3 is a polycrystalline silicon layer formed on the insulating layer 2, and 4 is a plurality of diffusions formed by implanting impurities (poron) into a part of the polycrystalline silicon layer 3. 5 is an insulating layer formed on the surface of the polycrystalline silicon layer 3; 6 is an aluminum wiring that penetrates the insulating layer 5 and connects the diffused resistor 4 and the electrode pads and between the diffused resistors 4; 8 is an electrode; This is a gold wire that connects the pad 7 and the lead post 9.

次に動作にいて説明する。半導体ダイヤフラム1は矢印
方向からエンジンの排気圧等の外部圧力が作用すると、
その圧力の大きさに応じて変形し、この変形によって拡
散抵抗4からアルミニューム配線6、電極パッド7、金
線8を介してリードポスト9に出力される電気信号が変
り、この電気信号の変動によって圧力を検出するもので
ある。
Next, I will explain the operation. When external pressure such as engine exhaust pressure acts on the semiconductor diaphragm 1 from the direction of the arrow,
It deforms according to the magnitude of the pressure, and this deformation changes the electrical signal output from the diffusion resistor 4 to the lead post 9 via the aluminum wiring 6, the electrode pad 7, and the gold wire 8, and this electrical signal changes. The pressure is detected by

〔発明が解決しようとする課題] 従来の圧力検出装置は以上のように構成されているので
、電極パッド7において、アルミニューム配線6と金線
8の異種金属の接合が存在し、特に高温雰囲気中におけ
る異種金属の腐食差などにより、動作に不安定を生じる
という課題があった。
[Problems to be Solved by the Invention] Since the conventional pressure detection device is configured as described above, there is a bond between different metals of the aluminum wiring 6 and the gold wire 8 in the electrode pad 7, which is particularly difficult to solve in a high-temperature atmosphere. There was a problem with unstable operation due to differences in corrosion between different metals inside.

この発明は上記のような課題を解消するためになされた
もので、高温雰囲気中でも安定して動作可能な圧力検出
装置を得ることを目的とする。
This invention was made to solve the above-mentioned problems, and an object thereof is to obtain a pressure detection device that can operate stably even in a high-temperature atmosphere.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る圧力検出装置は、半導体ダイヤフラムの
絶縁層上に設けた拡散抵抗と電極パッド間および該拡散
抵抗相互間を接続する金配線と、上記電極パッドとリー
ドポスト間を接続する上記金配線と同種金属の金線とを
具備したものである。
The pressure detection device according to the present invention includes a gold wire connecting between a diffused resistor and an electrode pad provided on an insulating layer of a semiconductor diaphragm and between the diffused resistors, and a gold wire connecting between the electrode pad and the lead post. and a gold wire of the same kind of metal.

〔作 用〕[For production]

この発明における圧力検出装置は、電極パッドに金配線
と金線の同種金属を接合することにより、高温雰囲気中
でも安定して動作可能である。
The pressure detection device according to the present invention can operate stably even in a high temperature atmosphere by bonding the same metals of gold wiring and gold wire to the electrode pad.

〔実施例〕〔Example〕

以下、この発明の実施例を図面について説明する。前記
第4図、第5図と同一部分に同一符号を付して重複説明
を省略した第1図、第2図において、14は半導体ダイ
ヤフラム1の表面に形成した絶縁層、15a〜15dは
絶縁層14上に設けた拡散抵抗、18は拡散抵抗15a
〜15(lを覆う絶縁層、19は絶縁層13を貫通して
拡散抵抗15a〜15dと電極パッド7間を接続すると
ともに拡散抵抗15a〜15dの相互間を接続してブリ
ッジ構成とする金配線、20は金配線19上に形成した
表面保護層である。
Embodiments of the present invention will be described below with reference to the drawings. In FIGS. 1 and 2, in which the same parts as in FIGS. 4 and 5 are given the same reference numerals and redundant explanations are omitted, 14 is an insulating layer formed on the surface of the semiconductor diaphragm 1, and 15a to 15d are insulating layers. Diffused resistor provided on layer 14, 18 is diffused resistor 15a
~15 (an insulating layer covering l, 19 is a gold wiring that penetrates the insulating layer 13 and connects the diffused resistors 15a to 15d and the electrode pad 7, and also connects the diffused resistors 15a to 15d to each other to form a bridge configuration. , 20 is a surface protective layer formed on the gold wiring 19.

次に上記実施例の動作について説明する。半導体ダイヤ
フラム1が矢印方向から外部圧力を受けて変形すると、
この変形によりブリ・ノジ構成に接続された拡散抵抗1
5a〜15bからの電気信号も変動し、この変動によっ
て圧力を検出することができるものである。
Next, the operation of the above embodiment will be explained. When the semiconductor diaphragm 1 is deformed by receiving external pressure from the direction of the arrow,
Due to this deformation, the diffused resistor 1 is connected in a Buri-Noji configuration.
Electrical signals from 5a to 15b also fluctuate, and pressure can be detected based on this fluctuation.

以下、この発明の圧力検出装置の製造方法の1例を第3
図について説明する。N型シリコン(Si)基板11上
に厚さ500人の下敷酸化層(SiO□)12を形成し
く5T−1)、その下敷酸化層上に厚さ800人の窒化
層(SiJ4)  13を堆積する(ST−2)。
Hereinafter, one example of the method for manufacturing the pressure detection device of the present invention will be described in the third section.
The diagram will be explained. An underlying oxide layer (SiO□) 12 with a thickness of 500 nm is formed on an N-type silicon (Si) substrate 11 (5T-1), and a nitride layer (SiJ4) 13 with a thickness of 800 nm is deposited on the underlying oxide layer. (ST-2).

上記シード部11aに対応する部分を残して、窒化層1
3、下敷酸化膜12、N型シリコン基板11を順次にエ
ツチング除去する(ST−3〜5T−5)。この場合、
N型シリコン基板11のエツチング量H1は3500人
程度Tbる。
The nitride layer 1 is left with a portion corresponding to the seed portion 11a.
3. The underlying oxide film 12 and the N-type silicon substrate 11 are sequentially etched away (ST-3 to 5T-5). in this case,
The etching amount H1 of the N-type silicon substrate 11 is approximately 3,500 Tb.

継いで、残留している窒化13上のレジスト21を除去
後(ST−6)、熱酸化によってN型シリコン基板1上
に厚さT=1.1μmの酸化層14を形成後(ST−7
)、残留している窒化層13を除去し、引続き残留して
いる下敷酸化層12を除去するとともに酸化層14を0
.1μm程度エツチング除去して表面を平坦化する(S
T−8,5T−9)。
Subsequently, after removing the resist 21 on the remaining nitride layer 13 (ST-6), an oxide layer 14 with a thickness T=1.1 μm is formed on the N-type silicon substrate 1 by thermal oxidation (ST-7).
), the remaining nitride layer 13 is removed, the remaining underlying oxide layer 12 is removed, and the oxide layer 14 is removed.
.. The surface is flattened by etching away approximately 1 μm (S
T-8, 5T-9).

しかる後、上記酸化層14上にポリシリコン層15を厚
さ5000人堆積しく5T−10)、その上に窒化層1
6を厚さ500人堆積しく5T−11)、この窒化層1
6をストライプ上に残るようにレジスト22をエツチン
グ除去して反射防止層17を形成する(ST−12,5
T−13)。
Thereafter, a polysilicon layer 15 is deposited to a thickness of 5000 on the oxide layer 14 (5T-10), and a nitride layer 1 is deposited thereon.
6 to a thickness of 500 mm (5T-11), and this nitride layer 1
The resist 22 is etched away so that 6 remains on the stripe to form an antireflection layer 17 (ST-12, 5
T-13).

継いで、上部より不図示のレーザ(アルゴンレーザ)を
照射、走査し、上記ポリシリコン層15を熔融させた後
、単結晶に再結晶化させる(ST−14)。この後、上
記反射防止層17、窒化層16を除去する(ST−15
)。
Subsequently, a laser (not shown) (argon laser) is irradiated and scanned from above to melt the polysilicon layer 15 and then recrystallize it into a single crystal (ST-14). After that, the antireflection layer 17 and the nitride layer 16 are removed (ST-15
).

上記再結晶化されたポリシリコン層15を拡散抵抗とな
る部分を残してレジスト23とともにエツチング除去す
る(ST−16,5T−17)。
The recrystallized polysilicon layer 15 is etched away together with the resist 23, leaving a portion that will become a diffusion resistance (ST-16, 5T-17).

残留されたポリシリコン層5に不純物(例えばボロン)
を注入して複数の拡散抵抗15a〜15dとする(ST
−18)。これにより、酸化層である絶縁層上に複数の
拡散抵抗を電気的に絶縁分離された状態で形成すること
ができ、この後、その拡散抵抗を覆うように酸化層14
の全面に高温酸化層18を堆積する(ST−19)。
Impurities (for example, boron) are added to the remaining polysilicon layer 5.
is implanted to form a plurality of diffused resistors 15a to 15d (ST
-18). As a result, a plurality of diffused resistors can be formed on the insulating layer, which is an oxide layer, in an electrically isolated state, and then an oxide layer 14 is formed to cover the diffused resistors.
A high temperature oxide layer 18 is deposited on the entire surface (ST-19).

次いで、コンタクトとなる部分の高温酸化層18をレジ
スト層23とともにエツチング除去した後(ST−20
)、レジスト層23をエツチング除去する(ST−21
)。しかる後、前面に金配線層19を形成しく5T−2
2)、配線領域に対応する上記金配線層19を残して、
他の部分およびレジスト層24をエツチング除去した後
(ST−23,5T−24)、全面にガラスコートによ
る保護層20 (ST−25)を施す。
Next, after removing the high-temperature oxide layer 18 that will become the contact together with the resist layer 23 (ST-20
), the resist layer 23 is removed by etching (ST-21
). After that, a gold wiring layer 19 is formed on the front surface.
2), leaving the gold wiring layer 19 corresponding to the wiring area,
After removing other parts and the resist layer 24 by etching (ST-23, 5T-24), a protective layer 20 by glass coating is applied to the entire surface (ST-25).

しかる後、保護層20の一部をエツチング除去して電極
パッド7を形成するとともにN型シリコン基板1の裏面
研磨を行って所望の厚さにウェハを形成し、裏面に金(
^u)25を形成する(ST26)。そして、ダイヤフ
ラム部となる部分の金25およびレジスト26を除去し
く5T−27゜5T−28)、残った金25をマスクと
して、N型シリコン基板11の裏面をエツチング除去し
て半導体ダイヤフラム1となる薄肉部1aを形成する(
ST−29)。
Thereafter, a part of the protective layer 20 is removed by etching to form the electrode pad 7, and the back surface of the N-type silicon substrate 1 is polished to form a wafer with a desired thickness.
^u) Form 25 (ST26). Then, remove the gold 25 and resist 26 from the portion that will become the diaphragm (5T-27°5T-28), and use the remaining gold 25 as a mask to remove the back surface of the N-type silicon substrate 11 by etching to form the semiconductor diaphragm 1. Forming the thin part 1a (
ST-29).

なお、上記5T−3,5T−12,5T−16゜5T−
23,5T−27におけるレジスト層21〜24.26
は、それぞれの前段階でエツチングするためのマスク合
わせ(パターン合わせ)のとき塗布する。これがエツチ
ングを行うときのマスクとなる。
In addition, the above 5T-3, 5T-12, 5T-16゜5T-
Resist layers 21 to 24.26 in 23,5T-27
is applied during mask matching (pattern matching) for etching in each pre-stage. This will serve as a mask for etching.

以上の製造方法によって、半導体シリコン単結晶基板上
に形成した絶縁層上に単結晶シリコンからなる複数の拡
散抵抗を、相互に電気的に絶縁された状態で形成するこ
とができる。この結果、高温環境下でも熱応力が緩和さ
れ、温度ドリフトを減少させて動作を安定化できる。
By the above manufacturing method, a plurality of diffused resistors made of single crystal silicon can be formed on an insulating layer formed on a semiconductor silicon single crystal substrate in a state where they are electrically insulated from each other. As a result, thermal stress is alleviated even in high-temperature environments, reducing temperature drift and stabilizing operation.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、電極パッドに金配線
と金線という同種金属を接合するように構成したので、
高温雰囲気中でも腐食などにより、動作が不安定になる
ことがない優れた圧力検出装置が得られる効果がある。
As described above, according to the present invention, since the gold wiring and the gold wire are connected to the electrode pad, the same kind of metals are connected to the electrode pad.
This has the effect of providing an excellent pressure detection device that does not become unstable due to corrosion even in a high-temperature atmosphere.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は表面保護層を取外したこの発明の一実施例によ
る圧力検出装置を示す平面図、第2図はその断面図、第
3図はこの発明の圧力検出装置の製造方法を示す説明図
、第4図は従来の圧力検出装置の表面保護層を取外した
平面図、第5図はその断面図である。 7は電極パッド、8は金線、9はリードポスト、11は
シリコン基板、14は絶縁層、15a〜15dは拡散抵
抗、19は金配線、laは薄肉部。 なお、図中、同一符号は同一または相当部分を示す。 第1図
FIG. 1 is a plan view showing a pressure detection device according to an embodiment of the present invention with the surface protective layer removed, FIG. 2 is a sectional view thereof, and FIG. 3 is an explanatory diagram showing a method for manufacturing the pressure detection device of the present invention. , FIG. 4 is a plan view of a conventional pressure detection device with the surface protective layer removed, and FIG. 5 is a sectional view thereof. 7 is an electrode pad, 8 is a gold wire, 9 is a lead post, 11 is a silicon substrate, 14 is an insulating layer, 15a to 15d are diffused resistors, 19 is a gold wiring, and la is a thin part. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1

Claims (1)

【特許請求の範囲】[Claims] 中央部を薄肉部とした半導体ダイヤフラムと、この半導
体ダイヤフラムの表面に形成した絶縁層と、前記薄肉部
に対応して前記絶縁層上に設けた複数の拡散抵抗と、前
記各拡散抵抗と電極パッド間および該拡散抵抗相互間を
接続する金配線と、前記電極パッドとリードポスト間を
接続する前記金配線と同種金属の金線とを備えた圧力検
出装置。
A semiconductor diaphragm having a thin portion in the center, an insulating layer formed on the surface of the semiconductor diaphragm, a plurality of diffused resistors provided on the insulating layer corresponding to the thin portion, and each of the diffused resistors and an electrode pad. A pressure detection device comprising a gold wire connecting between the electrode pad and the lead post, and a gold wire made of the same metal as the gold wire connecting the electrode pad and the lead post.
JP19129890A 1990-07-19 1990-07-19 Pressure detector Pending JPH0476960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19129890A JPH0476960A (en) 1990-07-19 1990-07-19 Pressure detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19129890A JPH0476960A (en) 1990-07-19 1990-07-19 Pressure detector

Publications (1)

Publication Number Publication Date
JPH0476960A true JPH0476960A (en) 1992-03-11

Family

ID=16272237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19129890A Pending JPH0476960A (en) 1990-07-19 1990-07-19 Pressure detector

Country Status (1)

Country Link
JP (1) JPH0476960A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5672551A (en) * 1994-03-18 1997-09-30 The Foxboro Company Method for manufacturing a semiconductor pressure sensor with single-crystal silicon diaphragm and single-crystal gage elements

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432282A (en) * 1977-08-18 1979-03-09 Toshiba Corp Semiconductor pressre conversion unit
JPS58102567A (en) * 1981-12-14 1983-06-18 Yamatake Honeywell Co Ltd Semiconductor pressure transducer
JPS61131567A (en) * 1984-11-30 1986-06-19 Sanyo Electric Co Ltd Semiconductor pressure senser
JPS6286871A (en) * 1985-10-14 1987-04-21 Fuji Electric Co Ltd Semiconductor pressure sensor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432282A (en) * 1977-08-18 1979-03-09 Toshiba Corp Semiconductor pressre conversion unit
JPS58102567A (en) * 1981-12-14 1983-06-18 Yamatake Honeywell Co Ltd Semiconductor pressure transducer
JPS61131567A (en) * 1984-11-30 1986-06-19 Sanyo Electric Co Ltd Semiconductor pressure senser
JPS6286871A (en) * 1985-10-14 1987-04-21 Fuji Electric Co Ltd Semiconductor pressure sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5672551A (en) * 1994-03-18 1997-09-30 The Foxboro Company Method for manufacturing a semiconductor pressure sensor with single-crystal silicon diaphragm and single-crystal gage elements

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