JPS58102567A - Semiconductor pressure transducer - Google Patents

Semiconductor pressure transducer

Info

Publication number
JPS58102567A
JPS58102567A JP20127481A JP20127481A JPS58102567A JP S58102567 A JPS58102567 A JP S58102567A JP 20127481 A JP20127481 A JP 20127481A JP 20127481 A JP20127481 A JP 20127481A JP S58102567 A JPS58102567 A JP S58102567A
Authority
JP
Japan
Prior art keywords
substrate
piezoresistive element
conductor layer
single crystal
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20127481A
Other languages
Japanese (ja)
Inventor
Haruo Yamauchi
山内 治男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Azbil Corp
Original Assignee
Azbil Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Azbil Corp filed Critical Azbil Corp
Priority to JP20127481A priority Critical patent/JPS58102567A/en
Publication of JPS58102567A publication Critical patent/JPS58102567A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/84Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure

Abstract

PURPOSE:To obtain a device resistant to noises, by forming a piezoresistive element on a substrate via an insulation layer, and surrounding the outer periphery thereof by a conductor layer. CONSTITUTION:A piezoresistor constituted of P type single crystal Si has good linearity of pressure-resistance and can take out the output in forward-reverse directions having good symmetry, in the plane (100) and the direction <110> wherein the piezoresistance coefficient becomes the maximum. Therefore, by constituting the substrate 1 and the conductor layer 5 of P type single crystal semiconductor the same as the piezoresistive element 3, a P-N junction is not formed, and accordingly electrically and mechanically good matching ca be obtained. By impressing a positive potential with the highest circuit voltage on the conductor layer 5 and the substrate 1 connected thereto, the piezoresistive element 3, in the periphery thereof, is surrounded by a shield plate having a higher potential, and negative ions contained in sealing solution are trapped to the conductor layer 5 or the substrate 1. Therefore, the output drift due to ion migration can be avoided.

Description

【発明の詳細な説明】 本発明は、半導体率−晶からなるピエゾ抵抗素子を用い
た半導体圧力変換器に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor pressure transducer using a piezoresistive element made of semiconducting crystal.

従来この種の半導体圧力変換器は、半導体単結晶基板の
略中央部に設けた圧力に応じて起歪する起歪部に1当該
基板と異なる導電形を有するピエゾ抵抗領域を設けた構
造を有している。
Conventionally, this type of semiconductor pressure transducer has a structure in which a piezoresistive region having a conductivity type different from that of the substrate is provided in a strain-generating portion that is provided approximately in the center of a semiconductor single crystal substrate and that generates strain in response to pressure. are doing.

このように、従来の半導体圧、力変換器においては、ピ
エゾ抵抗領域間の絶縁は当該抵抗領域と基板との間のP
N接合によって保たれているため、特に高温時において
、PN接合間のリーク電流に起因してSN比が低下する
等の欠点が生じた。
Thus, in conventional semiconductor pressure and force transducers, the insulation between the piezoresistive regions is the same as the insulation between the piezoresistive regions and the substrate.
Since this is maintained by the N junction, there have been drawbacks such as a decrease in the S/N ratio due to leakage current between the PN junctions, especially at high temperatures.

また、特に1この圧力変換器を圧力伝達媒体としてのシ
リコンオイル、フッ素オイル等の封入液中で使用する場
合には、封入液中に含まれるイオンの移動等の影響によ
シ、出力に時間的変動(ドリフト)が認められるという
欠点があった。
In addition, especially when this pressure transducer is used in a sealed liquid such as silicone oil or fluorine oil as a pressure transmission medium, the output may take a long time due to the influence of the movement of ions contained in the filled liquid. The disadvantage of this method was that it allowed fluctuations (drift).

本発明は、以上のような状況Kfsみてなされたもので
あシ、その目的は、ピエゾ抵抗領域間のリーク電流およ
びイオンの移動に起因する出力のドリフトを抑制し、・
ノイズに対して強く、かつ通電彼達やかに安定した出力
を得ることが可能な半導体圧力変換器を提供するととに
ある。
The present invention was made in view of the above-mentioned situation Kfs, and its purpose is to suppress output drift caused by leakage current and ion movement between piezoresistive regions,
The object of the present invention is to provide a semiconductor pressure transducer that is resistant to noise and capable of obtaining a stable output when energized.

このような目的を達成するために、本発明は、半導体単
結晶基板の略中央部に設けた起歪部上に、前記半導体・
の化合物からなる絶縁層を設け、仁の絶縁層の上部に半
導体単結晶からなるピエゾ抵抗素子を設けると共に、少
なくともこのピエゾ抵抗素子の上に、当該抵抗素子上の
前記絶縁層を介して導電体層を設けたものである。
In order to achieve such an object, the present invention provides a strain-generating portion provided approximately at the center of a semiconductor single crystal substrate.
An insulating layer made of a compound of It has layers.

即ち、半導体単結晶基板上に絶縁層を設け、その上に半
導体単結晶からなるピエゾ抵抗素子を形成したことによ
シ、ピエゾ抵抗素子は完全な絶餘体によってその絶縁が
保たれることとなるため、従来のPN接合による場合の
ようなリーク電流を防ぐことができ、よシ高温下におけ
る使用が可能となる。また、従来、上記PN接合のディ
プレッション効果によって電圧と抵抗とが比例しない現
象が生じることがあったが、上述したようにピエゾ抵抗
素子と基板との間に絶縁層を介在させたことにより、こ
の現象を有効に防止することができる。
In other words, by providing an insulating layer on a semiconductor single-crystal substrate and forming a piezo-resistive element made of a semiconductor single-crystal on top of the insulating layer, the piezo-resistive element can maintain its insulation as a completely insulated body. Therefore, it is possible to prevent leakage current as in the case of a conventional PN junction, and it is possible to use the device at a much higher temperature. In addition, conventionally, the depletion effect of the PN junction has caused a phenomenon in which the voltage and resistance are not proportional, but by interposing an insulating layer between the piezoresistive element and the substrate as described above, this This phenomenon can be effectively prevented.

この場合、上記絶縁層は、基板やピエゾ抵抗素子を構成
する半導体の化合物によって形成するため、各界面での
整合性は良好で、熱膨張係数の差違等による歪の発生等
を回避することができる。
In this case, since the insulating layer is formed from a semiconductor compound that constitutes the substrate and the piezoresistive element, the consistency at each interface is good, and it is possible to avoid distortion due to differences in thermal expansion coefficients, etc. can.

また、上記絶縁層を介してピエゾ抵抗素子の周囲を導電
体層でとシ囲むように構成したことによシ、この導電体
層はファラデーシールドとしての機能を有する結果、ノ
イズに対して強い構造となる。特に、圧力伝達媒体とし
てシリコンオイル、フッ素オイル等の封入液を使用した
場合・に、封入液中のイオンはこの導電体層に固定化さ
れるため、イオン移動の影響による出力のドリフトを抑
えることができる。
Furthermore, since the piezoresistive element is surrounded by a conductive layer through the insulating layer, this conductive layer functions as a Faraday shield, resulting in a structure that is resistant to noise. becomes. In particular, when a sealed liquid such as silicone oil or fluorine oil is used as a pressure transmission medium, the ions in the filled liquid are fixed to this conductive layer, so it is possible to suppress output drift due to the influence of ion movement. Can be done.

以下、実施例について説明する。Examples will be described below.

第1図は、本発明の一実施例を示す断面図である。同図
において、1はP形単結晶シリコンからなる基板である
。この基板1は、エツチングによシその裏面の略中央部
を除去することによってカップ状に形成され、中央部の
ダイヤフラム1&と、これを周縁部で支持する固定部1
bとからなる。
FIG. 1 is a sectional view showing one embodiment of the present invention. In the figure, reference numeral 1 denotes a substrate made of P-type single crystal silicon. This substrate 1 is formed into a cup shape by removing a substantially central portion of the back surface of the substrate 1 by etching, and includes a diaphragm 1 in the center and a fixing portion 1 that supports the diaphragm 1 at its periphery.
It consists of b.

2はこの基板10表面上に形成した二酸化シリコンから
なる絶縁層、また、3は前記ダイヤフラム1a の上に
位置する上記絶縁層2の上部に設けたr 形単結晶シリ
コンからなるピエゾ抵抗素子、4は電極としてのメタリ
ゼーションバタン、5は、このメタリゼーションバタン
40部分を除き、ピエゾ抵抗素子3の上の前記絶縁層2
を覆うように形成したt形単結晶シリコンからなる導電
体層である。この導電体層5は、上記絶縁層2に設けた
透孔6を通して基板1に接続され、この導電体層Sと基
板1とに、回路電圧9最も高い正電位のバイアス電圧が
、電源7によってメタリゼーションバタン8を介して印
加しである。また、前記ピエゾ抵抗索子3は、例えばC
VD法によって堆積させたポリシリコンを、レーザビー
千を照射することによシ再結晶化することによって形成
することができる。この場合、レーザビームのスキャン
方向によって、再結晶化した単結晶の結晶軸方向を制御
することができる。
2 is an insulating layer made of silicon dioxide formed on the surface of the substrate 10; 3 is a piezoresistance element made of r-type single crystal silicon provided on the insulating layer 2 located above the diaphragm 1a; 4; 5 is a metallization batten serving as an electrode, and 5 is the insulating layer 2 on the piezoresistive element 3 except for the metallization batten 40.
This is a conductor layer made of T-type single crystal silicon formed so as to cover the conductor layer. This conductive layer 5 is connected to the substrate 1 through a through hole 6 provided in the insulating layer 2, and a bias voltage of the highest positive potential is applied to the conductive layer S and the substrate 1 by a power source 7. The voltage is applied via the metallization batten 8. Further, the piezoresistive cable 3 may be, for example, C
It can be formed by recrystallizing polysilicon deposited by the VD method by irradiating it with laser beams. In this case, the crystal axis direction of the recrystallized single crystal can be controlled by the scanning direction of the laser beam.

一般にP形単結晶シリコンからなるピエゾ抵抗体は、N
形のものに比較して圧力−抵抗のりニアリテイが良く、
ピエゾ抵抗係数が最大となる(100)面、<11.0
)方向において対称性の良好な正逆両方向の出力が取出
せる。この場合、特に、上述したように基、板1および
導電体層5tもピエゾ抵抗素子3と同様のP形単結晶半
導体で構成することにより、PN接合が形成されず、電
気的、機絨的に最も良好な整合性が得られる。
Generally, piezoresistors made of P-type single crystal silicon are N
It has better pressure-resistance adhesiveness compared to the shaped type,
(100) plane where the piezoresistance coefficient is maximum, <11.0
) output with good symmetry in both forward and reverse directions. In this case, in particular, as described above, the substrate, the plate 1, and the conductive layer 5t are also made of a P-type single crystal semiconductor similar to the piezoresistive element 3, so that a PN junction is not formed and electrical and mechanical provides the best consistency.

また、上述したように回路電圧の最も高い正電位を導電
体層5およびこれに接続された基板1に印加したことに
よシ、ピエゾ抵抗素子3は、周囲をよ)高い電位を有す
るシールド板でとり囲まれ      ゝる形となシ、
封入液中に含まれる蔭イオンは導電体層5もしくは基板
1にトラップされるため、イオンの移動による出力の、
ドリフトを回避することができる。。
Furthermore, as described above, by applying the highest positive potential of the circuit voltage to the conductive layer 5 and the substrate 1 connected thereto, the piezoresistive element 3 is exposed to a shield plate having a higher potential than the surroundings. A shape surrounded by
Since the shadow ions contained in the filled liquid are trapped in the conductor layer 5 or the substrate 1, the output due to the movement of ions is
Drift can be avoided. .

第2図は、本発明の他の実施例を示す断面図であシ、第
1図と同一部分は同一記号を用いてその詳細説明を省略
する。即ち、第2図の実施例(おいては、絶縁層2を介
してピエゾ抵抗素子3を、とシ囲むように、金属からな
る導電体層11を形成し、基板1との接触部に、r単結
晶シリコンからなるオーム擬勢領域10を設けである。
FIG. 2 is a sectional view showing another embodiment of the present invention, and the same parts as in FIG. 1 are designated by the same symbols, and detailed explanation thereof will be omitted. That is, in the embodiment shown in FIG. 2, a conductive layer 11 made of metal is formed so as to surround the piezoresistive element 3 via an insulating layer 2, and a conductive layer 11 made of metal is formed at the contact portion with the substrate 1. An ohmic bias region 10 made of single crystal silicon is provided.

このようなオーム接触領域10は、導電体上金属によっ
て構成し、かつ基板1の不純物#1度が低い場合には、
両者間のオーム接触を得るために必要である。
Such an ohmic contact region 10 is made of metal on a conductor, and when the impurity #1 degree of the substrate 1 is low,
This is necessary to obtain ohmic contact between the two.

なお、上述した実施例においては、P形シリコンを用い
た場合についてのみ説明したが、N形半導体からなるピ
エゾ抵抗素子を用いた場合には、基板も導電体層4N形
半導体を用いることが望ましく、導電体層および基板は
最も大きい負電位にバイアスすることは勿論である。
In addition, in the above-mentioned embodiment, only the case where P-type silicon was used was explained, but when a piezoresistive element made of an N-type semiconductor is used, it is preferable that the conductor layer 4 is also made of an N-type semiconductor. , the conductor layer and the substrate are of course biased to the most negative potential.

また、導電体層は、ポリシリコンによって構成しても良
い。
Further, the conductor layer may be made of polysilicon.

以上説明したように、本発明によれば、ピエゾ抵抗素子
管、絶縁層を介して基板上に形成し、かつこのピエゾ抵
抗素子の外周を導電体層でと9屈んだことによシ、ノイ
ズに対して強く、かつ通電級速やかに出力が安定する半
導体圧力変換器を得るととが可能になるという優れた効
果を有する。
As explained above, according to the present invention, a piezoresistive element tube is formed on a substrate via an insulating layer, and the outer periphery of this piezoresistive element is surrounded by a conductive layer. It has the excellent effect of making it possible to obtain a semiconductor pressure transducer that is strong against electricity and whose output stabilizes quickly in current-carrying class.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す断面図、第2M#′i
、本発明の他の実施例を示す断面図である。 1・・・・基板、1h  a 拳・φダイヤフラム、1
b  ・・・・固定部、2・・・・絶縁部、3・・0.
ピエゾ抵抗素子、4@@@@メタリゼーシヨン″タン1
5,9・・・・導電体層。 特許出願人 山武ハネウェル株式会社
FIG. 1 is a cross-sectional view showing one embodiment of the present invention, and FIG.
FIG. 2 is a sectional view showing another embodiment of the present invention. 1... Board, 1h a fist/φ diaphragm, 1
b...Fixed part, 2...Insulating part, 3...0.
Piezoresistive element, 4@@@metallization" tongue 1
5, 9... Conductor layer. Patent applicant Yamatake Honeywell Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 圧力に応じて起歪するダイヤフラム状の起歪部およびこ
の起歪部周縁部を支持する固定部から表る半導体単結晶
基板と、この基板の前記起歪部上に形成した前記半導体
の化合物から々る絶縁層と、仁の絶縁層の上部に形成し
た半導体単結晶からなるピエゾ抵抗素子と、少なくとも
このピエゾ抵抗素子の上の前記絶縁層を覆う導電体層と
、前記ピエゾ抵抗素子の電極を構成するメタリゼーショ
ンパタンとを有する半導体圧力変換器。
A semiconductor single-crystal substrate exposed from a diaphragm-shaped strain-generating portion that strains in response to pressure and a fixed portion that supports the peripheral edge of the strain-generating portion, and a compound of the semiconductor formed on the strain-generating portion of this substrate. a piezoresistive element made of a semiconductor single crystal formed on the upper part of the insulating layer; a conductive layer covering at least the insulating layer on the piezoresistive element; and an electrode of the piezoresistive element. and a metallization pattern comprising a semiconductor pressure transducer.
JP20127481A 1981-12-14 1981-12-14 Semiconductor pressure transducer Pending JPS58102567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20127481A JPS58102567A (en) 1981-12-14 1981-12-14 Semiconductor pressure transducer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20127481A JPS58102567A (en) 1981-12-14 1981-12-14 Semiconductor pressure transducer

Publications (1)

Publication Number Publication Date
JPS58102567A true JPS58102567A (en) 1983-06-18

Family

ID=16438236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20127481A Pending JPS58102567A (en) 1981-12-14 1981-12-14 Semiconductor pressure transducer

Country Status (1)

Country Link
JP (1) JPS58102567A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61248482A (en) * 1985-04-25 1986-11-05 Nippon Denso Co Ltd Semiconductor strain detector
JPS6329981A (en) * 1986-07-24 1988-02-08 Toshiba Corp Semiconductor pressure transducer
JPH0476960A (en) * 1990-07-19 1992-03-11 Mitsubishi Electric Corp Pressure detector
JPH0476957A (en) * 1990-07-19 1992-03-11 Mitsubishi Electric Corp Acceleration sensor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039085A (en) * 1973-08-08 1975-04-10
JPS5632772A (en) * 1979-08-27 1981-04-02 Hitachi Ltd Semiconductor pressure sensor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039085A (en) * 1973-08-08 1975-04-10
JPS5632772A (en) * 1979-08-27 1981-04-02 Hitachi Ltd Semiconductor pressure sensor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61248482A (en) * 1985-04-25 1986-11-05 Nippon Denso Co Ltd Semiconductor strain detector
JPS6329981A (en) * 1986-07-24 1988-02-08 Toshiba Corp Semiconductor pressure transducer
JPH0476960A (en) * 1990-07-19 1992-03-11 Mitsubishi Electric Corp Pressure detector
JPH0476957A (en) * 1990-07-19 1992-03-11 Mitsubishi Electric Corp Acceleration sensor

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