JPH0475364A - Programmable logic array - Google Patents

Abstract

PURPOSE:To obtain a programmable logic array(PLA) which can handle the situation instantly by installing at least two sets of OR arrays to one AND array and providing a selection means to select one signal out of at least two sets of output signals against one set of input signal. CONSTITUTION:A certain value is kept in a feedback register 4. This value and an input signal entered from the outside are input into an AND array 2 by way of an input decoder 1, thereby generating a logical production term. The logical production terms thus generated are input into OR arrays 3a and 3b respectively so that two types of output signals may be obtained as its logical sum. These output signals are selected by a control signal determined after the confirmation of an input signal of PLA 7 at a multiplexer 6. The selected signals are input into the feedback register 4 and an output register 5 so that the signals may be transmitted outside.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a programmable logic array.

[Conventional technology]

Figure 2 shows the conventional programmable logic play c and below P.
In Figure 0, which is a block diagram showing the configuration of LA), (1) is an input decoder, (2) is an ANP array, (
3) is an OR array, (4) is a feedback register,
(5) is an output register, and (7) is a PLA.

Next, the operation will be explained.

It is now assumed that feedback register (4) K holds a certain value. This value and the input signal input from the outside pass through the input decoder (1) and are AND7-rayed (2).
is input. This generates all logical product terms. Then, by inputting it to the OR play (3), a logical sum is taken and an output signal is obtained. This output signal J8- is input to a feedback register (4) and an output register (5) to transmit the signal to the outside.

[Problem that the invention attempts to solve]

Since the conventional PLA is configured as described above, only one set of output signals is generated for one set of input signals. When PLA is used in a system that controls state transition, PL
Even if the input signal changes and enters a different state during the process of determining the value of A, it cannot be dealt with immediately. Furthermore, it is not suitable to use PLA in such a structure.

This invention was made to solve the above-mentioned problems, and aims to provide a PLA that can be dealt with immediately.

[Means for solving the lI problem]

The PLA according to the present invention is provided with a plurality of OR arrays for one AND array t, and means for selecting one of the outputs thereof, and the input signal determined quickly is the input signal of the PLA. and the input signal to be determined late is PL
The output of A is selected.

[Effect]

Since the PLA according to the present invention has a plurality of outputs, it can be used in a system that controls state transition.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a PLA according to an embodiment of the present invention. In the figure, <1), t2).

(4), (5), and (7) are the same as those shown in the conventional example of FIG. 2, and therefore their explanations will be omitted. (3a),
(3b) is an OR array, and (6) an ri multiplexer.

Next, the operation will be explained.

Assume that a certain value is now held in the feedback register (4). This value and the input signal input from the outside pass through the input decoder (1) and the AND array (21K
is input. This generates a logical product term. Then, the generated logical product terms are ORed (3a), (
3b) and performs a logical sum to obtain two output signals. These output signals are P L
The 0 selected signal -8 selected by the control signal determined after the input signal of A (7) is determined is input to the feedback register (4) and the output register (5) to transmit the signal to the outside.

Note that in the above embodiment, two OR arrays (3a),
Although the case of (sb) has been described, the same effects as in the above embodiment can be obtained even in cases beyond that.

〔Effect of the invention〕

As described above, according to the present invention, a plurality of OR arrays are provided for one AND array of a PLA, and the outputs thereof are selected by a multiplexer to obtain a desired output signal. Then, P
The LA input signal is used as the input signal, and the signal determined later is used as the multiplexer control signal. Therefore, even if the logic configuration is such that the conditions change while the PLA output is being determined after the PLA input is determined, it can be dealt with immediately.

In other words, it can be used in a system that controls state transitions. In addition, since the PLA AND array is a unit, the layout area can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a PLA according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional PLA. In the figure, (1) is an input decoder, (2) is an AND array, (3a) and (3b) are OR arrays, (4) is a feed barac register, (5) is an output register, and (6) u
The multiplexer (7) is a PLA. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] Receives N input signals (N>O), receives L input signals (L>O)
In an ANP array that generates a logical product term and a programmable logic array that receives L logical product terms as input and outputs M logical sums (M>O), one AND array includes at least two sets of OR arrays. A programmable logic array comprising means for selecting one of at least two sets of output signals output in response to one set of input signals.