JPH0474235A - Wrong control preventing circuit - Google Patents

Wrong control preventing circuit

Info

Publication number
JPH0474235A
JPH0474235A JP2187644A JP18764490A JPH0474235A JP H0474235 A JPH0474235 A JP H0474235A JP 2187644 A JP2187644 A JP 2187644A JP 18764490 A JP18764490 A JP 18764490A JP H0474235 A JPH0474235 A JP H0474235A
Authority
JP
Japan
Prior art keywords
circuit
signal
microprocessor
control signal
alarm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2187644A
Other languages
Japanese (ja)
Inventor
Makoto Hanawa
良 花輪
Satoshi Morishita
聡 森下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Aerospace Systems Ltd
Original Assignee
NEC Corp
NEC Aerospace Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Aerospace Systems Ltd filed Critical NEC Corp
Priority to JP2187644A priority Critical patent/JPH0474235A/en
Publication of JPH0474235A publication Critical patent/JPH0474235A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the output of a wrong control signal to a controlled circuit by deciding the validity of the control signals outputted to a microprocessor and a peripheral circuit based on the input of an alarm signal. CONSTITUTION:A microprocessor/peripheral circuit 3 outputs a state signal 5 to an alarm detection circuit 2 to show the state of a microprocessor. The circuit 2 produces no alarm signal 7 as long as the signal 5 is normal, and a control signal deciding circuit 1 decides a valid control signal 6 outputted from the microprocessor and then outputs a control signal 8. When the microprocessor becomes abnormal, the circuit 2 produces the signal 7. Thus the circuit 1 decides a valid signal 6 sent from the microprocessor and then stops the output of the signal 8. As a result, the malfunction of a controlled circuit can be evaded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマイクロプロセッサ及び周辺回路が、対象とす
る被制御回路を制御するシステムにおいて、特に、マイ
クロプロセッサの異常時に被制御回路に対して誤り制御
信号を出力する事を防止する誤り制御防止回路に関する
Detailed Description of the Invention [Industrial Application Field] The present invention provides a system in which a microprocessor and peripheral circuits control a target controlled circuit, and in particular, a system in which a microprocessor and a peripheral circuit control a target controlled circuit. The present invention relates to an error control prevention circuit that prevents control signals from being output.

〔従来の技術〕[Conventional technology]

従来、マイクロプロセッサおよび周辺回路を使用して対
象とする被制御回路を制御するシステムにおいて、マイ
クロプロセッサが異常となった場合には、マイクロプロ
セッサの異常をLEDやブザーにより人間に伝えて人為
的にマイクロプロセッサの動作を停止させて誤り制御信
号の出力を防止する方法がとられていた。
Conventionally, in systems that use a microprocessor and peripheral circuits to control the target controlled circuit, if the microprocessor becomes abnormal, it can be artificially reported to a human by using an LED or a buzzer. A method has been used to prevent the output of error control signals by stopping the operation of the microprocessor.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の誤り制御防止回路は、人為的に異常とな
ったマイクロプロセッサを停止する方法なので、速やか
に誤り制御を防止できず、被制御回路が誤動作を続ける
という欠点がある。
The above-described conventional error control prevention circuit is a method of stopping a microprocessor that has artificially become abnormal, so it has the disadvantage that error control cannot be promptly prevented and the controlled circuit continues to malfunction.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の誤り制御防止回路は、装置の正常異常を表す状
態信号を出力する機能を有するマイクロプロセッサ及び
周辺回路と、前記状態信号を検出してアラーム信号を発
生させるアラーム検出回路と、前記マイクロプロセッサ
及び周辺回路の出力する制御信号の有効性を前記アラー
ム信号の入力により判定し被制御回路に制御信号を出力
する制御信号判定回路とを有する。
The error control prevention circuit of the present invention includes a microprocessor and a peripheral circuit that have a function of outputting a status signal indicating normality or abnormality of the device, an alarm detection circuit that detects the status signal and generates an alarm signal, and the microprocessor. and a control signal determination circuit that determines the validity of the control signal output from the peripheral circuit based on the input of the alarm signal and outputs the control signal to the controlled circuit.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

本実施例はマイクロプロセッサ及び周辺回路3と、マイ
クロプロセッサ及び周辺回路3により制御を受ける被制
御回路4と、マイクロプロセッサ及び周辺回路3の状態
を示す信号を検出して、アラーム信号7を発生させるア
ラーム検出回路2と、マイクロプロセッサおよび周辺回
路3の出力する制御信号6の有効性をアラーム信号7に
より判定して有効な場合のみ被制御回路4に制御信号8
を出力する制御信号判定回路1から構成されている。
This embodiment detects a microprocessor and peripheral circuit 3, a controlled circuit 4 controlled by the microprocessor and peripheral circuit 3, and a signal indicating the status of the microprocessor and peripheral circuit 3, and generates an alarm signal 7. The validity of the control signal 6 output from the alarm detection circuit 2, the microprocessor, and the peripheral circuit 3 is determined based on the alarm signal 7, and only when the control signal 6 is valid, the control signal 8 is sent to the controlled circuit 4.
It consists of a control signal determination circuit 1 that outputs.

次に本実施例の動作を説明する。マイクロプロセッサ及
び周辺回路3は、マイクロプロセッサの状態を示す状態
信号5をアラーム検出回路2に出力している。マイクロ
プロセッサの状態を示す状態信号5が正常中はアラーム
検出回路2はアラーム信号7を発生していない。したが
って制御信号判定回路1はアラーム信号7が入力されな
い間は、マイクロプロセッサの出力する制御信号6を有
効と判定し、制御信号8を出力している。マイクロプロ
セッサが異常となった時、アラーム検出回路2はアラー
ム信号7を発生する事により、制御信号判定回路1はマ
イクロプロセッサの出力する制御信号6を有効と判定し
制御信号8の出力を停止する。
Next, the operation of this embodiment will be explained. The microprocessor and peripheral circuit 3 outputs a status signal 5 indicating the status of the microprocessor to the alarm detection circuit 2. While the status signal 5 indicating the status of the microprocessor is normal, the alarm detection circuit 2 does not generate the alarm signal 7. Therefore, the control signal determination circuit 1 determines that the control signal 6 output from the microprocessor is valid and outputs the control signal 8 while the alarm signal 7 is not input. When the microprocessor becomes abnormal, the alarm detection circuit 2 generates an alarm signal 7, and the control signal determination circuit 1 determines that the control signal 6 output from the microprocessor is valid and stops outputting the control signal 8. .

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、マイクロプロセッサ及び
周辺回路の異常時にアラーム信号を出力するアラーム検
出回路と、アラーム信号のありなしにより制御信号を出
力又は停止する制御信号判定回路とを設けることにより
、被制御回路が誤動作し続ける事を回避できる効果があ
る。
As explained above, the present invention provides an alarm detection circuit that outputs an alarm signal when the microprocessor and peripheral circuits are abnormal, and a control signal determination circuit that outputs or stops the control signal depending on the presence or absence of the alarm signal. This has the effect of preventing the controlled circuit from continuing to malfunction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のブロック図である。 1・・・制御信号判定回路、2・・・アラーム検出回路
、3・・・マイクロプロセッサ及び周辺回路、4・・・
被制御回路、5・・・マイクロプロセッサの状態信号、
6・・・マイクロプロセッサの制御信号、7・・・アラ
ーム信号、8・・・制御信号。
FIG. 1 is a block diagram of one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Control signal determination circuit, 2... Alarm detection circuit, 3... Microprocessor and peripheral circuit, 4...
Controlled circuit, 5... microprocessor status signal;
6... Microprocessor control signal, 7... Alarm signal, 8... Control signal.

Claims (1)

【特許請求の範囲】[Claims] 装置の正常異常を表す状態信号を出力する機能を有する
マイクロプロセッサ及び周辺回路と、前記状態信号を検
出してアラーム信号を発生させるアラーム検出回路と、
前記マイクロプロセッサ及び周辺回路の出力する制御信
号の有効性を前記アラーム信号の入力により判定し被制
御回路に制御信号を出力する制御信号判定回路とを有す
ることを特徴とする誤り制御防止回路。
a microprocessor and a peripheral circuit that have a function of outputting a status signal indicating normality or abnormality of the device; an alarm detection circuit that detects the status signal and generates an alarm signal;
An error control prevention circuit comprising: a control signal determination circuit that determines the validity of control signals output from the microprocessor and peripheral circuits based on the input of the alarm signal, and outputs the control signal to the controlled circuit.
JP2187644A 1990-07-16 1990-07-16 Wrong control preventing circuit Pending JPH0474235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2187644A JPH0474235A (en) 1990-07-16 1990-07-16 Wrong control preventing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2187644A JPH0474235A (en) 1990-07-16 1990-07-16 Wrong control preventing circuit

Publications (1)

Publication Number Publication Date
JPH0474235A true JPH0474235A (en) 1992-03-09

Family

ID=16209725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2187644A Pending JPH0474235A (en) 1990-07-16 1990-07-16 Wrong control preventing circuit

Country Status (1)

Country Link
JP (1) JPH0474235A (en)

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