JPH04741A - Semiconductor integrated circuit device and layout system thereof - Google Patents

Abstract

PURPOSE:To increase element density by connecting a wiring for connecting blocks arranged in hierarchy on a side of a block as directly as possible. CONSTITUTION:A block is arranged without providing a wiring region among blocks. Wiring among blocks is connected on a side of adjacent blocks which are in contact with each other. When blocks are apart, they are connected by a wiring of a minimum distance to cross with a longitudinal direction of a channel among blocks. When another block exists between blocks to be connected, a passing wiring is formed in the block between blocks and a plurality of dummy terminals connected thereto are provided. A terminal of each block is connected to each dummy terminal on a side. As for layout of an interior of a block, an element is arranged to shorten a distance to an external terminal of a block.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device and its layout method, and particularly to a semiconductor integrated circuit device constructed using a building block method and its layout design method. It is about effective techniques.

[Conventional technology]

FIG. 7 shows a layout model based on conventional automatic layout design. This method is called a building block method, in which the chip is configured in a hierarchical manner, in which blocks are configured for each functional unit, and the blocks are arranged and connected. In this layout method, connection points (referred to as external terminals) for signals going out from inside the block are determined in the internal layout of the block, regardless of the mutual arrangement of the blocks. For this reason, the wiring that connects the blocks is provided with gaps (channels) between the blocks.

Regarding such a building block method, for example, Confucian Technical Report, Vol. 86, N1328 pp59~
66, r analog custom LSI layout CAD
There is a J.

[Problem to be solved by the invention]

In the conventional building block layout, wiring connecting blocks is formed in wiring areas provided between blocks. FIG. 8 shows the relationship between the element density and the number of elements of a semiconductor integrated circuit device. In FIG. 8, reductions in element size and wiring width due to process miniaturization are normalized and expressed on the same scale. Generally, as the number of elements increases, the number of blocks and the number of wires increase, and the ratio of the wiring area increases. Therefore, as shown in the figure, there is a problem in that the element density decreases as the number of elements increases. This applies not only to automatic layout but also to manual layout.

An object of the present invention is to provide a semiconductor integrated circuit device that can increase element density and an eye-out method thereof.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the configuration and method are such that the wiring connecting blocks arranged hierarchically is connected as directly as possible on the sides of the blocks.

[For production]

According to the above-mentioned means, since the wiring area for connecting blocks can be configured to the minimum necessary size, the element density can be increased accordingly.

〔Example〕

FIG. 1 shows a layout diagram of an embodiment of a semiconductor integrated circuit device formed by the automatic layout method according to the present invention.

Figure (a) shows a layout diagram of the entire chip,
FIG. 1B shows a layout diagram of one block, and FIG. 1C shows a pattern diagram of transistors and resistors as representative examples of circuit elements constituting the block.

The automatic layout method in this embodiment is performed according to the following basic idea.

■As a general rule, place blocks without providing any wiring areas between the blocks.

■Connect the wiring between two blocks on the sides of adjacent blocks. Furthermore, when the blocks are far apart, the blocks are connected by wiring of the shortest distance so as to intersect the longitudinal direction of the channel between the blocks.

■When there is another block between the blocks to be connected, form a passing wiring between the blocks sandwiched between them and provide multiple dummy-terminals connected to it, and connect each dummy-terminal to each of the above blocks. Connect the terminals on the sides.

■When designing the layout inside the block, arrange the elements so that the distance to the external terminals of the block is shortened.

This will be specifically explained using FIGS. 2 to 8.

FIG. 2 shows a layout diagram of an embodiment inside a block, and FIG. 3 shows a layout diagram of an embodiment in which two blocks as described above are arranged side by side.

In Figure 3, the wiring connecting two adjacent blocks is laid out so that the corresponding sides of the two blocks overlap directly, without providing a wiring channel as in the conventional case, and the wiring above the overlapping sides is Connect as shown by the small black circle. That is, a net connected to an adjacent block is wired to an external terminal indicated by a small black circle on the side of the block. The wiring connected to the above net in the adjacent block is also drawn out in accordance with the position of the external terminal. Then, by overlapping the sides of adjacent blocks, wires of the same net are automatically connected.

This is a sequence that follows the principles of and ■ above.

FIG. 4 shows a layerer NEI as an embodiment for connecting distant blocks.

When another block exists between two blocks as in this embodiment, a passing wiring is provided in the block sandwiched between the two blocks. For this reason, this block is provided with a pair of dummy external terminals connected to wiring passing through the block. Therefore, in a block sandwiched between two blocks in this way, data of only wiring, which is not connected to internal circuit elements, is created as a passing wiring. Then, using this dummy external terminal, the two blocks are laid out so that their corresponding sides directly overlap as described above, and the connections are made as shown by the small black circles above the overlapping sides.

By adopting such a configuration or layout method, it is possible to connect two blocks even if another circuit block exists between them. The passing wiring within the block is not particularly limited, but is formed so as to appropriately pass over the element formation area, rather than providing a special wiring area as shown in the figure.

This prevents the block itself from increasing in size due to the internal wiring passing through it.

This is an example of applying the principle of ① above.

Note that if there are two or more blocks sandwiched between two blocks, a passing wiring and a dummy external terminal are provided for each block. Therefore, adjacent dummy external terminals may be connected to each other on the side of the block.

FIG. 5 shows a layout diagram of an embodiment in which there is a gap between blocks. In this embodiment, since adjacent blocks are not in contact with each other, the wiring between the blocks is not automatically connected, but is connected by the wiring between the blocks. In this case, since the external terminals to be connected are facing each other across the gap between the blocks, the connection is made by a wiring of the shortest length orthogonal to the longitudinal direction of the gap (channel). If the positional relationship between the two external terminals is shifted vertically, as in the case of the wiring between blocks in the upper part of the figure, it is necessary to particularly widen the wiring area (gap between blocks) by connecting using a line with a bend. There is no. This is an example in accordance with the principle of ① above.

Figure 6 shows 1.
A layout diagram of an embodiment in which two linear integrated circuits are configured is shown.

As can be understood from the whole figure, in principle, no gaps (channels) are provided between the blocks to form wiring for connecting the blocks.

Furthermore, even if a gap is provided between the blocks due to vertical or horizontal displacement of the external terminals in the two blocks to be connected as described above, the gap is the minimum required for arranging the bent line. It is something. This makes it possible to reduce the chip size of semiconductor integrated circuit devices when the same element size and functionality are provided, compared to the conventional case where gaps called wiring channels are uniformly provided between blocks. can. In other words, the element density can be increased to the extent that the uniform wiring area as described above is not formed.

The effects obtained from the above examples are as follows. In other words, connections between blocks that are arranged hierarchically are directly connected on the edges of the blocks as much as possible, or by using the block layout method described above. The effect is that the wiring channel can be omitted or reduced and the chip size can be reduced.

(2) In the block sandwiched between the blocks to be connected, provide wiring passing through the blocks, and assign a pair of dummy external terminals to both ends of the wiring, and connect each dummy external terminal to the wiring of the block to be connected. By connecting the external terminals, there is no need to provide a special wiring area even when the blocks are not adjacent to each other, so it is possible to reduce the chip size.

(3) According to (1) and (2) above, the number of semiconductor chips formed from one semiconductor wafer increases, so that the effect of improving mass productivity can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, a functional professional
The elements constituting the circuit may be MOSFETs (insulated gate field effect transistors) in addition to bipolar transistors and resistive elements such as those mentioned above. Sand 2″
) H. This invention is applicable not only to linear ICs using bipolar transistors, but also to digital ICs using bipolar transistors and MOS type LSIs. Alternatively, it may be constructed from a combination of a MOS FET and an Ibora type transistor.

The present invention can be widely used in semiconductor integrated circuit devices and their layout methods.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, connections between blocks that are arranged in a hierarchical manner can be made directly on the edges of the blocks as much as possible, or by using the block layout method described above, wiring between blocks can be reduced. Is it possible to omit or reduce the number of channels?It is possible to reduce the chip size.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of an embodiment of a semiconductor integrated circuit device formed by the automatic layout method according to the present invention, FIG. 2 is a layout diagram showing an embodiment of the block, and FIG. FIG. 4 is a layout diagram showing an example of connection between adjacent blocks. FIG. 4 is a layout diagram showing an example of connection between distant blocks. FIG. 5 is an example of connection when there is a gap between blocks. A layout diagram showing an embodiment; FIG. 6 is an overall layout diagram showing an embodiment of a semiconductor integrated circuit device to which the present invention is applied; FIG. 7 is a layout diagram showing an example of a conventional semiconductor integrated circuit device. , FIG. 8 is a correlation diagram for explaining the element density and the number of elements of a semiconductor integrated circuit device.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device characterized in that it is configured by hierarchically arranging blocks, and wiring connecting blocks is connected as directly as possible on the sides of the blocks. 2. A semiconductor integrated circuit characterized in that when one semiconductor integrated circuit is constructed by arranging blocks hierarchically, each block is laid out so that the wiring connecting between the blocks is directly connected as much as possible on the side of the block. Equipment layout method. 3. In a block sandwiched between blocks to be connected, provide a wiring that passes through the blocks, and assign a plurality of dummy external terminals to the end points of the wiring, and connect each dummy external terminal to the external terminal of the block to be connected. 3. A semiconductor integrated circuit device and its layout method according to claim 1 or 2, wherein the semiconductor integrated circuit device and its layout method are connected.