JPH0474010A - Differential amplifier - Google Patents

Abstract

PURPOSE:To realize the differential amplifier whose offset voltage is easily obtained or adjustable by connecting transistors(TRs) and resistor as specified between input terminals so as to decrease a gain change due to a change in the voltage level of an input signal. CONSTITUTION:A differential amplifier circuit comprising elements Q3, Q4 and resistors R3, R4 is connected in parallel with a differential amplifier circuit comprising TRs Q1, Q2 and resistors R1, R2 and a current flowing to load resistors R5, R6 is divided into the elements Q1-Q4 pairs being components of plural differential amplifier circuits. As a result, it is not required to connect many temperature semiconductor elements in series with the load resistors. TRs Q7, Q8 connecting in series with the R5, R6 act like temperature compensation for the elements Q1-Q4 and also act like gain adjustment elements in response to the voltage adjustment of a base bias power terminal 4. The elements Q5, Q6 form a cascode amplifier. An offset voltage (DC bias voltage) is obtained between output terminals 6, 7 by varying the voltage of a base bias power terminal 9 and the voltage of a base bias power terminal 10, thereby adjusting the offset voltage.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is capable of reducing changes in gain caused by changes in a human input signal, and also allows easy obtaining or adjustment of an offset voltage. The present invention relates to a differential amplifier that can be used in various ways.

[Prior Art] In a differential amplifier, if the voltage level of an input signal changes, the collector current and voltage of a pair of transistors also change. As a result, the temperature of the base-collector junction of the pair of transistors changes, causing a change in the base-emitter voltage VBE. When the base-emitter voltage VBE of a pair of transistors changes as a result of a change in junction temperature,
Since the collector current also changes, the gain of the differential amplifier eventually changes.

In order to solve this kind of problem, a method is proposed in which a temperature-compensating semiconductor element (a diode with a structure in which the collector and base of a transistor are shorted) having a PN junction is connected in series with the load resistance of a differential amplifier. It is disclosed in Publication No. .605.906.

[Problems to be Solved by the Invention] The gain of a differential amplifier is generally determined by the value of an emitter feedback resistor and the value of a load resistor connected between the emitters of a pair of transistors. In the case where the temperature-compensating semiconductor elements (diodes) disclosed in the above-mentioned US patent publication are connected in series with a load resistor, when n temperature-compensating semiconductor elements are connected, the load resistance value changes stepwise. As a result, in order to obtain the target gain, the value of the emitter feedback resistor or load resistor must be set to an appropriate value.

Furthermore, when a large number of temperature compensation semiconductor elements (diodes) are connected in series with a load resistor, it becomes necessary to increase the value of the collector power supply voltage Vcc of the differential amplifier by that amount, making it difficult to drive at a low voltage.

By the way, there are cases where it is desired to output a signal accompanied by an offset voltage (DC bias voltage) from the differential amplifier. In order to meet this requirement, in the case of a typical differential amplifier or the differential amplifier shown in the above-mentioned US patent publication, a bias power supply (offset voltage power supply) must be connected to one of the pair of input terminals. When a bias power supply is connected to one of the input terminals in this way, it becomes difficult to apply input signals differentially. Furthermore, noise from the bias power supply becomes a problem. For example, as shown in FIG. 2, a pair of input terminals 11.
In a differential amplifier circuit having a multi-stage (three-stage) configuration in which first, second, and third differential amplifiers AMPI, AMP2, and AMP3 are connected in order between 12 and a pair of output terminals 13 and 14, each DC Assuming that the gains are Gl, G2, and G3, and the respective input conversion noises are Vnl, Vn2, and Vn3,
The output noise v nout is as shown in the following equation.

Vnout-[(Vni Gl +Vn2) G2 +
Vn3] G3-vnl・G1-G2・G3+■n2・
G2・G3+Vn3− G3 ・・・・・・(1)
Therefore, the input terminal 11.1 of the first stage differential amplifier AMPI
When a bias power supply (offset voltage power supply) is connected to one of 2, the noise component of 2 or the subsequent differential amplifier AMP2
, AMP3 are sequentially amplified, and the noise components at the output terminals 13 and 14 become larger.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to reduce changes in gain due to changes in the voltage level of an input signal, enable low voltage operation, and provide output without relying on a bias voltage at the input terminal. The object of the present invention is to provide a differential amplifier that can provide or adjust a bias voltage (offset voltage).

[Means for Solving the Problems] To achieve the above object, the present invention will be described with reference to the reference numerals in the drawings showing the embodiments. a first transistor Q1 whose base is connected to input terminal 1 of
a second transistor Q2 whose base is connected to;
a third transistor Q3 whose base is connected to the first input terminal 1; a fourth transistor Q4 whose base is connected to the second input terminal 2; and an emitter of the first transistor Q1. and the second transistor Q
between the emitter of the third transistor Q3 and the emitter of the fourth transistor Q4; third and fourth resistors R3 and R4 connected and connected in series with each other;
and a first current source ISI connected to the connection point of the second resistors R1 and R2; a second current source IS2 connected to the connection point of the third and fourth resistors R3 and R4; a fifth transistor Q5 whose emitter is connected to the collector of the first transistor Q1 and whose base is connected to the first base bias power supply terminal 3; a sixth transistor Q6 connected to the collector of the transistor Q2, and whose base is connected to the first base bias power supply terminal 3;
a second base bias power supply terminal 4;
a seventh transistor Q7 whose base is connected to the base bias power supply terminal 4; an eighth transistor Q8 whose base is connected to the second base bias power supply terminal 4; A fifth resistor R5 connected between the emitter of transistor Q7 of
and the collector of the sixth transistor Q6 and the eighth transistor Q6.
The sixth transistor Q8 is connected between its emitter and the emitter of the transistor Q8.
resistor R6, the first collector power supply terminal 5, and the first collector power terminal 5.
seventh and eighth resistors R7 and R8 connected between the collector power supply terminal 5 and the seventh and eighth transistors Q7 and G8, respectively; and a seventh resistor R7 and R8 connected to the collector of the fifth transistor Q5. 1 output terminal 6 and a second output terminal 7 connected to the collector of the sixth transistor Q6.
, a second collector, the eighth transistor, a third base bias power supply terminal 9, and an emitter of the third transistor Q.
a ninth transistor Q9, whose collector is connected to the second collector and the eighth transistor, and whose base is connected to the third base bias power supply terminal 9;
and a tenth transistor QIO whose emitter is connected to the collector of the fourth transistor Q4, whose collector is connected to the collector of the sixth transistor Q6, and whose base is connected to the third base bias power supply terminal 9.
and a fourth base bias power supply terminal 10, the emitter of which is connected to the collector of the third transistor Q3, the collector of which is connected to the collector of the fifth transistor Q5, and the base of which is connected to the fourth base bias power supply terminal. 10
an eleventh transistor Qll connected to the fourth transistor Qll, and an emitter connected to the collector of the fourth transistor Q4;
a collector connected to the second collector and the eighth;
This relates to a differential amplifier comprising a twelfth transistor Q12 whose base is connected to the base bias power supply terminal 10.

[Function] In the differential amplifier of the present invention, the third and fourth transistors Q3, Q4 and third and fourth resistors R3, R
A second differential amplifier circuit consisting of 4 and 4 is substantially connected in parallel. Therefore, the current flowing through the fifth and sixth resistors R5 and R6 as load resistors is divided between the plurality of pairs of transistors Q1 to Q4 of the differential amplifier circuit. As a result, it becomes unnecessary to connect a large number of temperature compensation semiconductor elements in series with the load resistor. Seventh and eighth transistors Q7 and Q8 connected in series to the fifth and sixth resistors R5 and Re.
serves as a temperature compensation terminal for the first to fourth transistors Q1 to Q4, and serves as a second base bias power supply terminal 4.
It also functions as a gain adjustment element in response to voltage adjustment. The fifth and sixth transistors Q5 and Q6 constitute a cascode amplifier. By changing the voltage of the third base bias power supply terminal 9 and the voltage of the fourth base bias power supply terminal 10, it is possible to obtain or adjust an offset voltage (DC bias voltage) between the output terminals 6 and 7. become.

[Embodiment] Next, a differential amplifier according to an embodiment of the present invention will be described with reference to FIG.

This differential amplifier has first and second input terminals 1.2,
NPN type first to twelfth transistors Q1 to Q12, first to eighth resistors R1 to R8, first and second constant current sources ISI and IS2, first and second, third and It consists of a fourth base bias power supply terminal 3.4.9.10, first and second collector power supply terminals 5.8, and first and second output terminals 6.7.

The bases of the first pair of transistors Ql and Q2 are connected to the first and second input terminals 1
．． 2, these emitters are connected to the first and second
are connected to each other via resistors R1 and R2, and a first constant current source S1 is connected between the connection midpoint of the first and second resistors R1 and R2 and the ground.

The bases of the third and fourth transistors QB, Q4, which are the second pair of transistors, are connected to the first and second input terminals 1
．． 2, and these emitters are connected to the third and fourth emitters, respectively.
are connected to each other via resistors R3 and R4, and a second constant current source IS2 is connected between the connection midpoint of the third and fourth resistors R3 and R4 and the ground.

The emitter of the fifth transistor Q5 is connected to the collector of the first transistor Q1. It is connected to the collector power supply terminal 5.

The emitter of the sixth transistor Q6 is connected to the collector of the second transistor Q2, and the collector is connected to the first collector power supply terminal 5 via a sixth resistor R8, an eighth transistor Q8, and an eighth resistor R8. It is connected.

A first base bias power supply terminal 3 providing voltage vbl is connected to the bases of fifth and sixth transistors Q5 and Q6, respectively.

A second base bias power supply terminal 4 that provides voltage Vb2 is connected to the bases of seventh and eighth transistors Q7 and Q8.

The first and second output terminals 6.7 are connected to the collectors of the fifth and sixth transistors Q5 and QB, respectively.

The emitter of the ninth transistor Q9 is connected to the collector of the third transistor Q3, the collector is connected to the second collector and the eighth transistor, and the base is connected to the third base bias power supply terminal 9.

The emitter of the tenth transistor QIO is connected to the collector of the fourth transistor Q4, the collector is connected to the collector of the sixth transistor Q6, and the base is connected to the third base bias power supply terminal 9.

The emitter of the eleventh transistor Qll is connected to the collector of the third transistor Q3, the collector is connected to the collector of the fifth transistor Q5, and the base is connected to the fourth base bias power supply terminal 10.

The emitter of the twelfth transistor Q12 is connected to the collector of the fourth transistor Q4, the collector is connected to the second collector and the eighth transistor, and the base is connected to the fourth base bias power supply terminal 10.

Note that the first, second, third and fourth resistors R1, R2, R
3, R4 has substantially the same value, the fifth and sixth resistors R5, R6 also have substantially the same value, and the seventh and eighth resistors R5 and R6 also have substantially the same value;
The resistors R7 and R8 also have substantially the same value. Also,
R1-R2-R3-R4-R5-Re -(3/2)・
The values of each of the resistors R1 to R8 are set so that R7-(3/2)/R8-RO. Also, the first pair of transistors Q1 and Q2 have substantially the same electrical characteristics, and similarly the second pair of transistors Q3 and Q4, the third
a pair of transistors Q5 and Q6, a fourth pair of transistors Q7 and Q8, a fifth pair of transistors Q9, QIO1
The sixth pair of transistors Qll, Q12 each have substantially the same electrical characteristics. Further, the first and second constant current sources ISI and IS2 supply currents of substantially the same value, and are composed of, for example, a combination of a DC power source and a resistor or a current control semiconductor element. Further, the first and second collector power terminals 5.8 and the first, second, third and fourth base bias power terminals 3.4.9.10 are each connected to a constant voltage source. Further, at least one of the third and fourth base bias power supply terminals 9.10 is connected to a variable constant voltage source.

[Operation] When the signals e1 and Q2 are applied to the input terminals 1.2 of this differential amplifier, an output voltage corresponding to el-Q2 is obtained between the output terminals 6.7 as in a typical differential amplifier. .

Seventh and eighth transistors Q7 and Q8 connected in series to fifth and sixth resistors R5 and R6 as load resistances.
are two pairs of transistors Ql, Q2, Q for amplification
3. It functions as a compensation for the base-emitter voltage VBE of Q4. The ninth, tenth, eleventh and twelfth transistors Q9, QLOlQll, Q12 are the first, second,
The fifth and sixth transistors Ql, Q2, Q5,
This is for configuring the shunt circuit of Q6.

Incidentally, the gain Gd2 of the differential amplifier circuit including the third and fourth transistors Q3 and Q4 can be expressed by the following equation.

Gd2- [(R5+ R6+ r e7+ r Q8
)/(R3+R4+re3+re4)] (1/2
)...(2) Here, re3, re4, re7, re8 are the third and fourth
, seventh and eighth transistors Q3, Q4, Q7, Q8
is the emitter resistance of

1/2 in equation (2) means that the collector current of the third transistor Q3 is divided and flows to the ninth and eleventh transistors Q9 and QIL, and the collector current of the fourth transistor Q4 is divided and flows to the tenth transistor Q9. and flows to the twelfth transistor QIO1Q12. here,
Transistors Q9Q12, QIO and Qll are used as an output pair, and the base potential is the transistor Q9 and QLOlQl.
Since l and Q12 are bare, each output bear (Q9 and Q
The added value of 12 and the added value of QlO and Qll are equal values. The gain Gd2 in equation (2) above is the third and fourth gain Gd2.
Base bias power supply terminal 9.10 voltage Vb3, Vb
It is always constant regardless of the value of 4. That is, R5-R6-R
3-R4 and r e7+ r e8- r e3+ r
If e4, Kane Gd2 becomes 1/2.

Therefore, for example, the fourth base bias voltage Vb4 is set to Vb
3, the collector current of the third transistor Q3 is increased to the eleventh transistor Qll while the gain Vb2 remains fixed at 1/2, and conversely the amount of the collector current of the third transistor Q3 is increased to the eleventh transistor Qll. 10th transistor QIO
As a result, the current flowing through the fifth resistor R5 serving as one load resistor increases and the current flowing through the sixth resistor R6 serving as the other load resistor decreases.
7, a DC bias voltage (offset voltage) can be obtained.

Further, when the fourth base bias voltage Vb4 is lowered from Vb3, the collector current of the third transistor Q3 is shunted to the eleventh transistor Qll, and conversely, the collector current of the fourth transistor Q4 is shunted to the eleventh transistor Qll. The shunt to the transistor QIO of 10 is increased, resulting in a decrease in the current in the fifth resistor R5 and an increase in the current in the sixth resistor R6.

Even when the voltage Vb3 of the third base bias power supply terminal 9 is changed, a current change similar to that when the fourth base bias voltage Vb4 is changed occurs.

The bias current (offset current) flowing through the resistors R5 and R6 is adjusted by the third and fourth base bias voltages Vb3.
, Vb4 can also be adjusted.

The emitters of the first and second transistors Ql and Q2
The collector-collector voltages of the third and fourth transistors Q3 and Q4 are equal to each other, and the emitter-collector voltages of the seventh and eighth transistors Q7 and Q8 are equal to each other. Appropriately set collector power supply voltages Vccl, vcc2, base bias power supply voltages Vbl, Vb2, Vb3, and Vb4, and R1-R2-R3-R4-R5-R6-2・R
7/3-2/old/3-RO, and the emitter resistance re of each transistor Q1 to Q12
If l~re12 is reO, and RO is sufficiently larger than reO, that is, RO)reO, then the differential gain Gd between the input terminal 1.2 and the output terminal 6.7 is expressed by the following equation.

Gd −(R5+R6+ re7+ Pc8) / (
10R2+ r eL+r e2) + [(R5+R8+ re7+ Pc8) / (R
3+R4+ re3+ Pc4) ] ・l/221
゜5 ・・・・・・(3) Amount of change in voltage between base and emitter of transistor ΔVB
Since E depends on the amount of change ΔT in the junction temperature, and ΔT depends on the amount of change ΔPC in power loss, the following equation holds true.

ΔV BB/ΔPC-(ΔV BE/ΔT) (Δ
T/ΔPC) ・・・・・・(4) First, second
, third, fourth, seventh and eighth transistors Q1, Q2
, Q3, Q4, Q7, and Q8 as VBEI, VBE2, VBE3, and VB, respectively.
E4, VBE7, and VBE8, and the respective changes due to the input signal V1n are ΔV BEI, ΔVBE2, and Δ
If VBE3, ΔVBE4, ΔVBE7, ΔVBE8, then the sum of the emitter currents of the first and second transistors Ql, Q2 and the third and fourth transistors Q3, Q
The added value of the emitter currents of the 4th and 11th transistors Q10 and Qll becomes equal, and the added value of the emitter currents of the 3rd and 4th transistors Q3 and Q4 becomes 1/2 of the added value of the emitter currents of the 3rd and 4th transistors Q3 and Q4. Therefore, the emitter current of the seventh transistor Q7 has a value 1.5 times that of the emitter currents of the first and third transistors Q1 and Q3, and similarly, the emitter current of the eighth transistor Q8 is It has a value 1.5 times the emitter current of the second and fourth transistors Q2 and Q4.

First to fourth transistors Ql, Q2, Q3, Q4
and seventh and eighth transistors Q7. Q8 shift loss ΔPC1, ΔPc2, ΔPC3, ΔPC3,
ΔPC4, Pc7, and ΔPc8 have the following relationship.

APCI -ΔPc3- (2/3)-ΔPC7...
...(5) ΔPC2-ΔPC4-(2/3)-APC8...(6
) Therefore, the bases of transistors Q1 to Q4, Q7, and Q8
The amount of change in the emitter voltage can be expressed by the following equation.

ΔVBEI −ΔV BF2− (2/3) ・ΔV
BF7 ・(7)ΔVBE2− ΔVBE4− (
2/3) -ΔVBE8- (8) The change in the transistor base-emitter voltage VBE operates as if the input signal Vin had changed, but in this amplifier, the gain Gd' due to ΔVBE is expressed by the following formula. Express.

△VBE7 (2/3) △VBEI! G d −−1,5 (9) ΔVBE1 (−ΔVBE3) ΔVBEI, that is, a constant gain can be maintained regardless of changes in the base-emitter voltage VBH based on the input signal.

Furthermore, in this differential amplifier, the compensation transistors Q7 and Q8 can be made into one stage by connecting a plurality of pairs of transistors Ql, Q2 and Q3, Q4 in parallel. Therefore, low voltage operation is possible.

Furthermore, when the differential amplifier shown in FIG. 1 is connected to the third stage (final stage) differential amplifier AMP3 of the circuit shown in FIG. (DC bias voltage) output terminal] 3.14
It will be possible to get it in time.

Therefore, compared to the conventional method of applying a bias voltage to either of the input terminals 11 or 12, the noise component based on the offset voltage (DC bias voltage) is reduced.

[Effects of the Invention] As described above, according to the present invention, it is possible to easily obtain or adjust the offset voltage (bias voltage) without changing the gain based on the change in the input signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a differential amplifier according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a multi-stage connected differential amplifier circuit. 1.2...Input terminal, 3,4,9.10...Base bias power supply terminal, 5,8...Collector power supply terminal, 6
．． 7... Output terminal, Q1-Q12... Transistor, R1-R12... Resistor, I Sl, I S2...
...Constant current source.

Claims (1)

[Claims] [1] First and second input terminals (1) (2); a first transistor (Q1) whose base is connected to the first input terminal (1); a second transistor (Q2) whose base is connected to the second input terminal (2); a third transistor (Q3) whose base is connected to the first input terminal (1); a fourth transistor (Q4) whose base is connected to the second input terminal (2); an emitter of the first transistor (Q1) and the second transistor (Q4);
and the emitter of the transistor (Q2) and are connected in series with each other.
1) (R2), the emitter of the third transistor (Q3) and the fourth
and the emitter of the transistor (Q4) and are connected in series with each other.
3) (R4), a first current source (IS1) connected to the connection point of the first and second resistors (R1) (R2), and the third and fourth resistors (IS1);
A second current source (IS2) connected to the connection point of the resistors (R3) (R4) and a first base bias power supply terminal (3
), a fifth transistor (Q5) whose emitter is connected to the collector of the first transistor (Q1) and whose base is connected to the first base bias power supply terminal (3); a sixth transistor (Q6) connected to the collector of the transistor (Q2) and whose base is connected to the first base bias power supply terminal (3); a second base bias power supply terminal (4); a seventh transistor (Q7) whose base is connected to the second base bias power supply terminal (4); and an eighth transistor (Q8) whose base is connected to the second base bias power supply terminal (4). , the collector of the fifth transistor (Q5) and the seventh transistor
a fifth resistor (R5) connected between the emitter of the sixth transistor (Q6) and the eighth transistor (Q6);
a sixth resistor (R6) connected between the emitter of the transistor (Q8); a first collector power terminal (5); and the first collector power terminal (5) and the seventh and seventh resistor (R6); 8
a seventh and eighth resistor (R7) (R8) connected between the transistors (Q7) (Q8), respectively; and a first output terminal connected to the collector of the fifth transistor (Q5). (6), a second output terminal (7) connected to the collector of the sixth transistor (Q6), a second collector power supply terminal (8), and a third base bias power supply terminal (9). and the emitter is connected to the collector of the third transistor (Q3), and the collector is connected to the second collector power supply terminal (Q3).
8), and a ninth transistor (Q9) whose base is connected to the third base bias power supply terminal (9);
and the emitter is connected to the collector of the fourth transistor (Q4), and the collector is connected to the collector of the sixth transistor (Q6).
), the base of which is connected to the third base bias power terminal (9), and the fourth base bias power terminal (10
), the emitter is connected to the collector of the third transistor (Q3), the collector is connected to the collector of the fifth transistor (Q5), and the base is connected to the fourth base bias power supply terminal (10). The eleventh transistor (Q11) has an emitter connected to the collector of the fourth transistor (Q4), a collector connected to the second collector power supply terminal (8), and a base connected to the fourth base A differential amplifier consisting of a twelfth transistor (Q12) connected to a bias power supply terminal (10).