JPH0473286B2 - - Google Patents
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- Publication number
- JPH0473286B2 JPH0473286B2 JP20490483A JP20490483A JPH0473286B2 JP H0473286 B2 JPH0473286 B2 JP H0473286B2 JP 20490483 A JP20490483 A JP 20490483A JP 20490483 A JP20490483 A JP 20490483A JP H0473286 B2 JPH0473286 B2 JP H0473286B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- layer
- semiconductor
- thin film
- superlattice
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 13
- 239000010409 thin film Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 9
- 239000010408 film Substances 0.000 claims description 7
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 description 9
- 238000001459 lithography Methods 0.000 description 6
- 239000000969 carrier Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000000737 periodic effect Effects 0.000 description 4
- 230000000704 physical effect Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Drying Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は、微細構造素子および多次元超格子等
を製作する上で基礎となる多層膜の製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer film, which is the basis for manufacturing microstructure elements, multidimensional superlattices, and the like.
近年、半導体を用いた超格子が注目されてお
り、その際立つた物性が議論を呼んでいる。現在
製作されているすべての超格子は、分子線エピタ
キシ法等を用いて製作される異なる薄膜結晶を交
互に周期的に重ね合せた構造の１次元超格子であ
る（第１図ａにGaAs／AlAs系を用いた場合を示
す）。この１次元超格子は異なるバンドギヤツプ、
異なる電子親和力を有する異種半導体薄膜を上述
のように周期的に重ねることにより、第１図ｂに
示すような周期的に変化するバンド構造を形成す
るため、半導体薄膜１（GaAs層）中にキヤリア
の束縛状態（量子準位）を生起せしめるものであ
る。ここで、黒丸印は電子を、白丸印は正孔を示
している。この量子準位の位置は半導体薄膜１の
厚さによつて変るため、ここに束縛されたキヤリ
ア（電子と正孔）の再結合に伴う発光の波長を超
格子の周期を変えることによりかなり自由に変え
ることができるという特徴を有している（N.
Holonyak etal.，“Journal of Applied
Physics”，52（1981）7201参照）。この１次元超格
子の他に、異なる棒状結晶を交互に周期的に束ね
た形の２次元超格子（第２図参照）、異なる角状
結晶を交互に周期的に積み重ねた形の３次元超格
子（第３図参照）も原理的には存在する。一般
に、ｎ次元超格子（ｎ＝１，２，３）におけるキ
ヤリアの自由度は３−ｎ次元の空間となる。従つ
て、例えばｎ次元超格子を用いたレーザでは、そ
のしきい値電流の温度依存性がｎの増大と共に少
なくなるという（Y.Arakawa and H.Sakaki，
“Applied Physics Letters”，40（1982）939参照）
キヤリアの束縛の程度を反映した現象が期待され
る。また、ｎの増大と共にキヤリアの存在する空
間の次元（３−ｎ）が減少するため、空間内に存
在する不純物等によるキヤリアの散乱方向の自由
度が減少して結果的に散乱頻度が減少し、高速輸
送状態が実現されるものと期待されている（H.
Sakaki，“Japanese Journal of Applied
Physics”，19（1980）L735参照）。このように、
多次元超格子は１次元超格子以上に興味深い物性
を示すと予想されるため、光デバイス、高速電子
デバイスへの応用が期待されている。従つて、こ
れらの多次元超格子が実際に製作されてその際立
つた物性が明らかになれば、新しい学問分野を形
成することは必至であると考えられる。しかし、
これら多次元超格子を製作する方法の発表は現在
のところ未だない。近年の高度に発達したリソグ
ラフイ技術を用いて周期的なパターンを形成した
基板上に１次元超格子の成長を行なう方法は多次
元超格子製作に対する１つの解答であるが、この
場合の超格子の周期はリソグラフイ技術により制
限される（現状では20.1μｍ）。従つて、現状の
リソグラフイ技術に依存する限り超格子本来の特
性を発揮する10−100Å周期の多次元超格子を製
作することは不可能といえる。 In recent years, superlattices using semiconductors have attracted attention, and their outstanding physical properties have sparked debate. All superlattices currently manufactured are one-dimensional superlattices with a structure in which different thin film crystals are alternately and periodically superposed using molecular beam epitaxy (see Figure 1a). (The case using AlAs system is shown). This one-dimensional superlattice has different band gaps,
By periodically stacking different types of semiconductor thin films having different electron affinities as described above, carriers are formed in the semiconductor thin film 1 (GaAs layer) to form a periodically changing band structure as shown in Figure 1b. This causes a bound state (quantum level) to occur. Here, black circles indicate electrons, and white circles indicate holes. Since the position of this quantum level changes depending on the thickness of the semiconductor thin film 1, the wavelength of the light emitted due to the recombination of the carriers (electrons and holes) bound here can be considerably controlled by changing the period of the superlattice. It has the characteristic that it can be changed to (N.
Holonyak et al., “Journal of Applied
Physics”, 52 (1981) 7201).In addition to this one-dimensional superlattice, there are two-dimensional superlattices in which different rod-shaped crystals are bundled together periodically (see Figure 2), and different angular crystals are arranged in alternating bundles. In principle, a three-dimensional superlattice (see Figure 3) exists in which the carriers are stacked periodically.Generally, the degrees of freedom of carriers in an n-dimensional superlattice (n = 1, 2, 3) are 3-n. Therefore, for example, in a laser using an n-dimensional superlattice, the temperature dependence of the threshold current decreases as n increases (Y. Arakawa and H. Sakaki,
(See “Applied Letter Physics,” 40 (1982) 939)
We can expect a phenomenon that reflects the degree of carrier restraint. In addition, as n increases, the dimension (3-n) of the space in which the carrier exists decreases, so the degree of freedom in the scattering direction of the carrier due to impurities existing in the space decreases, and as a result, the scattering frequency decreases. , it is expected that high-speed transportation conditions will be realized (H.
Sakaki, “Japanese Journal of Applied
Physics”, 19 (1980) L735). Thus,
Multidimensional superlattices are expected to exhibit more interesting physical properties than one-dimensional superlattices, and are therefore expected to find applications in optical devices and high-speed electronic devices. Therefore, if these multidimensional superlattices are actually fabricated and their outstanding physical properties are revealed, it is inevitable that a new academic field will be formed. but,
At present, there has been no publication of a method for producing these multidimensional superlattices. The method of growing a one-dimensional superlattice on a substrate with a periodic pattern using the highly developed lithography technology of recent years is one solution to the fabrication of a multidimensional superlattice. The period is limited by lithography technology (currently 20.1 μm). Therefore, it can be said that it is impossible to fabricate a multidimensional superlattice with a period of 10-100 Å that exhibits the characteristics inherent to a superlattice as long as it relies on current lithography technology.
本発明は、以上に述べたリソグラフイ技術の限
界を認識した上で全く新たな発想により超微細な
構造素子および多次元超格子等を製作し得る多層
膜の製造方法を提供するものである。 The present invention recognizes the limitations of the lithography technology described above and provides a method for producing a multilayer film that can produce ultrafine structural elements, multidimensional superlattices, etc. based on a completely new idea.
以下本発明を詳細に説明する。 The present invention will be explained in detail below.
本発明の多層膜製造方法を、ヘテロ接合におけ
る格子整合性が良く現在１次元超格子の製作が最
も進んでいるGaAs／AlAs系を用いた２次元超格
子の製作に適用した例について述べる。製作すべ
き２次元超格子は断面が100Å×100ÅのGaAsお
よびAlAsの棒状結晶を交互に各５層並べて束ね
全体が断面1000Å×1000Åの棒状をなす構造であ
る（第８図参照）。以下に記す(1)〜(5)は、この２
次元超格子の製作工程である。 An example will be described in which the multilayer film manufacturing method of the present invention is applied to the production of a two-dimensional superlattice using GaAs/AlAs, which has good lattice matching in a heterojunction and is currently the most advanced in the production of one-dimensional superlattices. The two-dimensional superlattice to be fabricated has a structure in which five layers each of GaAs and AlAs rod-shaped crystals with a cross section of 100 Å x 100 Å are arranged alternately and bundled to form a rod-like structure with a cross section of 1000 Å x 1000 Å (see Figure 8). (1) to (5) below are these two
This is the manufacturing process of a dimensional superlattice.
(1) 第４図は薄膜成長層の断面図である。分子線
エピタキシ法を用いてGaAs基板３の上に厚さ
100ÅのAlAs層２，GaAs層１を交互に成長し、
厚さ1000Åの１次元超格子を製作する。(1) Figure 4 is a cross-sectional view of the thin film growth layer. A thick layer is deposited on the GaAs substrate 3 using the molecular beam epitaxy method.
AlAs layer 2 and GaAs layer 1 of 100 Å are grown alternately,
Fabricate a one-dimensional superlattice with a thickness of 1000 Å.
(2) 成長面に交叉する面（例えば垂直な面）でへ
き開し、結晶を横転する（第５図）。(2) Cleave on a plane that intersects the growth plane (for example, a vertical plane) and roll the crystal over (Figure 5).
(3) へき開面に対しプラズマエツチングを行ない
GaAs層１の部分のみを100Å選択エツチング
する（第６図）。(3) Perform plasma etching on the cleavage plane
Only the portion of GaAs layer 1 is selectively etched by 100 Å (FIG. 6).
(4) 選択エツチングにより段差ができた表面上
に、再び(1)と同様に、分子線エピタキシ法を用
いてGaAs層１を100Å成長し、引続きAlAs層
２を100Å成長させることにより、１次元的な
超格子成長を行う（第７図）。(4) On the surface with steps formed by selective etching, GaAs layer 1 is grown to 100 Å using the molecular beam epitaxy method again in the same manner as in (1), and then AlAs layer 2 is grown to 100 Å, thereby creating a one-dimensional structure. A typical superlattice growth is performed (Figure 7).
(5) GaAs層，AlAs層を各５層成長することによ
り断面が1000Å×1000Åの２次元超格子を得
る。第８図は、紙面に垂直な方向に100Å×100
Å断面の棒状結晶が多数束になつた構造の断面
を示している。(5) A two-dimensional superlattice with a cross section of 1000 Å x 1000 Å is obtained by growing 5 GaAs layers and 5 AlAs layers each. Figure 8 is 100Å x 100mm in the direction perpendicular to the paper.
It shows a cross section of a structure in which many rod-shaped crystals with a cross section of Å are bundled.
以上の工程によりGaAs／AlAs2次元超格子を
製作することができる。さらに、第８図の構造に
上記(2)以降の工程を施すことにより３次元超格子
を製作することもできる。この２次元超格子を製
作する上で重要な工程は(3)と(4)である。 Through the above steps, a GaAs/AlAs two-dimensional superlattice can be manufactured. Furthermore, a three-dimensional superlattice can also be manufactured by subjecting the structure shown in FIG. 8 to the steps from (2) above. The important steps in manufacturing this two-dimensional superlattice are (3) and (4).
まず、工程(3)について述べる。このような微細
構造の選択エツチングについては原子的な尺度で
の薄膜除去を可能にするドライエツチング装置が
存在しており（J.J.A.P，20（1981）L847，K.
Hikosaka et al参照）、これを用いることにより
達成される。この時、切れの良い選択エツチング
を行なうためには、イオンビームエツチングのよ
うな指向性のあるエツチングは不適当でありプラ
ズマエツチングのような化学反応に基づく指向性
の少ないエツチングが適している。 First, step (3) will be described. For selective etching of such fine structures, there is a dry etching device that enables thin film removal on an atomic scale (JJAP, 20 (1981) L847, K.
(see Hikosaka et al.). At this time, in order to perform selective etching with good sharpness, directional etching such as ion beam etching is inappropriate, and less directional etching based on chemical reaction such as plasma etching is suitable.
次に、工程(4)に関連して以下の２点に言及す
る。第１に、第８図に示すような規則正しい周期
構造を製作した場合、次に述べるような問題が発
生する。第８図に示すように、２次元超格子の場
合GaAsの単位格子（100Å×100Å断面の棒状結
晶）相互が紙面に垂直な方向の線を境界として隣
接しているため、GaAs単位格子間の障壁が極め
て薄く電子がトンネル効果により往来し、GaAs
単位格子中に電子を閉じ込めるという超格子の機
能を失つてしまう。この問題は、第８図のような
規則正しい周期構造でなく第９図に示すように、
AlAs層２をGaAs層１より厚くした成長を行なう
ことにより解決できる。第２に工程(4)において第
１０図ａに示すような側壁への成長（厚さd1）が
起き多次元超格子の形成を妨げる可能性がある点
である。この問題は指向性の良い分子線エピタキ
シ技術と指向性のないドライエツチング技術によ
り解決される。即ち、指向性の良い分子線エピタ
キシ技術を用いれば側壁への成長は第１０図ｂの
ように抑制することが可能である（d1＜d2）。次
に、成長後、成長面を指向性のないエツチング法
により厚さd1のエツチングを行なえば、第１０図
ｃに示すように側壁成長層は除去され、厚さd2−
d1の成長層を得る。 Next, the following two points will be mentioned in relation to step (4). First, when a regular periodic structure as shown in FIG. 8 is manufactured, the following problems occur. As shown in Figure 8, in the case of a two-dimensional superlattice, the GaAs unit cells (rod-shaped crystals with a cross section of 100 Å x 100 Å) are adjacent to each other with the line perpendicular to the plane of the paper as the boundary. GaAs
The superlattice loses its ability to confine electrons within the unit cell. This problem is due to the regular periodic structure shown in Fig. 9, rather than the regular periodic structure shown in Fig. 8.
This problem can be solved by growing the AlAs layer 2 to be thicker than the GaAs layer 1. Second, in step (4), growth (thickness d 1 ) on the side walls as shown in FIG. 10a may occur, which may impede the formation of a multidimensional superlattice. This problem can be solved by molecular beam epitaxy technology with good directionality and dry etching technology without directionality. That is, by using molecular beam epitaxy technology with good directionality, growth on the sidewalls can be suppressed as shown in FIG. 10b (d 1 <d 2 ). Next, after the growth, if the growth surface is etched to a thickness of d 1 using a non-directional etching method, the sidewall growth layer is removed and the thickness is reduced to d 2 - as shown in FIG. 10c.
Obtain d 1 growth layer.
以上、本発明の典型的な実施例を述べた。その
基本的手法は結晶のみならず非晶質にも、また、
半導体のみならず金属、絶縁体にも適用しうる。
その最大の特徴はリソグラフイを用いることなく
Å単位の微細構造を形成できる点にある。従つ
て、半導体、金属および絶縁体を含む構造への適
用により超短チヤンネル（〜10Å）FETを実現
することも期待できよう。 Typical embodiments of the present invention have been described above. The basic method is applicable not only to crystals but also to amorphous materials.
It can be applied not only to semiconductors but also to metals and insulators.
Its greatest feature is that it can form microstructures on the order of Å without using lithography. Therefore, it is expected that ultrashort channel (~10 Å) FETs will be realized by application to structures including semiconductors, metals, and insulators.
なお、一次元の格子構造を製造する場合は、第
７図に示すように、AlAs層２とGaAs層１を少な
くとも１層設けたものでもよい。 In addition, in the case of manufacturing a one-dimensional lattice structure, as shown in FIG. 7, at least one AlAs layer 2 and one GaAs layer 1 may be provided.
また、第６図のようにGaAs層１を選択性エツ
チングをした後にAlAs層２を先に積層してもよ
い。 Alternatively, as shown in FIG. 6, after selectively etching the GaAs layer 1, the AlAs layer 2 may be laminated first.
以上説明したように、本発明は成長薄膜の厚さ
を横方向のパターンとして再び薄膜成長を行なう
ものであるから従来のリソグラフイでは実現でき
ない微細な薄膜構造を形成できるという利点があ
る。 As explained above, since the present invention grows the thin film again by changing the thickness of the grown thin film into a horizontal pattern, it has the advantage of being able to form a fine thin film structure that cannot be achieved with conventional lithography.
第１図ａはGaAs／AlAs系による１次元超格子
を示す斜視図、第１図ｂは第１図ａに示した１次
元超格子に対応するエネルギーバンド図、第２図
はGaAs／AlAs系による２次元超格子を示す斜視
図、第３図はGaAs／AlAs系による３次元超格子
を示す斜視図、第４図はGaAs／AlAs系による１
次元超格子成長層の断面図、第５図は第４図の１
次元超格子成長層をへき開した後結晶を横転した
状態を示す正面図、第６図は第５図のへき開面に
対しGaAsの選択エツチングを施した状態を示す
正面図、第７図は第６図の選択エツチング面に再
び第４図と同様の１次元的な超格子を成長した状
態を示す正面図、第８図は製作された２次元超格
子を紙面に垂直な方向に棒状結晶が多数束になつ
た構造の断面を示す断面図、第９図は第７図にお
いてGaAs層より厚いAlAs層を成長した場合を示
す正面図、第１０図ａは第７図におけるGaAs層
の成長において側壁に成長が起る様子を示す断面
図、第１０図ｂは第７図におけるGaAs層の成長
において指向性の良い分子線エピタキシ法により
側壁への成長（厚さd1）が平面への成長（厚さ
d2）に比べて少ない（d1＜d2）様子を示す断面
図、第１０図ｃは第１０図ｂの成長後指向性のな
いエツチング法によりGaAs層を厚さd1分除去す
ることにより側壁成長層を取除いた様子を示す断
面図である。
１…GaAs層、２…AlAs層、３…GaAs基板。
Figure 1a is a perspective view showing a one-dimensional superlattice based on the GaAs/AlAs system, Figure 1b is an energy band diagram corresponding to the one-dimensional superlattice shown in Figure 1a, and Figure 2 is a perspective view showing a one-dimensional superlattice based on the GaAs/AlAs system. Figure 3 is a perspective view showing a three-dimensional superlattice based on GaAs/AlAs system, Figure 4 is a perspective view showing a three-dimensional superlattice based on GaAs/AlAs system.
A cross-sectional view of the dimensional superlattice growth layer, Figure 5 is 1 in Figure 4.
FIG. 6 is a front view showing the state in which the crystal is turned over after the dimensional superlattice growth layer has been cleaved, FIG. A front view showing that a one-dimensional superlattice similar to that shown in Figure 4 has been grown on the selected etching surface of the figure. 9 is a cross-sectional view showing the cross section of the bundled structure, FIG. 9 is a front view showing the case where the AlAs layer is grown thicker than the GaAs layer in FIG. 7, and FIG. FIG. 10b is a cross-sectional view showing how the growth occurs in the GaAs layer in FIG . thickness
Figure 10c is a cross-sectional view showing that the GaAs layer is removed by a thickness of d 1 using the non-directional etching method after growth as shown in Figure 10b . FIG. 3 is a cross-sectional view showing a state in which a sidewall growth layer has been removed. 1...GaAs layer, 2...AlAs layer, 3...GaAs substrate.
Claims (1)
体薄膜とを交互に積層し前記主面に垂直な方向に
一次元超格子を形成する第１の工程と、前記一次
元超格子を前記基板に交叉する面に沿つて切断す
る第２の工程と、該切断により生じた前記第１の
半導体薄膜と前記第２の半導体薄膜との積層多層
膜の断面が露出したる切断面の該第１の半導体層
又は該第２の半導体層のみを選択的にエツチング
する第３の工程と、該エツチングの行なわれた前
記切断面に該第１の半導体層と該第２の半導体層
を交互に少くとも一回積層する第４の工程とを含
む多層膜の製造方法。 ２ 前記第４の工程において積層される前記第１
の半導体層と前記第２の半導体層との各膜厚に差
をもたせたことを特徴とする特許請求の範囲第１
項記載の多層膜の製造方法。 ３ 前記第４の工程における前記第１の半導体層
又は前記第２の半導体層は指向性の良い分子線エ
ピタキシ技術による成長と該成長面に対する指向
性のないエツチングにより積層されることを特徴
とする特許請求の範囲第１項又は第２項に記載の
多層膜製造方法。 ４ 前記第１の半導体層がAlAs層であり前記第
２の半導体層がGaAs層であることを特徴とする
特許請求の範囲第１項，第２項又は第３項に記載
の多層膜の製造方法。[Claims] 1. A first step of alternately stacking a first semiconductor thin film and a second semiconductor thin film on the main surface of the substrate to form a one-dimensional superlattice in a direction perpendicular to the main surface; a second step of cutting the one-dimensional superlattice along a plane intersecting the substrate, and exposing a cross section of the laminated multilayer film of the first semiconductor thin film and the second semiconductor thin film produced by the cutting; a third step of selectively etching only the first semiconductor layer or the second semiconductor layer on the cut surface, and etching the first semiconductor layer and the second semiconductor layer on the etched cut surface; a fourth step of alternately stacking two semiconductor layers at least once. 2 The first layer laminated in the fourth step
Claim 1, characterized in that the semiconductor layer and the second semiconductor layer have different thicknesses.
2. Method for producing a multilayer film as described in Section 1. 3. The first semiconductor layer or the second semiconductor layer in the fourth step is layered by growth using a molecular beam epitaxy technique with good directionality and etching with no directionality on the growth surface. A multilayer film manufacturing method according to claim 1 or 2. 4. Manufacturing a multilayer film according to claim 1, 2, or 3, wherein the first semiconductor layer is an AlAs layer and the second semiconductor layer is a GaAs layer. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20490483A JPS6098615A (en) | 1983-11-02 | 1983-11-02 | Manufacture of multilayer film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20490483A JPS6098615A (en) | 1983-11-02 | 1983-11-02 | Manufacture of multilayer film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6098615A JPS6098615A (en) | 1985-06-01 |
| JPH0473286B2 true JPH0473286B2 (en) | 1992-11-20 |
Family
ID=16498310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20490483A Granted JPS6098615A (en) | 1983-11-02 | 1983-11-02 | Manufacture of multilayer film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6098615A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60113488A (en) * | 1983-11-24 | 1985-06-19 | Nec Corp | Manufacture of element having effect of one-dimensional quantum size |
| KR100580623B1 (en) * | 2003-08-04 | 2006-05-16 | 삼성전자주식회사 | Semiconductor device having super lattice semiconductor layer and manufacturing method thereof |
-
1983
- 1983-11-02 JP JP20490483A patent/JPS6098615A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6098615A (en) | 1985-06-01 |
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