JPH0471379B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention: Field of the Invention The present invention relates to a receive buffer circuit for a data terminal device.

Background Art In data terminal devices that process data while sending and receiving data via communication lines, the data transmission speed is generally lower than the processing speed of the data processing device installed in the terminal device, so the speed difference between the two is Buffer circuits are provided on the receiving and transmitting sides to buffer the

Conventionally, in a reception buffer circuit, one frame of transmitted reception data is continuously written into a buffer memory, and the written one frame of reception data is read word by word from the buffer memory in the order in which it was written and processed. Ta.

Problems to be Solved by the Invention In the conventional reception buffer circuit described above, the data processing device reads the received data by directly accessing the buffer memory, so it is necessary to synchronize the buffer control circuit and the data processing device. There is a problem that access waiting time occurs and reading takes time.

Means for Solving the Problems of the Structure of the Invention A reception buffer circuit of the present invention which solves the problems of the prior art described above has a buffer register that holds one word of reception data read from the buffer memory, and a buffer register that holds one word of reception data read from the buffer memory. When the received data reaches the amount of data for one frame, the first written word is read from this buffer memory and held in the buffer register, and then a request is made to the data processing device to start reading the received data. From now on, this data processing device will process 1 from the buffer register.
By providing a buffer control circuit that detects each word of received data every time it is read, reads the next word from the buffer memory, and holds it in the buffer register, the received data can be read from the buffer memory to the data processing device. Configured to increase speed.

Hereinafter, the operation of the present invention will be explained along with examples.

Embodiment FIG. 1 is a block diagram showing an example of the configuration of a data terminal device including a reception buffer circuit according to an embodiment of the present invention.

This data terminal device is a transmission control device 1 connected to a transmission line via a line termination device (not shown).
, a processor 2 for processing data, a reception buffer circuit 3 and a transmission buffer circuit 4 disposed between them, and an input/output device 6 connected to the processor 2 via an input/output interface circuit 5. ing.

The reception buffer circuit 3 includes a frame memory 10 for storing one frame of received data, an address counter 11, a timing control circuit 12, and a buffer register 13.

When the timing control circuit 12 receives a frame pulse indicating the start of one frame of received data separated by the transmission control unit 1 on the signal line a, the timing control circuit 12 resets the address counter 11 via the signal line b.
A read command is issued to the frame memory 10 via the signal line c. Thereafter, each time the control circuit 12 receives a predetermined number of clock signals reproduced by the transmission control unit and output on the signal line a, the control circuit 12 increments the contents of the address circuit 11 via the signal line b and controls the transmission. The received data converted into parallel data is written into the frame memory 10 one word at a time.

When the timing control circuit 12 receives a frame pulse on the signal line a indicating the end of one frame of received data separated by the transmission control section 1, it resets the address counter 11. Subsequently, the timing control circuit 12 reads the first word of the frame from the frame memory 10 by outputting a read command on the signal line c, and then reads the first word of the frame from the frame memory 10 by outputting a hold command on the signal line d. The first word read from 10 is held in buffer register 13. As a result, the first word of one frame of received data is transferred from the buffer memory 10 to the buffer register 13. When this transfer is completed, the timing control unit 1
2 requests the processor 2 to start reading one frame of received data by notifying the processor 2 of this via the signal line e.

Upon receiving this request, the processor 2 issues a transfer command on the signal line f at an appropriate time, reads out the first word received data from the buffer register 13, and processes it. When a transfer command appears on the signal line f, the timing control circuit 12 increments the address counter 11 via the signal line b, and increments the next one of the received data.
Transfer the word from frame memory 10 to buffer register 13. However, unlike the case of the first word, the processor is not notified.

Processor 2 issues a transfer command on signal line f at an appropriate time, reads out the second word of received data from buffer register 13, and processes it. When a transfer command appears on the signal line f, the timing control circuit 12 controls the address counter 11 via the signal line b.
and transfers the third word of the received data from the frame memory 10 to the buffer register 13.

Similarly, when the processing of one word of received data is completed, the processor 2 reads the next word from the buffer register 13 and reads the previous one.
When the timing control circuit detects that a word has been read from the buffer memory, it immediately transfers the following word to the buffer register 13. In this way, one frame of received data is read out to the processor 2 via the buffer register 13.

Although the configuration in which the reception buffer circuit is provided separately from the transmission control section has been exemplified above, it may be configured to be included in the transmission control section.

Effects of the Invention As explained in detail above, the reception buffer circuit of the present invention is capable of transferring one word of subsequent reception data from the buffer memory to the buffer register every time the data processing device reads one word of reception data from the buffer register. The data processing device and the buffer control circuit operate asynchronously to eliminate access waiting time for synchronization between the two, so received data in the buffer memory can be transferred to the buffer memory at high speed. This has the advantage that it can be read out to a processing device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a data terminal device including a reception buffer circuit according to an embodiment of the present invention. 1...Transmission control circuit, 2...Processor, 3...
...Reception buffer, 10...Frame memory, 11
... Address counter, 12 ... Timing control circuit, 13 ... Buffer register.

Claims (1)

[Scope of Claims] 1. A data terminal device in which a reception buffer memory is provided between a communication line and a data processing device, comprising: a buffer register for holding one word of reception data successively output from the reception buffer memory; When the received data that has been written reaches the amount of data for one frame, the first written word is read from the receive buffer memory and held in the buffer register, and then the start of reading the received data is From then on, each time this data processing device reads one word of received data from the buffer register, it detects this reading and causes the next one word to be read from the reception buffer memory and stores it in the buffer register. A reception buffer circuit for a data terminal device, comprising a control circuit for holding data.