JPH047133B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit test circuit using a shift counter.

[Conventional technology]

FIG. 2 is a circuit diagram showing a shift counter and its conventional test circuit. In the figure, 1 indicates flip-flops 11 to 15 connected in series to form a shift register and exclusive OR gate 16 for feedback. 2 is a decoder block consisting of decoders 20 to 24, 7 is a reset input terminal, 8 is an OR gate that calculates the logical sum of the input of reset input terminal 7 and the output T ₀ of decoder 20, Q ₁ to _{Q 5} is flipflop 11-15
outputs, 20-24 are flip-flops 11-1
A decoder that decodes the outputs Q ₁ to Q ₅ of 5, T ₀ to
_T4 is the decoded output of decoders 20-24, and φ is the clock of flip-flops 11-15.

Next, the operation will be explained. First, the state of the reset input terminal 7 is set to "H", and each flip-flop 11-15 is reset. At this time, the outputs Q ₁ to _{Q 5} of flip-flops 11 to 15 are “L”,
The output of the exclusive OR gate 16 is "H".

Next, when the state of the reset input terminal 7 is set to "L" while inputting the clock φ, the flip-flop 11 outputs the output of the exclusive OR gate 16, and the flip-flops 12 to 15 output the outputs Q ₁ to Q ₄ respectively.
and outputs its status at the next clock. Here, the decode output T ₀ of the decoder 20
If the shift counter 1 is not reset by 1, the shift counter 1 will count up by 1 per clock. How the “H” and “L” states of Q ₁ to _{Q 5} change and count up, and how many combinations of Q ₁ to Q ₅ there are, are determined by the output Q ₁ to _{Q 5}
The total number of combinations of outputs Q ₁ to _{Q 5} is 31, excluding the reset state, depending on the connection relationship between the shift counter 1 and the input terminal of the exclusive OR gate 16. . Decoder 20-2
4 decodes the states of the outputs Q ₁ to Q ₅ and sets the decoded outputs T ₀ to T ₄ to “H” for the states of the outputs Q ₁ to _{Q 5} of the set specific combination. degaud output
Since the shift counter 1 can be reset by _T0 , by appropriately setting the decoder 20, a desired number of counters can be realized.

Decode outputs T ₁ to _{T 4} of decoders 21 to 24 are connected to an external circuit to control it. Output T ₁
To test the external circuit controlled by ~ _T4 , reset input terminal 7 is changed from "H" to "L" to start counting of shift counter 1, and the output is
This is done by sequentially outputting T ₁ to _{T 4} and examining the operation of the external circuit.

[Problem that the invention seeks to solve]

Since the conventional shift counter is configured as described above, when testing the external circuit controlled by the decode outputs _T1 to _T4 , the reset input terminal 7 is changed from "H" to "L". The only way to do this is to start counting and output a set of decode outputs T ₁ to _{T 4} , and to see the operation of the external circuit due to this in sequence. For example, if you look at the operation of the external circuit due to only the decode output T ₁ , There was a problem in that it was not possible to test the operation of individual external circuits.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a test circuit that can separately test the operation of external circuits controlled by each decode output of a decoder.

[Means for solving problems]

The test circuit according to the present invention connects either the output of the feedback exclusive OR gate or the input from the external input terminal to the input terminal of the flip-flop of the least significant bit of the shift register constituting the shift counter. The input switching gates are connected, and the output of the feedback exclusive OR gate is selected during normal testing, and the input from the external input terminal is selected during external individual testing.

[Effect]

The test circuit according to the present invention arbitrarily sets the state of the shift register by sequentially inputting input data from the external input terminal to the shift register constituting the shift counter when performing an external individual test, and also performs decoding. Set the output as desired and output.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1, 2, 7, 8, 11 to 15, 16 and 20 to 24 are equivalent to those in the conventional test circuit shown in FIG. 3 is a switching gate that outputs either the output of the feedback exclusive OR gate 16 or the data input from the test setting data input terminal 4 in accordance with the switching control signal Test; 4 is the test setting data input terminal; 5 When the switching control signal Test is “H”
This is an AND gate that prohibits the reset of flip-flops 11 to 15 by the output of OR gate 8 when .

Next, the operation of the test circuit of this embodiment configured as described above will be explained. During normal operation (not testing), the switching control signal Test is set to “L”.
and causes the switching gate 3 to select the output of the exclusive OR gate 16. In this state, first reset input terminal 7 is set to "H", and each flip-flop 1
Reset 1 to 15. Next, when the reset input terminal 7 is set to "L" while inputting the clock φ, the shift counter 1 counts up by 1 every clock. Decoders 20 to 24 output
The states of Q ₁ to Q ₅ are decoded, and the decoded outputs T ₀ to _{T 4} are set to “H” for each set specific combination of states of Q ₁ to _{Q 5} . The output _T0 resets the shift counter 1, and _T1 to _T4 are connected to an external circuit to control it. The above operation is the same as that of the conventional circuit.

At the time of an external individual test, the switching control signal Test is set to "H" to cause the switching gate 3 to select data input from the test setting data input terminal 4. In this state, the setting data of flip-flops 11 to 15 are input from the test setting data input terminal 4 in synchronization with the clock φ, and the output Q ₁
~ Set _Q5 . Here, if a combination of outputs Q ₁ to Q ₅ is set such that the decode output T 1 _becomes “H”, the decode output T ₁ becomes “H _” , and the external The circuit works. In this way, the decode outputs T ₁ to _{T 4} are sequentially set to "H", and each of the external circuits controlled by each signal is individually tested to see if they are operating normally.

In the above embodiment, a method of testing the external circuits individually was explained, but for example, after setting the outputs Q ₁ to _{Q 5} using the method described above, the switching control signal
Since the shift counter 1 can be started from this set value by setting Test to "L", it can also be used for initial setting of the shift counter 1.

Furthermore, in the above embodiment, the reset input terminal 7 for forced reset from the outside, the OR gate 8, and the AND gate 5 for prohibiting reset during testing are connected; If you don't have them, you don't need to install them.

Furthermore, if a terminal is connected to the output of the final stage flip-flop (Q ₅ in the above example) and this output can be measured, the switching control signal Test
By setting ``H'' to "H" and checking whether the data input from the test setting data input terminal 4 is output with a delay of a specified number of clocks from the terminal connected to the output of this final stage flip-flop. The flip-flop itself can be tested.

〔Effect of the invention〕

As described above, according to the present invention, the states of the plurality of flip-flops constituting the shift counter can be arbitrarily set by data input from the external input terminal, so that the external This allows you to test each circuit individually.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a test circuit having a shift counter configuration according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional test circuit having a shift counter configuration. 1 is a shift counter, 2 is a decoder block,
3 is a switching gate, 4 is a test setting data input terminal, 5 is an AND gate, 7 is a reset input terminal,
8 is an OR gate, 11 to 15 are flip-flops, 16 is a feedback exclusive OR gate, 20 to 2
4 is a decoder, Q ₁ to Q ₅ are flip-flops 11
~15 output signals, _T0 ~ _T4 are decoders 20~2
4 is the decoded output, Test is a switching control signal, and φ is a clock signal. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. It has a shift register in which a plurality of flip-flops are connected in series, and a logic gate that takes the exclusive OR or inversion of some of the outputs of these flip-flops, and the output of this logic gate is sent to the shift register. A test circuit that includes a shift counter having a circuit configuration that is input to the input terminal of the first stage flip-flop, and a decoder that decodes the state of the shift register, and tests an external circuit that operates at the timing decoded by the decoder. A switching circuit is provided between the output terminal of the gate and the input terminal of the flip-flop in the first stage of the shift register, which selects and outputs either the output of the logic gate or the input data input from the outside by a switching control signal. The output of the logic gate is controlled by the switching control signal during normal testing in a predetermined order.
A test circuit characterized in that each of the input data inputted from the outside is selected when performing an individual test from the outside.