JPH0469928U - - Google Patents
Info
- Publication number
- JPH0469928U JPH0469928U JP11289290U JP11289290U JPH0469928U JP H0469928 U JPH0469928 U JP H0469928U JP 11289290 U JP11289290 U JP 11289290U JP 11289290 U JP11289290 U JP 11289290U JP H0469928 U JPH0469928 U JP H0469928U
- Authority
- JP
- Japan
- Prior art keywords
- logic level
- processing
- switches
- circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案による冗長系スイツチ回路の一
例を示すブロツク図、第２図は従来の冗長系スイ
ツチ回路の一例を示すブロツク図である。
１０９……論理和回路、１１０……２進計数回
路、１１１……論理回路、１１８……論理積回路
、１１４，１１５……処理回路、１１６，１１７
……監視回路、２０１，２０２……押しボタンス
イツチ、２０３，２０４……ＲＳフリツプフロツ
プ回路、２０５〜２０８……抵抗。
FIG. 1 is a block diagram showing an example of a redundant switch circuit according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional redundant switch circuit. 109...Order circuit, 110...Binary counting circuit, 111...Logic circuit, 118...Andor circuit, 114, 115...Processing circuit, 116, 117
... Monitoring circuit, 201, 202 ... Push button switch, 203, 204 ... RS flip-flop circuit, 205 to 208 ... Resistor.
Claims (1)
作結果にもとづいて第１の論理レベルの制御信号
が入力されたとき所定の処理を行う第１の処理回
路と、前記２つのスイツチの操作結果にもとづい
て第２の論理レベルの前記制御信号が入力された
とき所定の処理を行う第２の処理回路とを備えた
冗長系スイツチ回路において、 前記２つのスイツチが操作されるごとに出力信
号の論理レベルを切り替える計数手段と、 前記第１および第２の処理回路が前記所定の処
理を実行していないとき所定の論理レベルの信号
を出力する監視手段と、 この監視手段が前記所定の論理レベルの信号を
出力しているとき、前記計数手段の前記出力信号
を前記制御信号として前記第１および第２の処理
回路に与える論理回路とを備えたことを特徴とす
る冗長系スイツチ回路。[Claims for Utility Model Registration] Two switches, a first processing circuit that performs predetermined processing when a control signal of a first logic level is input based on the operation results of these two switches; and a second processing circuit that performs predetermined processing when the control signal of a second logic level is input based on the operation results of the two switches, in which the two switches are operated. counting means for switching the logic level of the output signal every time; monitoring means for outputting a signal at a predetermined logic level when the first and second processing circuits are not executing the predetermined processing; a logic circuit that supplies the output signal of the counting means to the first and second processing circuits as the control signal when outputting the signal at the predetermined logic level. switch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11289290U JPH0469928U (en) | 1990-10-26 | 1990-10-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11289290U JPH0469928U (en) | 1990-10-26 | 1990-10-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0469928U true JPH0469928U (en) | 1992-06-22 |
Family
ID=31860419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11289290U Pending JPH0469928U (en) | 1990-10-26 | 1990-10-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0469928U (en) |
-
1990
- 1990-10-26 JP JP11289290U patent/JPH0469928U/ja active Pending
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