JPH0469821U - - Google Patents
Info
- Publication number
- JPH0469821U JPH0469821U JP11374590U JP11374590U JPH0469821U JP H0469821 U JPH0469821 U JP H0469821U JP 11374590 U JP11374590 U JP 11374590U JP 11374590 U JP11374590 U JP 11374590U JP H0469821 U JPH0469821 U JP H0469821U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- generated
- counter circuit
- outputs
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Electric Clocks (AREA)
- Electromechanical Clocks (AREA)
- Keying Circuit Devices (AREA)
Description
第１図は本考案の一実施例に係るスイツチ機構
を用いた時計の回路構成図、第２図及び第３図は
タイムチヤートである。
１０……外部操作部材、１６……第１カウンタ
回路、２８……第２カウンタ回路、４０……モー
ド切替回路、４６……ゲート回路。
FIG. 1 is a circuit diagram of a timepiece using a switch mechanism according to an embodiment of the present invention, and FIGS. 2 and 3 are time charts. DESCRIPTION OF SYMBOLS 10... External operation member, 16... First counter circuit, 28... Second counter circuit, 40... Mode switching circuit, 46... Gate circuit.
Claims (1)
後に第１信号を出力する第１カウンタ回路と、 前記第１信号発生時にのみ前記操作信号を入力
して前記第１カウンタ回路より短く設定された所
定時間後に第２信号を出力する第２カウンタ回路
と、 前記第２信号発生までは前記操作信号に応答し
て出力を可変するモード切替回路と、 前記第２信号発生時から前記第１信号発生時ま
で前記操作信号を有効とするゲート回路と、 を設けたことを特徴とするスイツチ機構。[Claims for Utility Model Registration] An external operating member; a first counter circuit that outputs a first signal after a predetermined time in response to an operating signal from the external operating member; and a first counter circuit that outputs the operating signal only when the first signal is generated. a second counter circuit that outputs a second signal after a predetermined time set shorter than that of the first counter circuit; and a mode switching circuit that varies the output in response to the operation signal until the second signal is generated. A switch mechanism comprising: a gate circuit that makes the operation signal valid from the time when the second signal is generated until the time when the first signal is generated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11374590U JPH0642233Y2 (en) | 1990-10-30 | 1990-10-30 | Clock correction mechanism |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11374590U JPH0642233Y2 (en) | 1990-10-30 | 1990-10-30 | Clock correction mechanism |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0469821U true JPH0469821U (en) | 1992-06-19 |
| JPH0642233Y2 JPH0642233Y2 (en) | 1994-11-02 |
Family
ID=31861353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11374590U Expired - Lifetime JPH0642233Y2 (en) | 1990-10-30 | 1990-10-30 | Clock correction mechanism |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0642233Y2 (en) |
-
1990
- 1990-10-30 JP JP11374590U patent/JPH0642233Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0642233Y2 (en) | 1994-11-02 |