JPH0468885A - Time base corrector - Google Patents

Abstract

PURPOSE:To prevent circuit scale from being enlarged and to reduce cost by executing the write of a memory at the timing of a single reference clock and excluding time base fluctuation within one cycle of the reference clock after excluding time base fluctuation for the unit of the cycle of the reference clock. CONSTITUTION:Sample data are written in memories 30 and 31 at the timing of a reference clock phis. A time base error detection circuit 34 detects the fluctu ated component of time base and generates first and second error signals ER1 and ER2. Next, a read timing generation circuit 35 generates a read control signal SR and a control signal Sc. In this case, the read control signal SR shifts the read timing of the sample data from the memories 30 and 31 only for time with the cycle of the reference clock phis as the unit corresponding to the first error signal ER1. Next, corresponding to the control signal Sc, interpolation filters 36 and 37 select either the sample data or an interpolation data and output it for each cycle of the sample data (cycle Ts of the reference clock phis).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time axis correction device suitable for use in home VTRs (video tape recorders) and the like.

[Prior Art] In a VTR, fluctuations in the time axis occur in reproduced video signals due to uneven rotation of the head cylinder. In VTRs used in broadcasting stations, etc., in order to correct such time axis fluctuations, time axis correction devices (hereinafter referred to as T B
Time Ba5e Corrector (C) is used.

Generally, TBC is mainly A/
D (analog/digital) converter 1, memory 2, D
/A (digital/analog) converter 3, write clock generator 4, and read clock generator 5. The input video signal A having a time axis fluctuation component is an A/D
Converter 1 converts it into digital video signal B, and memory 2
will be written to. Further, the input video signal A is supplied to a write clock generator 4, and a write clock E is generated. Using this write clock E as a sampling clock, the input video signal A is converted into a digital video signal B in the A/D converter 1, and the digital video signal B is written into the memory 2 using this write clock E as a reference. The digital video signal B written in the memory 2 is read based on the read clock F generated by the read clock generator 5. The read digital video signal C is converted into an analog video signal by a D/A converter 3 using a read clock F.

Here, if the write clock E has the same time axis fluctuation as the input video signal A, this write clock E is used as the sampling pulse of the A/D converter 1.
The same time axis fluctuation component exists in the digital video signal B, and since the digital video signal B is written into the memory 2 using this write clock E as a reference, the digital video signal introduced into the memory 2 There is no time axis fluctuation component. Therefore, if the digital video signal stored in the memory 2 is read out using the readout clock F having a stable frequency, the read out digital video signal C will have no time axis fluctuation component.

The above is the general principle of TBC used in broadcasting VTRs. For details, see, for example, "rVTR Technology" published by Japan Broadcasting Publishing Association, 1981, pp. 1
07-134, etc.

By the way, the conventional TBCffi time axis correction ability depends on how accurately the write clock E follows the time axis fluctuations of the input video signal A. As an example of write clock generation @4 taking this point into consideration, p L
An L (Phase Locked, Loop) configuration is known. FIG. 18 is a block diagram showing such a write clock generator 4.

In the figure, an input video signal A is supplied to a synchronization separation circuit 6, and a horizontal synchronization signal HD is separated.

Now, if the frequency of this horizontal synchronization signal HD is f8, then the VCO (voltage controlled oscillator) 9 is nf, (where n>1
) generates a write clock E with a frequency of This write clock E is frequency-divided by an n frequency divider 1o to become a signal with a frequency of f9, and a horizontal synchronizing signal HD is generated by a phase comparator circuit 7.
An error signal G is formed by comparing the phase with This error signal G has high frequency components removed by an LPF (low pass filter) 8 and is supplied to a VCO 9. VCO9 is this LPF
8, which changes the frequency of the write clock E.

Here, phase comparator circuit 7. LPF8. VCO9 and n
The frequency divider 110 constitutes a PLL, and the horizontal synchronization signal HD
When the phases of the output signal ■ of the n frequency divider 10 match, V
By designing the oscillation frequency of the CO9 to be nf8 and appropriately setting the constant of the LPF8, it is possible to maintain the oscillation frequency of the VCO9 in a locked state where it is always n times the frequency f□ of the horizontal synchronizing signal HD. can, therefore,
It is possible to obtain a write clock E that follows the time axis fluctuations of the input video signal A.

In such a write clock generator 4, the LPF 8 is essential for stably operating the PLL.

However, on the other hand, since the LPF 8 causes a phase delay in the signal, the write clock generator 4 has a problem in that its follow-up characteristics are not very good. In other words, it follows well the low frequency fluctuations of the time axis fluctuations included in the input video signal A, but cannot follow the high frequency fluctuations.

Therefore, various methods of generating a write clock with good follow-up characteristics have been studied, and an example is given in "Technical Report of the Television Society of Japan, J VoQ, 13°No, 38.
(August 1989) pp. L7-22. This method will be explained below with reference to FIG.

In the figure, the reference oscillator 14 generates a reference clock fll having a frequency of nf8, and this reference clock fs
is supplied to the phase delay circuit 13 and the frequency is nfn and Δτ
m subclocks fulfi+ with different phases in sequence
..., f, is generated.

However, Δτ is nf and Xm.

The horizontal synchronization signal HD separated from the input video signal A by the synchronization separation circuit 6 is supplied to a phase comparator circuit 11, where the phase is compared with each of the subclocks f to f.

Then, the phase comparison circuit 11 detects the subclock having the smallest phase difference from the horizontal synchronization signal HD among the subclocks mos to f, and controls the clock selection circuit 12 to detect the subclock having the smallest phase difference from the horizontal synchronization signal HD. A smaller subclock is selected as the write clock E. This operation is performed every time the horizontal synchronizing signal HD is supplied to the phase comparator circuit 11.

According to this write clock generation method, input video signal A
The response of the write clock instantaneously responds to fluctuations in the time axis, and can sufficiently follow fluctuations in the high frequency time axis.

However, in this way, T
BC (hereinafter referred to as an instantaneous response TBC) has a problem that does not exist in a TBC (hereinafter referred to as a PLL type TBC) equipped with a PLL write clock generation circuit 4 shown in FIG. 7. This is because the input video signal Al7) If the S/N is poor, the high frequency time axis fluctuation of the video signal output from the TBC increases compared to the input video signal A.

That is, if the S/N of the input video signal A is poor, the write clock generation circuit 4 shown in FIG.

The time axis precision of the horizontal synchronization signal HD output from the synchronization separation circuit 6 deteriorates, and the phase comparison circuit 11 ends up responding to the horizontal synchronization signal HD with poor precision.

For this reason, the write clock E outputted from the clock selection circuit 12 is affected by the time axis fluctuation of the input video signal A.
This also includes erroneous time axis fluctuations due to noise. For this reason, erroneous time axis fluctuations due to noise appear in the video signal output from the instantaneous response TBC.

Of course, even in the PLL type TBC, time axis fluctuations due to noise appear in the output video signal.

However, since the PLL type TBC does not respond to high frequency time axis fluctuations, it can be affected by noise.

Only low frequency time axis fluctuations appear. For this reason,
The time axis fluctuation of the output video signal caused by noise is P
The LL type TBC is smaller than the instantaneous response type TBC.

As one method for compensating for the shortcomings of such an instantaneous response type TBC, the above-mentioned document "Television Society Technical Report" describes a method for accurately separating only the horizontal synchronization signal HD from the input video signal A as a synchronization separation circuit 6. A so-called adaptive sync separation circuit is used. This will be explained below using FIG. 20.

In the figure, an input video signal A is delayed by an IH delay circuit 15 (where IH is one horizontal scanning period), and a 1-H delayed video signal A' is obtained. This IH delayed video signal A' is further delayed by an IH delay circuit 16 to obtain a 2H delayed video signal A'. These input video signal A and delayed video signals A', A'' are supplied to a 3-line cosine filter 17. The 3-line cosine filter 17 averages these input signals A, A'A Tl, 4
Attenuates noise in the frequency band of /4 or higher.

The output video signal of the 3-line cosine filter 17 is LP
Color subcarrier, synchronization signal overshoot, ringing, etc. with F18, #! After two decays, the signal is supplied to the comparator circuit 19. In the comparator circuit 19, the synchronization tip potential and pedestal potential of the supplied video signal are sampled and held, their intermediate potential is detected as a threshold kick, and this threshold potential is compared to the supplied video signal and level. By comparison, the composite synchronization signal of this video signal is separated. This composite synchronization signal is supplied to the AFC gate circuit 20. In the AFC gate circuit 20, a window pulse is formed from the composite synchronization signal by an AFC (automatic frequency control) circuit. A gate is placed around Edge. As a result, noise, equalization pulses, and vertical synchronization signals in a period centered on the trailing edge are removed, and a horizontal synchronization signal is obtained. This horizontal synchronization signal is supplied to the noise gate circuit 21, and A, F
Among the output signals of the C gate circuit 20, the horizontal synchronization signal
It also removes pulses with a narrow duration as noise. The horizontal synchronization signal output from the noise gate circuit 21 is supplied to a dummy sync insertion circuit 22, and when the horizontal synchronization signal is not supplied at a regular cycle, a dummy horizontal synchronization signal is inserted.

In this way, the horizontal synchronization signal HD with sufficiently attenuated noise is obtained from the dummy sync insertion circuit 22 as the output of the synchronization separation circuit 6.

Note that the IH delayed video signal A' output from the IH delay circuit 1.5 is converted into a digital video signal B by the A/D converter 1, and is supplied to the memory 2 (FIG. 17).

By the way, in FIG. 20, LPF18. As mentioned above, the comparator circuit 19 is effective for improving the timing accuracy of the synchronization signal, and is often used in TBCs for boat fishing. Further, the AFC gate circuit 20. The noise gate circuit 21 and the dummy sink insertion circuit 22 are effective in preventing malfunctions caused by noise, and are often used in TBCs for boat fishing.

The synchronous separation circuit shown in FIG.
This means that it uses Generally, noise has no correlation between lines, so when the three-line cosine filter 17 equalizes the video signal three lines at a time, the noise is attenuated and the S/N is improved. This process is L in the frequency domain.
This produces an effect as a PF, and in the above-mentioned conventional technology, frequency components of frequency fM/4 or higher are attenuated. For the second reason, the frequency components of f8/4 or higher in the time axis fluctuations are also attenuated, but in home VTRs, the time axis fluctuations included in the reproduced video signal are mostly low frequency components, so this Even if high-frequency components are attenuated, performance degradation is small.

Another important point of the synchronization separation circuit 6 shown in FIG. 20 is that the video signal to be time-base corrected is the IH delayed video signal A' output from the IH delay circuit 15. This is because the output signal of the 3-line cosine filter 17 lags behind the input video signal A by IH, and as a result, the sync separation circuit 6
This is because the horizontal synchronizing signal HD output from the input video signal A is delayed by 1H from the input video signal A. Therefore, the detection of time axis fluctuations from this horizontal synchronization signal HD is delayed by IH than input video signal A, but since the digital video signal B, which is subject to time axis correction, is also delayed by IH than input video signal A, the timing of both is As a result, the time base correction is performed in response to 5 instants.

[Problems to be Solved by the Invention] As described above, in an instantaneous response TBC using the adaptive synchronization separation circuit shown in FIG. 20 as the synchronization separation circuit 6 of the write clock generation circuit 4 shown in FIG. is low S/N
Even for the input video and signal, the time axis variation can be corrected by responding instantaneously to the time axis variation without being affected by noise, but the following problem occurs.

First, as shown in FIG. 20, the video signal to be time-axis corrected is delayed by the IH delay circuit 15, and the S/N and frequency characteristics of the video signal are There is a risk of deterioration.

That is, as a 1H delay circuit, CCD (
Charge coupled devices (Coupled Devices) and semiconductor memories are used.Whichever is used, the video signal is sampled using a reference clock, supplied to a CCD or semiconductor memory, and output after a certain number of clocks to create the original continuous video. By returning it to a signal, the video signal is delayed. By the way, when sampling a video signal, a pre-filter is required to prevent aliasing noise.

An interpolation filter is required to convert the sampled video signal into a continuous video signal, but these prefilters and interpolation filters have a response of 1. If the video signal does not have ideal characteristics that result in a response of O outside the band, the S/
N deteriorates.

Furthermore, with currently available CCDs, it is often not possible to obtain a sufficient S/N ratio. In the case of semiconductor memory, it is necessary to quantize the video signal, and quantization noise becomes a problem.

As described above, when an adaptive synchronization separation circuit is used, there is a risk that the S/N and frequency characteristics of the video signal subjected to time axis correction processing may deteriorate.

Second, the performance of the write clock generation circuit 4 shown in FIG. 19 is easily affected by variations in circuit characteristics, temperature changes, and the like.

In other words, phase lag times w! r13 is set by the delay means,
Zero subclocks with a phase difference of Δ are formed from the reference clock f8, but if there are variations in the delay amount of this delay means or the delay amount fluctuates due to temperature changes, the phase difference between the subclocks will change. Δ is different from the normal value and varies. When the number of sub-clocks is small and the phase difference Δτ is set large, the variation in one phase difference Δτ becomes large. The clock delay circuit 12 receives the horizontal synchronization signal I based on the comparison result of the phase comparison circuit 11.
(Write the subclock whose phase is closest to D.
However, if there is a large variation in the phase difference Δτ, the time axis variation due to this will also occur in the write clock E, and the video signal output from the D/A converter 3 (Fig. 17) will be affected. The time axis fluctuation will remain.

In order to prevent this, the number of sub-clocks is increased and the phase difference Δτ between them is defined to be small.
Although it is possible to reduce the amount of delay of the delay means, the scale of the circuits such as the phase comparison circuit 11 and the clock delay circuit 12 increases accordingly, resulting in an increase in cost.

The purpose of the present invention is to eliminate such interlayer points and suppress the deterioration of the S/N and frequency characteristics of the video signal while maintaining the same level of time axis fluctuation correction ability as the conventional instantaneous response TBC or more. It is an object of the present invention to provide a time axis correction device that prevents an increase in circuit scale and is advantageous in terms of cost.

[Means for Solving the Problems] In order to achieve the above object, the present invention includes a reference tally clock generation means for generating a single reference clock, a synchronization separation means for separating a horizontal synchronization signal of the video signal, and a synchronization separation means for separating a horizontal synchronization signal of the video signal. The start timing of each horizontal scanning period of the video signal is set based on the horizontal synchronization signal separated by the synchronization separation means, and the video signal is synchronized with the reference clock from the start timing for each horizontal scanning period. A write timing generating means for writing to the memory, a time error signal for detecting the time axis fluctuation of the video signal, and representing the time axis fluctuation in units of the period of the reference clock and a time within one cycle of the reference clock. time axis error detection means for generating a second error signal representing axis fluctuation; and reading the video signal written from the memory in synchronization with the reference clock.

readout timing generating means for setting readout start timing from the memory based on the first error signal every horizontal scanning period of the video signal; 1 of the reference clock according to the error r signal
and an interpolation filter that shifts the time axis at the first position within the period.

[Effects] The time axis fluctuation of the video signal is corrected for each horizontal scanning period, but the start timing of each horizontal scanning period when writing to memory is temporarily set based on the horizontal synchronization signal separated from the video signal. be done. Memory writing is performed at the timing of a single reference clock, and since this reference clock does not include the time @ fluctuation of the video signal, the start timing of each horizontal scanning period differs depending on the amount of time axis fluctuation. 5. Each horizontal scanning period written in the memory includes time axis fluctuations.3 The read timing generating means determines the read start timing for each horizontal scanning period from the memory in accordance with the first error signal. is shifted in time by an integral multiple of the period of the reference clock. This eliminates time axis fluctuations in units of periods of the reference clock.

Also, the interpolation filter creates interpolated data within the period of the reference clock like a digital filter, but instead of the data read from the memory in response to the second error signal, it outputs it at the timing of the reference clock. . As a result, a time axis shift within one cycle of the reference clock is performed, and time axis fluctuations within one cycle of the reference clock are removed.

[Example code] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the time axis correction device according to the present invention, in which 23 and 24 are input terminals, 25 is a color decoder, 26 is a multiplexer, 27 is a frequency dividing circuit, and 28.29 is an A /D converter, 30.31 is memory, 3
2 is a synchronization separation circuit, 33 is a write timing generation circuit,
34 is a time axis error detection circuit, 35 is a read timing generation circuit, 36.37 is an interpolation filter, 38 is a synchronization signal addition circuit, 39 is a burst signal addition circuit, 40 to 42 are D/A converters, 43 44 is a reference clock generation circuit, and 45 and 46 are output terminals.

In the figure, a reference clock generation circuit 44 uses a crystal oscillator or the like and outputs a stable reference clock φ8 having a constant period. The baseband input luminance signal Y from the input terminal 23 is supplied to the A/D converter 28, which converts the digital luminance signal Y using the reference clock φ8 as a sampling pulse.
D and is supplied to the memory 30. Further, the chroma signal C from the input terminal 24 is demodulated by the color decoder 25 into two baseband color difference signals. These color difference signals are supplied to the multiplexer 26, and are alternately selected by a select signal obtained by frequency dividing the reference clock φ8 by the frequency divider circuit 27 to produce a time-division multiplexed signal (hereinafter referred to as
This is simply called a color signal). This color signal is supplied to two A/D converters, and is converted into a digital color signal CaO by a sampling pulse obtained by frequency-dividing the reference clock φ9 by a frequency dividing circuit 27, and is supplied to the memory 31.

On the other hand, the input luminance signal Y is supplied to the sync separation circuit 32,
Horizontal synchronization signal HD is separated. This horizontal synchronization signal HD
and the reference clock φ5 are the write timing generation circuit 33.
A write control signal S, . . . is generated, and the write control signal S, .

Here, the synchronization separation circuit 32 does not use a delay circuit as shown in FIG. 20, but a normal one.

Here, the operation of the write timing generation circuit 33 will be explained with reference to FIG.

When the horizontal synchronization signal HD separated from the input luminance signal Y as a H''' (high level) pulse is supplied to the synchronization separation circuit 32, the rising edge of the horizontal synchronization signal HD is detected and a reset pulse RP is formed. Reset the internal counter. When the reset is released, the second internal counter counts the reference clock φ8, and uses the count value to calculate the brightness information and color information of the horizontal synchronization signal in the digital brightness signal YD and digital color signal CBD. A valid period that includes the existing period and is slightly wider than this is set, and within this valid period, the write control signal S is sequentially transmitted at the timing of the reference clock φ8.
1 to memory 30.31. As a result, the sample data of the digital luminance signal YD and the digital color signal CaO are written to successive addresses in the memories 30 and 31, respectively.

According to this, the writing timing of the first address written in the memory 30.degree. 31 in each horizontal scanning period is determined by the timing of the rising edge of the horizontal synchronization signal HD separated by the synchronization separation circuit 32.

Further, the horizontal synchronization signal H output from the synchronization separation circuit 32
D and the digital luminance signal Yo output from the A/D converter 28 are supplied to the time axis error detection circuit 34, and using the reference clock φ8, the time axis fluctuation is detected from these horizontal synchronizing signal HD and digital luminance signal YD. The first minute is detected.
error signal ER.

and a second error signal ER2 are generated. As will be described later, the first error signal ER1 includes a time axis variation in units of cycles of the reference clock φ8, and the second error signal ER, includes a time axis variation within one cycle of the reference clock φ6. Contains.

Read timing generation circuit 35 generates read control signal SR and control signal Sc. The digital luminance signal Yo is read out from the memory 30 and the digital color signal Cao is read out from the memory 31 according to the readout control signal S2.
The timing of generation of R changes according to the first error signal ER by a time unit of the cycle of the reference clock φ8 (a time that is an integral multiple of this cycle), and for this reason, the memory 30°3
1, the read timing of the first address in each horizontal scanning period is determined by the reference clock φ, according to the first error signal ER□.
5 where the write control signal S
Write and read control signal S of memory 30°31 by
2 will now be described.

For example, in the case of the NTSC system, the frequency of the reference clock φ8 outputted from the reference clock generation circuit 44 is 4fs.
c (however, fs+c is the color subcarrier frequency, 455
/2×f□), which is an integer multiple of the normal horizontal synchronization frequency f,I.

Therefore, the sample data first written in the memories 30 and 31 during three horizontal scanning periods having different amounts of time-axis variation are shown in FIG. 3. However, in the same figure, a shows the case where there is no time axis variation, b shows the case where the time axis shrinks due to time axis variation, and C shows the case where the time axis expands due to time axis variation. Therefore, the relationship with the reference clock φ8 is exaggerated, and the front edges of the horizontal synchronizing signal HD in each horizontal scanning period a, b, and c are shown in phase with the reference clock φ8.

The O marks shown in each horizontal scanning period a, b, and c are memory 30.3.
This is the sample data that is first written to 1. Since the period of the reference clock φ8 is constant, sample data far from the horizontal synchronization signal HD is stored in the memory 30°31 during the horizontal scanning period in which the time axis is reduced compared to the horizontal scanning period a where there is no time axis variation. In the horizontal scanning period C in which data is written first and the time axis is expanded by one time, sample data close to the horizontal synchronization signal HD is written into the memory 30.31 first. In this way, sample data at different timings from the horizontal synchronization signal is stored in the memory 30 depending on the amount of time axis fluctuation.
．． 31 will be written first.

The read control signal S, ! is generated using the first error signal ER, output from the time axis error detection circuit 34. teeth,
The readout timing of sample data in each horizontal scanning period from the memory 30.31 is shifted by a period of the reference clock φ3 in response to the first error signal ERt detected by the time axis error detection circuit 34. Ru. That is,
In the third @, the horizontal synchronizing signal HD in the horizontal scanning period a
In the horizontal scanning period C, the timing of reading the first sample data with respect to the horizontal synchronizing signal HD is delayed by an integral multiple of the period of the reference clock φ5, and in the horizontal scanning period C, the timing of reading the first sample data with respect to the horizontal synchronizing signal HD is delayed by , the clock is advanced by an integral multiple of the period of the reference clock φ9. In this way, the timing relationship of each sample data with respect to the horizontal synchronization signal HD is aligned in each horizontal scanning period.

Note that the read timing generation circuit 35 is set to the reference clock φ.
1 is divided to generate a timing signal S for a composite synchronization signal and a timing signal BT for a color burst signal. The read timing of the memories 30 and 31 by the above read control signal S9 is set using these timing signals S and BT as a time reference.

Further, depending on the amount of deviation of each horizontal scanning period with respect to the reference clock φ5, sample data having different timing with respect to the horizontal synchronization signal becomes the sample data written first in the memory 30.31. 29 will be explained using Figure 4.

In the same figure, in order to simplify the explanation, each horizontal scanning period a to d is set to the same time axis, and the horizontal scanning period a
Then, the front edge of the horizontal synchronizing signal HD has the same phase as the reference clock φ, and the horizontal scanning period begins.

It is assumed that the front edge of the horizontal synchronizing signal HD is shifted from the reference clock φ8 by I74 of the period T8 in the order of c and d. Further, the O mark indicates sample data written first to the memory 30, 31.

Comparing such horizontal scanning periods, it depends on the amount of deviation of the horizontal synchronizing signal HD from the reference clock φ8.

The timing of the sample data first written to the memories 30 and 31 using the horizontal synchronization signal HD as a time reference is different. That is, the memory 30.3 is first read during the horizontal scanning period a.
If the sample data written in 1 is sample data with a timing of 8 Ts from the previous edge of the horizontal synchronization signal HD, then in the horizontal scanning period, the timing is (8Ts l / 4 TG) with the horizontal synchronization signal HD as the time reference. sample data is (8T) in the horizontal scanning period C.
The sample data at the timing of s 2 / 4 Ts) is (8Ts 3 / 4 Ts) in the horizontal scanning period d.
, l) are stored in the memory 30, respectively.
．． 31 is the sample data written first.

The timing signal ST output from the read timing generation circuit 35 is obtained by frequency-dividing the reference clock φ5.
A composite synchronization signal having a constant phase relationship with the reference clock φ8 is added to the digital luminance signal read from o, and as shown in FIG. 4, it is first written into the memory 30 for each horizontal scanning period. If the sample data differs in timing from the horizontal synchronization signal HD, this timing variation will cause 5 time axis variations.

In other words, even if the digital luminance signal YD is read out from the memory 30 by correcting the time axis fluctuation as explained in FIG. Period T
5, and cannot correct the time axis fluctuation within one period of the reference clock φ9 explained in FIG. 4.

To explain further, the time axis fluctuation is continuous, and due to this time axis fluctuation, the digital luminance signal YD is written in the memory 30 in a composite state of the state shown in FIG. 3 and the state shown in FIG. .

When the digital luminance signal YD is read out from the memory 30 by the readout control signal SR, time axis fluctuations in units of period Ty of the reference clock φS are removed, but time axis fluctuations within this period 18 are not removed and remain. I will do it.

The same applies to the digital color signal CBO read out from the memory 31, and the time axis fluctuation within the i period T5 remains without being removed.

Memory 30 as described above. :Digital luminance signal YD' + digital color signal CBD read from H
Interpolation filters 36 and 37 are provided in order to remove time axis fluctuations within one period T9 of the reference clock φ9 that remain in the period T9.

That is, the read timing generation circuit 35 uses the second error signal ER2 from the one time axis error detection circuit 34 to generate a control signal SC corresponding to the time axis variation within one cycle Tg of the reference clock φ8. The interpolation filters 36 and 37 are
As will be described later, a predetermined number of interpolated data between the sample data are created from the sample data output from the memories 30 and 31, and the period of the sample data (this is equal to the period T1 of the reference clock φ5) is determined according to the control signal Sc. Each time, either sample data or interpolated data is selected and output. In other words, for example, if sample data output from the memory 30 has a time axis fluctuation that is 18 cycles ahead of the reference clock φ6, the interpolation filter 36 is used instead of this sample data with a time axis that is 18 Ts behind this. Outputs interpolated data. As a result, this 1
The time axis fluctuation of T9 minutes is removed. Therefore, the sample data output from the interpolation filters 36 and 37 is synchronized with the reference clock φ8.

The digital luminance signal outputted from the interpolation filter 36 is added with a digital composite synchronization signal by the timing signal S in the synchronization signal addition circuit 38, and then supplied to the D/A converter 40, where it is converted using the reference clock φ8. , is converted into an analog luminance signal Y', and is output from the output terminal 45. Further, the digital color signal outputted from the interpolation filter 37 is added with a digital color burst signal by the timing signal BT in the burst signal adding circuit 39, and then supplied to the D/A converters 41 and 42, and then added to the digital color signal by the frequency dividing circuit 2.
A clock obtained by frequency-dividing the reference clock φyo by 7 is converted into two baseband color difference signals. These color difference signals are supplied to a color encoder 43, and a chroma signal C' is generated and output from an output terminal 46.

As described above, in this embodiment, time axis fluctuations in the input luminance signal Y and the input chroma signal C are removed, but the sync separation circuit 32 uses a normal sync separation circuit that does not require an IH delay circuit. Therefore, the luminance signal Y written in the memory 30 and the black signal C written in the memory 31 do not need to be delayed by the IH delay circuit, and there is no deterioration in the S/N or frequency characteristics of these signals.

Further, a series of operations such as writing and reading of the memory 30 and 31 are performed using a plurality of sub-clocks f to f as shown in FIG.
A stable single reference clock φ, not due to f,
It will be held after 5pm. For this reason, as in the case of using the write clock generation circuit 4 shown in FIG.
．． This does not occur in the digital signal read out from 31.

Next, specific examples of each part shown in FIG. 1 will be explained.

FIG. 5 is a block diagram showing a specific example of the time axis error detection circuit 34 in FIG. 1, in which 45 is a previous edge detection circuit, 46 is a counter, 47 is a threshold level generation circuit, and 48 is a level comparison circuit. , 49 is a minute error detection circuit.

In the same figure, the digital @degree signal YD from the A/D converter 28 is supplied to a threshold level generation circuit 47, the synchronization tip potential and the pedestal potential are detected, and the threshold level of the intermediate potential is determined. E8 is generated. The level comparison circuit 48 receives the digital luminance signal Y. A narrow trailing edge pulse BEP is generated at a timing equal to the threshold level Es at the trailing edge of the horizontal synchronizing signal in the digital luminance signal Yo.

On the other hand, the horizontal synchronization signal HD output from the synchronization separation circuit 32 (FIG. 1) is supplied to the previous edge detection circuit 45, and a reset pulse is generated at the timing of the previous edge.

This reset pulse resets the counter 46. Further, when the reset is released, the counter 46 counts the reference clock φ from the reference clock generation circuit 44 (FIG. 1), and temporarily stops counting at the trailing edge pulse BEP from the level comparison circuit 48. Data with a value 1 smaller than the current count value is output as the first error signal ER1.

Therefore, the first error signal ER1 is a reference from immediately after the front edge of the horizontal synchronization signal HD to immediately before the rear edge of the horizontal synchronization signal of the input luminance signal Y that follows (the point at which it matches the threshold level E8). It has a value equal to the number of clocks φ8.

Since the time width of the horizontal synchronization signal also changes due to the time axis fluctuation, the value of the first error signal ER1 also changes according to the time axis fluctuation. If the value of the first error signal ER□ with respect to the time width of the horizontal synchronization signal when there is no time axis variation is taken as the reference value,
The difference between the value of the first error signal ER obtained from the counter 46 and this reference value is the reference clock φ in the horizontal scanning period.
5 represents the time axis fluctuation in units of period T8.

Rear edge pulse BEP and threshold level E8
is also supplied to the minute error detection circuit 49 together with the digital luminance signal YD from the A/D converter 28, from which a second error signal ER, representing a time axis variation within one period Ts of the reference clock φ8, is output. The configuration and operation of this minute error detection circuit 49 will be explained with reference to FIGS. 6 and 7. However, in FIG. 6, 50 is a data holding circuit, 51 is an interpolation circuit, 52 to 54 are level comparison circuits, and 55 is an encoder. Of which, rear edge pulse B
Sample data immediately before EP (hereinafter referred to as "immediate sample data") and sample data immediately after the second edge pulse BEP (hereinafter referred to as "immediate sample data") are held, and these sample data are supplied to the interpolation circuit 51. The interpolation circuit 51 calculates three intermediate levels y0 . v2゜■
, generates.

Here, if the digital luminance signal YD is obtained by digitizing the input luminance signal Y including the negative polarity synchronization signal shown in FIG. 2, the rising and falling edges of the horizontal synchronization signal of this input luminance signal Y are inclined. Therefore, the data holding circuit 5
The sample data held as 0 is the value of the immediately preceding sample data (the immediately preceding sample data). Therefore, assuming that the value of the immediately preceding sample data is VF and the value of the immediately following sample data is v8, and the intermediate levels V<V and <V3, these intermediate levels v1 to V are expressed as follows.

8 VF ■・=VF+4 B−vF ■2=vF+4×2 V g−V F V,=Vp+ 4 x3 The intermediate value V□ is compared with the threshold level E9 in the level comparison circuit 52, and similarly, the intermediate value V2 is compared with the threshold level E8 by the level comparison circuit 53, and the intermediate value V by the level comparison circuit 54, respectively. Level comparison circuit 5
The output of level comparison circuit 53 is "0" (low level) when ■ y<E s, and "1" (high level) when ■ y ≧ Es. time 1'
0", 1" when v2≧Es, and the level comparison circuit 5
The output of 4 is "0" when v3<E, and "1n" when ≧Es.

The encoder 55 generates a second error signal ER of 2 bits ER2a, ER, - in accordance with the output levels of the level comparison circuits 52-54. Here, if the ER, □ bit is the lower bit and the ER2b bit is the upper bit, then
- As an example, the relationship between the threshold level E6 and the value of the second error latent signal ER2 for the intermediate levels V□ to ■ is expressed as shown in Table 1 below.

<Table 1> By the way, as shown in FIG. 7, the intermediate value V is a virtual level that is delayed by 18 of the period T of the reference clock φ9 from the value VF of the immediately preceding sample data, and similarly, the intermediate value V ,
, V□ are virtual levels delayed by Tg118T9 from the value V, respectively. Therefore, the second error signal ER2
indicates in which time region the threshold level Eg is divided between the immediately preceding and immediately following sample data by an intermediate section (direct 2, .about.2).

On the other hand, the digital luminance signal Y. The period of the sample data is equal to the period T3 of the reference clock φ9, and even if the amplitude of the synchronization signal fluctuates, the intermediate value is set as the threshold level E8.
Therefore, when there is no time axis variation in the digital luminance signal Y, or when the time axis variation is an integral multiple of the period T9 of the reference clock φ8, in each horizontal scanning period.

The timing at which the linear level line connecting levels VF and VB in FIG. Within one cycle T6, the timing at which the level line intersects the threshold level E8 varies between levels vF and VB for each horizontal scanning period.

From the above, the second error signal ER2, for example, by taking the values shown in Table 1 above, represents the time axis fluctuation within one cycle Ts of the reference clock φ9. An example of the relationship between the value of the second error signal ER2 and the amount of time-axis fluctuation is shown in Table 2 below.

<Table 2> In this way, the time axis error detection circuit 3 shown in FIG.
4, a first error signal ER□ and a second error signal ER2 are obtained. Note that the time T in FIG. 2 is the total time represented by the value of the first error signal ER1 and the value of the second error signal ER.

Further, in this specific example, the digital luminance signal Y0 is used to obtain the immediately preceding and immediately following sample data, but it goes without saying that the same effect can be achieved even if the input luminance signal Y is used.

However, in this case, it goes without saying that the data holding circuit 50 in FIG. 6 is supplied with data obtained by sampling this input luminance signal Y at the reference clock φ9. 5 is a block diagram showing another specific example of the time axis error detection circuit 34 in FIG. 1, in which 56 is a data holding circuit, 57 is an arithmetic circuit, and parts corresponding to those in FIG. 5 are given the same reference numerals and are duplicated. Omit the explanation.

In the figure, the counter 46 obtains error data ER1 having the same content as the first error signal ER1 obtained from the counter 46 in FIG. Error data E R having the same content as the second error signal ER2 obtained from the minute error detection circuit 49 in the figure.
' is obtained. These error data ER□'', ER2'
The total time represented by is the time T that includes the amount of time axis variation in the horizontal scanning period shown in FIG.

By the way, the time axis error detection circuit 34 shown in FIG.
If the time of the rear edge pulse BEP output from the level comparison circuit 48 with the front edge of the horizontal synchronization signal H5 as the time reference is the time of the rear edge pulse BEP output from the level comparison circuit 48, this time is detected for each horizontal scanning period. However, the time axis correction was made accordingly.

In FIG. 8, the time axis correction is performed according to the average value of the time tp of the horizontal scanning period for which one time axis correction is to be performed and the times tp of two horizontal scanning periods before and after this.

Therefore, in FIG. 9, the case where the first error signal ER□ and the second error signal ER2 in the horizontal scanning period H2 are formed will be described.
The time t +2 of 2 is the time T in FIG. 2 during this horizontal scanning period H2. This time iP' 2, a first error signal ER having a period Tll of the reference clock φ9 as a unit and a second error signal ER2 within one period T5 of the reference clock φ8 are formed. The time jP'2 obtained by this averaging is expressed as follows.

1, 2 = 18 tp1+ ”/2 t, 2+ ’ to jPi
(1) Here, as shown in FIG. 9, the count start time of the reference clock ψ6 of the counter 46 (FIG. 8) during the horizontal scanning period H2 is taken as the reference time, and the previous edge detection circuit 45 Counter 46 according to the reset pulse from
The reset period is set to 5, and the time T9 based on the error data E R', ER'2 in the horizontal scanning period HL IH1 is set to T, 8. T, . . . The time from when the counter 46 starts counting until it is completely set during the horizontal scanning period H is T1. Assuming T2, time 1.0 is based on reference time t0. □+P2+tP3 is tp□=-ΔT -T, + T8□ 1, □=T@2 t p3= T 2+ΔT+T@.

When these are substituted into the above equation (1), tP
'2 = 1/2T, 2+ "8 ('r2-T□+T
, □+T, 3)...(2). This time t,'2 is the reference time t. is based on the horizontal scanning period H
Time t at 2. This means that the correction time t02 is 2.

As is clear from equation (2), this time tQ'2 is a time that is an integral multiple of the period T8 of the reference clock φS and this period T
The former is the first error signal ER4 during the horizontal scanning period H2, and the latter is the second error signal E.
It is R2.

In FIG. 8, the arithmetic circuit 57 calculates jj of the above equation (2).
The first error signal ER and the second error signal E are calculated.
R2 is generated. T81°T@2+TQ in formula (2)
3 is the counter 46 during the horizontal scanning period H□, H2, H, respectively.
and error data ER' obtained from the minute error detection circuit 49.
2. It is obtained from ER'2, and the time T of equation (2),
, T2 are obtained from the count value from the reset release of the counter 46 to the next reset during the horizontal scanning period H4°H2. These count values are temporarily held in the data holding circuit 56, and taken into the arithmetic circuit 57 when calculating the above equation (2).

The above calculation is performed for each horizontal scanning period, and the calculation circuit 57 outputs the first error signal ER1 and the second error signal ER1 for each horizontal scanning period.
In this way, in this specific example, since the time axis variation is calculated by averaging the data obtained in three successive horizontal scanning periods, the S/R of the input video signal is output. Even if N is low, noise is reduced and the accuracy of time-opening axis error detection does not deteriorate.

However, in this specific example, as is clear from FIG. 9, the first error signal ER during the horizontal scanning period H2.

The second error signal ER2 is at time T of the next horizontal scanning period H7.
It is obtained after 1 is detected, and there is a delay of about IH in its generation. Therefore, the video signal to be corrected for one time axis must be delayed by about IH, but this requires the capacity of the memory 30°31 in Figure 1 to be about LH larger than the capacity originally required for time axis correction. However, the read timing from these memories 30 and 31 may be delayed by approximately IH under the control of the read timing generating circuit 35 (FIG. 1).

By the way, equation (2) shows an example of arithmetic processing, and does not limit the processing of the arithmetic circuit 57. next,
Another effect resulting from different arithmetic processing will be explained.

In the device of the present invention, writing to and reading from memory is performed using a single reference clock, so it is possible to correct the time axis of the signal by shifting it for each IH.
It is not possible to correct the expansion and contraction of the signal within H. Therefore, as mentioned above, when the time axis is corrected based on the horizontal synchronization signal, the time axis is corrected correctly at the left edge of the screen, but as you move to the right of the screen, more correction remains. Become. This residual correction is generally called a velocity error, and the details of its generation principle can be found in Saijo's RVTR Techniques, published by Japan Broadcasting Corporation, pp. 107-134, 1982.
It is mentioned in the following.

However, by devising the calculation in the calculation circuit 57 in FIG. 8, it is possible to reduce this velocity error. For example, the formula for time averaging is IIT.

1P': 2 t,, "2 jP)" - 2 fields (here, T
, is the standard new horizontal scanning period), and 2' is the time at the midpoint of the horizontal scanning period H2 shifted by H/2, so calculate according to equation (1)' and calculate the time If you correct the axis, the velocity error will be zero at the center of the two screens,
The velocity error at both ends of the screen is approximately half that of when calculation is performed using equation (1).

FIG. 10 is a block diagram showing a specific example of the interpolation filter 36 in FIG. 1, and 58 to 61 are latch circuits;
62 to 69 are coefficient circuits, 70 to 73 are multiplexers,
74 is an adder circuit.

In the figure, latch circuits 58 to 61 are connected in series, and a reference clock φ8 is used as a latch pulse to
Digital luminance signal YD read from 0 (Fig. 1)
' sample data sequentially for one period T of the reference clock φ8
Delay by 5 minutes.

The output data of the latch circuit 58 is multiplied by a coefficient of -1 in a coefficient circuit 62 and then supplied to the c and d contacts of the multiplexer 70. The output data of the latch circuit 59 is transmitted to the coefficient circuit 63.
, 64.65, respectively 18 and '8.

7 is multiplied by a coefficient to multiplexer 71.

Supplied to c and d contacts. The output data of the latch circuit 60 is supplied to the a contact of the multiplexer 72, and is multiplied by coefficients to 78 l'/911 in coefficient circuits 66, 67, and 68, respectively, and the output data of the multiplexer 72 is supplied to the a, c, and d contacts. is supplied to The output data of the latch circuit 61 is multiplied by a coefficient of -17' in a coefficient circuit 69 and then supplied to the contacts C and C of the multiplexer 73.

The multiplexers 70 to 73 are switched and controlled in accordance with a second error signal ER generated by the time axis error detection circuit 34 (FIG. 1) and a control signal Sc from the read timing generation circuit 35 (FIG. 1). However, they are linked so that contacts with the same sign are selected. Multiplexer 70~
The output data of 73 is added in an adder circuit 74, and the synchronization signal addition circuit 38 (
Figure 1).

The interpolation filter 36 having such a configuration uses a digital filter as time axis shifting means. First, the digital filter will be explained. Since the design method of the digital filter and the calculation method of the frequency characteristic are described in the general literature, only the main points will be explained.

Signal g (shi) whose frequency band is limited to W or less is transmitted over time T
='/2W sampled at intervals,...,g
(-2T), g(-T), g(0), g(T).

It is known that the signal consisting of sample data g(2T), .

It is expressed as

By the way, the fact that the original signal g (t) is restored by equation (3) means that by calculating equation (3), data representing the original signal g (t) between the above sample data is obtained, and these data are That is, the data is interpolated between sample data. Hereinafter, data interpolated between sample data will be referred to as interpolated data.

When sampling at the interval of time T mentioned above, the sampling frequency f is 1/T = 2 W. For example, a signal sampled at the sampling frequency fg is interpolated at 4f to obtain the original signal g(t ), use the above equation (3) as = T/4, 2/4T.

By substituting 3/・2T, etc.,
Interpolated data at these points in time can be obtained. This will be explained with reference to FIG.

In the figure, Q is indicated by a 0 mark. + Q4+ Q9!・・・
... is sasiple data whose sampling frequency is fg, and is sample data Q. So, 1=0. When the original signal gcL> is restored at 4f using equation (3) above for the signal sampled in this way, sample data Q is obtained. , Q, between 1/4f, (= T/4
) at equal time intervals, interpolated data qII q2 indicated by
1 ql is interpolated, and similarly, sample data Q, ,
Interpolated data qsy qGI q7 is interpolated between Q and
Thereafter, in the same manner, three pieces of interpolated data are interpolated at equal time intervals between each sample data.

Note that if the above equation (3) is calculated faithfully, the interpolated data will match the value of the original signal g (t), but since the sum of infinite terms is calculated, in reality, the error is within the allowable range. It is common to simplify the circuit configuration of the digital filter by cutting off the number of terms in equation (3) to the extent possible, and further approximating the square-shaped function S (t).

Further, when the sampling frequency f6 is sufficiently large with respect to the signal band W (ie, f, >2w), there is no problem in practical use even if the sampling frequency is simply linear interpolation.

By the way, in a digital filter in which interpolation is performed as shown in FIG. 11, QIl, q, q2゜qit Q
Instead of outputting data in the order of 'TSI...', if you output data at a time of 1/fs=T + t=Q, T, 2T,...
...and the sample data Qo l Q41 Ql?・
...Instead of, interpolated data qxr qsr qsr, which should be interpolated with a delay of T8 behind the sample data.
If we output..., then the sampling frequency f
The signal sampled at 11 has been shifted (advanced) in time by T8. Similarly, t=o, T,
Sample data Q at 2T,... +041
Interpolated data qz+ qsr instead of Q,...
'T engineering. , -..., the time axis has been shifted by T to ', and the interpolated data q] r q71
When 'T 1□2... is output, the time axis has been shifted by 38T.

In this way, it is possible to shift the input signal in the time axis using a digital filter, and the interpolation filters 36 and 37 shown in FIG. 1 are based on this principle, and FIG. 10 shows a specific example thereof.

In FIG. 10, the supplied digital luminance signal Y0
The sampling frequency fs of ' is equal to the frequency of the reference clock φ9, and is generally 4fgc as described above.

The multiplexers 70 to 73 are synchronized with the reference clock φ8, and the period Ts of the reference clock φ9 is changed to 1 by 3-*.
l) -) When switching in the order of C→d→a→..., a signal in which three interpolated data are interpolated between sample data is obtained from the adder circuit 74, as shown in FIG. The coefficients of coefficient circuits 62-69 are selected so that

Now, if T,/4 (='8 to s) is the delay unit, for the sample data at point A, the sample data at point B is T5, the sample data at point C is 2Ts, and the sample data at point A is T5. There will be a delay of 3T, Ts
Every time /4 time elapses, the sample data at points A, B, C, and D are further delayed in time by T y/4. Therefore, the time delay of T5/4 is calculated using the unit delay operator 2
-” and multiplexers 70 to 73 are set to 1 for every T5/4.
Assuming that the song order is changed in the order of a-+b-+c-+d→a→..., the transfer function H(z) of the digital filter at this time is H(z)=z-"+(1/4 z −' + 7/＠ z −' ”
7Hz-") + (-1858z-'0' to Z1-1 to z-42) + (-18z-"+78z-5+" to Z-g
)...Represented by (5). This is a low pass filter with a cutoff frequency of f8/2 and a response of approximately 1.

In equation (5), the first term on the right side is the multiplexer 70~
73 is the transfer function when the a contact is selected, and similarly, the second, third, and fourth terms on the right side are the transfer functions of the multiplexer 7, respectively.
0 to 73 are transfer functions when boc and d contacts are selected. Then, the latch circuits 58 to 61 collect sample data Q, , Q, , Q, . . . of the digital luminance signal Y9'.
When the multiplexers 70 to 73 are switched and controlled so that the contact point is selected at the time when is latched, that is, at the timing of the reference clock Φ8, the first term on the right side of the above equation (5) becomes the sample data Q. ,Q,,Q,.

. . . Similarly, the second term on the right side is a transfer function that generates interpolated data 'TL, 'TS, q, + -. which are delayed by T8/4 from these sample data.

Similarly, the third term on the right side is interpolated data 9□+ 'r*+ q, which is further delayed by T5/4. , . . . Similarly, the fourth term on the right side is an interpolated data word whose fourth term is further delayed by T9/4. 3. q fu, q engineering 4. It becomes a transfer function that produces...

For example, when the sample data Q, , Q, , Qo, (1) are latched in the latch circuits 58, 59, 60, and 61, respectively, and the multiplexers 70 to 73 are closed to the a contact, When the sample data Q is output and the multiplexers 70 to 73 are switched to b contacts after T g/4, according to the second term on the right side of the above equation (5).

18Q4+78Q. -18 Q.

Interpolated data q is obtained.

Therefore, if multiplexers 70 to 73 are not switched as described above but fixed to one of the a = d contacts,
Sample data or any one of three types of interpolated data is obtained.

For example, if the multiplexers 70 to 73 are left closed to the b contact side, the digital luminance signal Y will be generated.

Every time sample data of
874.

Therefore, as the interpolation filter 36, the multiplexer receives the control signal S from the read timing generation circuit 35 (FIG. 1). The second error signal ER, which is generated from the time axis error detection circuit 34 (FIG. 1), is controlled by
One of the contacts a and d is selected according to the amount of time axis variation within one cycle T5 of the reference clock φ8, which is represented by the reference clock φ8.

For example, as shown in FIG. 7, the second error signal ER2 has a one-time axis fluctuation amount of 27. When the TS is delayed, multiplexers 70 to 73 select the C contact. This results in a digital luminance signal Y. At the timing when sample data of ' is input, instead of these sample data, interpolated data qz+ qGI qxa+・
... will be output from the adder circuit 74.

This means that the digital luminance signal output from the adder circuit 74 is time-shifted by 28 Ts with respect to the input digital luminance signal YD'.
The time axis fluctuation of the 28 T delay described above will be eliminated.

In this way, each time the time axis error detection circuit 34 detects the second error signal ER2 from the horizontal synchronization signal during the horizontal scanning period, the contacts of the multiplexers 70 to 73 are selected accordingly, and the reference clock φS The time axis variation within IRNTg of is corrected.

The above also applies to the M-interval filter 37 in FIG.

The above is a description of the embodiment shown in FIG. 1. In this embodiment, writing control of input video signals to the memories 30 and 31 is performed using the horizontal synchronization signal HD separated by the synchronization separation circuit 32 as a time reference. However, this writing is to temporarily set the start timing of each horizontal scanning period of the input video signal.

This provisional start timing includes errors as shown in FIGS. 3 and 4. In order to correct the error in this provisional start timing and set the true start timing, the time axis error detection circuit 34 detects this error and outputs a first error signal ER□ and a second error signal ER. , and controls the readout timing of the memory 30.31 according to the first error signal ER□, and also controls the time axis shift amount of the interpolation filter 36.37 according to the second error signal ER. be.

According to this embodiment, the horizontal synchronization signal HD separated by the synchronization separation circuit 32 is used to set the temporary start timing of each horizontal scanning period, so there is no need to make the time axis accuracy very high. , therefore, the synchronization separation circuit 32
Therefore, it is not necessary to use the configuration shown in FIG. 20, and a conventionally used configuration with a simple configuration can be used. As a result, the input video signal does not need to be delayed by the LH delay circuit before being written into the memory, and no deterioration of frequency characteristics occurs.

In addition, the clock for writing and reading in the memory 30.31 and the clock for operating the interpolation filter 36.37 need only be the stable reference clock φ5, and when multiple sub-tallocks are used as shown in FIG. This problem can be avoided.

Note that the minimum unit of time axis fluctuation within one period Ts of the reference clock φ9 detected by the time axis error detection circuit 34 (T, /4 in the above explanation) and the minimum time axis shift amount of the interpolation filter 36° 37 are must match, but these are not limited to T5/4 in the above explanation; T,
It goes without saying that other amounts such as 7B, T, and /16 may be used, and the smaller the value, the higher the time axis correction accuracy.

FIG. 12 is a block diagram showing another embodiment of the time base correction device according to the present invention, in which 34' is a time base error detection circuit, 75 is an amplifier II, and the parts corresponding to FIG. The same reference numerals are used to omit duplicate explanations.

In the figure, the input luminance signal Y from the input terminal 23 is
After being amplified by an amplifier 75, it is converted into a digital luminance signal YD by an A/D converter 28.

On the other hand, the time axis error detection circuit 34' generates a first error signal ER□ and a second error signal ER, similar to the time axis error detection circuit 34 in FIG. Y. Detects the pedestal level of the pedestal and generates a control signal SP corresponding to the detected pedestal level. The amplifier 75 adjusts the DC level of the input luminance signal Y using the control signal S to keep its pedestal level constant.

The time axis error detection circuit 34' basically has the configuration shown in FIGS. 5 and 8, similar to the time axis error detection circuit 34 in FIG. The difference is that the above control signal S is also generated by the generation circuit 47.

FIG. 13 is a block diagram showing a specific example of the threshold level generation circuit 47' in this time axis error detection circuit 34', in which 77 and 78 are data holding circuits, and 78 is an LP
F, 79 is a reference pedestal level generation circuit, 80 is an arithmetic circuit, 81 is a level comparison circuit, and 82 is an LPF.

In the same figure, the digital signal Yr is supplied to data holding circuits 76 and 77, and is, for example, a synchronization separation circuit 32.
The pedestal level of the digital luminance signal VD is held in the data holding circuit 76 by the pedestal timing signal p formed from the horizontal synchronization signal HD separated in FIG. The data holding circuit 77 holds the synchronization leading edge level of the digital luminance signal YD.

The pedestal level held by the data holding circuit 76 is compared with the reference pedestal level output by the reference pedestal generation circuit 79 in the level comparison circuit 81, and after these error signals are averaged by the LPF 82, the control signal S , are supplied to the amplifier 75 as . As a result, the pedestal level of the digital luminance signal Y1 is always equal to the reference pedestal output from the reference pedestal generating circuit 79.

On the other hand, the data holding circuit 177 is outputted by the LPF 78 so that it represents a stable synchronization tip level even if the S/N of the input luminance signal Y is low, and then the reference pedestal generation circuit 79 outputs it in the arithmetic circuit 80. Arithmetic processing is performed with the reference pedestal level to generate a threshold level E8 which is an intermediate level between these levels.

In this embodiment, even if there is a level fluctuation in the input luminance signal Y, the pedestal level is kept constant by the amplifier 75, so that the detected threshold level in the 1-time axis error detection circuit 34' is equal to the input luminance. It is not affected by level fluctuations of the signal Y, and therefore, time axis fluctuations are always detected with high accuracy.

FIG. 14 is a block diagram showing still another embodiment of the time axis correction device according to the present invention, in which 83 is an A/D converter and 84 is a digital color decoder.

Reference numeral 85 denotes a reference clock generation circuit, and parts corresponding to those in FIGS. 1 and 12 are designated by the same reference numerals and redundant explanations will be omitted.

In FIG. 14, the reference nick generation circuit 85 is a PLL.
It consists of a circuit that multiplies by four the color subcarrier FsI: whose frequency is fsC, which is phase-synchronized with the input chroma C3 No. C input manually from the input terminal -24, and generates a reference clock φ9 whose frequency is 4Fs+H.

On the other hand, the human-powered chroma signal C input from the input terminal 24 is supplied to the A/D converter 83, and the reference clock generation circuit 8
The reference clock φ5 from 5 is converted into a digital chroma signal CD as a sampling pulse. This digital chroma signal C. is supplied to the digital color decoder 84, and the frequency obtained by dividing the reference clock φ5 by 4 in the frequency dividing circuit 27 is 4f, the carrier wave φ5. : The color signal components are alternately demodulated into two baseband digitized color signal components, and a digital color signal cBD which is a time division multiplexed signal of these color signal components is obtained. This digital color signal CBD is written into and read out from the memory 31 as in the previous embodiment.

Regarding digital color decoders, for example, "Television Society Journal J Vo12.33 No. 4 (1
979) pp. 35-39, the digital color decoder 8 of this embodiment
4 is also an application of this. Hereinafter, a specific example of this digital color decoder will be explained with reference to FIG. 15. However, 86 is a sign inverting circuit, and 87 is a multiplexer.

In the figure, sample data of a digital chroma signal Co with a sampling frequency of 4 fsC is directly supplied to a multiplexer 87, and is also supplied to a sign inverting circuit 8.
6, the positive and negative signs are inverted and supplied to the multiplexer 87. The multiplexer 87 is controlled by a select signal which is a carrier wave φsc having a frequency fsc, and converts the sample data of the supplied digital chroma signal CD and the sample data from the sign inverting circuit 86 into “i2 f s
They are selected alternately with a period of c.

As a result, the two color signal components of the digital chroma signal CD are alternately demodulated while being digitized, and the multiplexer 87 obtains a digital color signal csn in which these color signal components are time-division multiplexed.

The demodulation axis in this digital color decoder 84 is determined by adjusting the phase relationship between the input chroma signal C and the color subcarriers F, . . . (therefore, the reference clock ψ and the carrier wave ΦSC). ! , -Y@, r/Q@, etc. can be set arbitrarily. When correcting the L or L time axis, there is no need to limit the A-axis to a special one.2 Therefore, the adjustment of the phase relationship described above is not essential.7 As mentioned above, this embodiment Now, to generate the digital color signal CEID, it is sufficient to use the digital color decoder 84 with a simple configuration as shown in FIG. Compared to the embodiments, the circuit configuration is simplified and the cost is reduced, and the same time axis correction effect as those embodiments can be obtained.

Note that in this embodiment, the reference clock generation circuit 85
, the reference clock φ3 is the Kugata color print carrier wave F3. -4
A multiplication PLL circuit is used, but a 4fsc reference clock φ whose phase is locked to the burst signal of the input chroma signal C is used.
An oscillator that directly generates 5 may also be used.

Further, in FIG. 1, a color decoder 25° multiplexer 26 . In place of the A/D conversion IFi 29, the A/D converter 83. in FIG. Digital color decoder 8
4 may be used.

FIG. 16 is a block diagram showing still another embodiment of the time axis correction device according to the present invention, in which 88 is a digital color encoder, 89 is a D/A converter, and the parts corresponding to the previous drawings are The same reference numerals are used to omit duplicate explanations.

In the figure, the digital color signal CHD' output from the interpolation filter 37 is sent to the digital color encoder 88.
and is converted into a digital chroma signal CP' using the carrier wave φ9c from the frequency dividing circuit 27. This digital chroma signal Cp' is converted into an analog signal by a D/A converter 89, and sent to an output terminal 16 for time axis correction and a? Regarding the 9-digital color encoder that can obtain signal C', the above-mentioned ``Journal of the Television Society JV
oQ, 33° No. 4 (1979) pp, 35
39, etc., and the digital color encoder 88 in this embodiment is also an application of this, and performs inverse processing of the digital color decoding 84.

As mentioned above, in this embodiment, FIG.

In the embodiments shown in FIGS. 12 and 14, a digital color encoder 88 having a simpler configuration than the analog color encoder 43 is used to convert a digital color signal that has been time-base corrected into an analog chroma signal. Since only one D/A converter is required, the single circuit configuration becomes simple and inexpensive.

Although the present invention has been described in detail above, the present invention is not limited only to these examples.

For example, in the description of the above embodiment, the video signal is NTSC.
However, other television systems may be used.

Further, although the synchronization separation circuit 32 separates the horizontal synchronization signal of the input luminance signal Y, it may also separate the horizontal synchronization signal of the digital luminance signal YD from the A/D converter 28. In this case, the synchronous separation circuit 32 is as follows:
Like the threshold level generation circuit 47 in FIG. 5, a threshold level is generated from the pedestal level and the synchronization tip level, and this and the digital luminance signal Y
.

The horizontal synchronization signal may be separated by comparing the levels of the two signals.

[Effects of the Invention] As explained above, according to the present invention, (1) memory writing and reading are performed at the timing of a single reference clock, so the reference clock generation means is also simple and compact; can be used, making it possible to reduce the size and cost of the device.

(2) The synchronization separation circuit that separates the horizontal synchronization signal does not need to have a complicated configuration that uses a 1H delay circuit to increase separation accuracy, and it can also be used for low S/N input video signals.
Due to the effect of time axis averaging.

High time axis correction accuracy can be obtained.

(3) Therefore, when writing to the memory, there is no need to delay the input video signal with a delay circuit, and deterioration of the S/N and frequency characteristics of the video signal can be avoided.

(4) Set the intermediate level between the pedestal level and the synchronization tip level of the input video signal as the threshold level, remove the trailing edge of the horizontal synchronization signal of the video signal from the threshold level, and use the trailing edge as the threshold level. Since the time axis fluctuations are detected at the same time, even if the level of the input video signal fluctuates, the time axis fluctuations can be detected with high accuracy and the correction accuracy is high.

(5) When writing chroma signals into memory, a digital color decoder with a simple configuration using a reference clock can be used, and when reading from the memory, a digital color decoder with a simple configuration using the same reference clock can be used. Since a digital color encoder can be used, it
can be made smaller and lower cost.

(6) An inexpensive means that synchronizes with the color subcarrier can be used as a reference clock generating means, and excellent effects such as a reduction in the cost of the device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of time axis correction accuracy according to the present invention, FIG. 2 is a diagram showing a write operation in the memory in FIG. 1, and FIGS. 3 and 4 are respectively the same as in FIG. FIG. 5 is a block diagram showing a specific example of the time axis error detection circuit in FIG. 1;
6 is a block diagram showing a specific example of the minute error detection circuit in FIG. 5, FIG. 7 is an explanatory diagram of its operation, and FIG. 8 is a block diagram showing another specific example of the time axis error detection circuit in FIG. 1. A block diagram, FIG. 9 is a diagram explaining its operation, FIG. 10 is a block diagram showing a specific example of the interpolation filter in FIG. 1, FIG. 11 is a diagram explaining its principle, and FIG. F2 is a time axis correction according to the present invention. FIG. 13 is a block diagram showing another embodiment of the device; FIG.
FIG. 1 is a block diagram showing still another embodiment of the time axis correction device according to the present invention, FIG. 15 is a block diagram showing a specific example of the digital color encoder in FIG. 14, and FIG. A block diagram showing still another embodiment of the correction device, FIG. 17 is a block diagram showing conventional time axis correction accuracy, and FIGS. 18 and 19 respectively show the first embodiment.
FIG. 7 is a block diagram showing an example of the interfering tarlock generation circuit, and FIG. 20 is a block diagram showing an example of the synchronization separation circuit used in the write clock generation circuit shown in FIG. 17. 23...Input terminal for luminance signal, 24...Input terminal for chroma signal, 25...Color decoder, 2
6...Multiplexer, 28.29=-A/
D converter, 30.31...Memory, 32...Synchronization separation circuit, 34.34'...Time axis error detection circuit, 36.37...--Interpolation filter, 4°~・
12...D/A converter, 43...Color encoder, 44...Reference clock generation circuit 545...
・・Output terminal for luminance signal, ・16・・Output terminal for chroma signal, 75・Amplifier, 83・A/D converter,
84...Digital color decoder, 85...Reference clock generation circuit, 88...Digital color encoder, 89...D/A converter. Fig. 2 Fig. 3 φ5 HL) Fig. 4 s Fig. 5 - One stroke - Fig. 6 Fig. 7 c Between h - Fig. 10 Fig. aim - Fig. 8 Fig. 9

Claims (1)

[Scope of Claims] 1. In a time axis correction device that corrects time axis fluctuations of a video signal by digitizing the video signal, writing it to a memory, and reading it out, a standard for generating a single reference clock: a clock generating means; a synchronization separation means for separating a horizontal synchronization signal of the video signal; setting a start timing of each horizontal scanning period of the video signal based on the horizontal synchronization signal separated by the synchronization separation means; write timing generating means for writing the video signal into the memory in synchronization with the reference clock from the start timing for each horizontal scanning period; time axis error detection means for generating a first error signal representing a time axis fluctuation within one period of the reference clock and a second error signal representing a time axis fluctuation within one cycle of the reference clock; read timing means for reading a video signal written from the memory and setting a read start timing from the memory based on the first error signal for each horizontal scanning period of the video signal; A time axis correction device comprising: an interpolation filter that shifts the time axis of a video signal in units of one cycle or less of the reference clock according to the second error signal. 2. In claim 1, the time axis error detection means includes: threshold level generation means for generating a threshold level that is an intermediate level between the pedestal level and the synchronization tip level of the video signal; Level comparison means for comparing the level with the threshold level and generating an edge pulse representing a leading edge or a trailing edge of the horizontal synchronizing signal of the video signal; a counting means for outputting a count value of the reference clock from a start timing to immediately before the edge pulse; and generation of the threshold level and the level at the timing of the reference clock immediately before and after the edge pulse in the video signal. From a threshold level generated by the means, detect a time shift from the reference clock at a timing when the level of the front edge or the rear edge of the horizontal synchronization signal of the video signal matches the threshold level. minute error detection means, the output count value of the counting means is detected by the first
, and a detection output of the minute error detection means is used as the second error signal. 3. In claim 1, the time axis error detection means includes: threshold level generation means for generating a threshold level that is an intermediate level between the pedestal level and the synchronization tip level of the video signal; Level comparison means for comparing the level with the threshold level and generating an edge pulse representing a leading edge or a trailing edge of a horizontal synchronizing signal of the video signal; Counting means that starts counting the reference clock from the originally created horizontal start timing and outputs a first count value up to immediately before the edge pulse and a second count value up to the next horizontal start timing; The leading edge of the horizontal synchronizing signal of the video signal is determined from the level at the timing of the reference clock immediately before and after the edge pulse in the video signal and the threshold level generated by the threshold level generating means. or minute error detection means for detecting a time shift from the reference clock at the timing when the trailing edge level and the threshold level match, and a first count of the counting means in a plurality of consecutive horizontal scanning periods
, a calculation means for calculating the second count value and the detection output of the minute error detection means to generate the first and second error signals. 4. In claim 1, 2 or 3, the interpolation filter comprises: means for generating interpolation data that can be interpolated between sample data of the video signal read from the memory; A time axis correction device comprising means for selecting and outputting either the sample data or the interpolated data at the timing of the reference clock. 5. Claims 1, 2, 3, or 4, further comprising: means for detecting the amount of variation in the pedestal level of the input video signal; and adjusting the DC level of the input video signal according to the detection output of the means. A time axis correction device comprising means for adjusting the pedestal level of the input video signal to a constant level. 6. In claim 1, 2, 3, 4 or 5, the video signal is composed of a luminance signal and a chroma signal, and the memory and the interpolation filter are provided for each of the luminance signal and the chroma signal, and the chroma signal A time axis correction device characterized in that two demodulated color signal components of the chroma signal are time-division multiplexed and written into the memory as a digitized digital color signal. 7. In claim 6, the means for generating the digital color signal includes: a decoder that demodulates the inputted chroma signal into two color signal components; a multiplexer that time-division multiplexes the color signal components; A time axis correction device comprising an analog/digital converter that digitizes an output signal. 8. In claim 6, the means for generating the digital color signal includes: an analog/digital converter that digitizes the inputted chroma signal using the reference clock as a sampling pulse; and the digitalized chroma signal. and a decoder that alternately demodulates the reference clock into two digitized color signal components using frequency-divided pulses of the reference clock. 9. The time axis correction device according to claim 8, wherein the reference clock generation means receives a color subcarrier as an input signal and generates the reference clock phase-synchronized with the color printing carrier. 10. Claim 8 or 9, further comprising: an encoder that converts the digital chrominance signal output from the interpolation filter into a digitized chroma signal; and a digital chroma signal that converts the output signal of the encoder into an analog signal.
A time axis correction device characterized by comprising an analog converter.