JPH046846A - Semiconductor integrated circuit for analog scanning test - Google Patents
Semiconductor integrated circuit for analog scanning testInfo
- Publication number
- JPH046846A JPH046846A JP10961490A JP10961490A JPH046846A JP H046846 A JPH046846 A JP H046846A JP 10961490 A JP10961490 A JP 10961490A JP 10961490 A JP10961490 A JP 10961490A JP H046846 A JPH046846 A JP H046846A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- test
- circuit
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000012360 testing method Methods 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 abstract description 3
- 239000000523 sample Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 2
- 238000011990 functional testing Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000004927 clay Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路チップのウェハテスト、特に
入力端子のリーク電流等のアナログスキャンテストを容
易にする半導体集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit that facilitates wafer testing of semiconductor integrated circuit chips, particularly analog scan testing of input terminal leakage current, etc.
第g図は従来の半導体集積回路チップのウェハテストの
方法を説明するための平面図である。図において、+1
1は半導体集積回路チップ、・21は半導体集積回路チ
ップfil上の作られた外部接続用端子(以下ポンディ
ングパッドと呼ぶ)31ハポンデイングパツド)21に
接続するチップテスト用の接触針である。14)はポン
デイグパッド!1に接続された入力回路1,61はポン
ディングパッド12)に接続された出力回路である。FIG. g is a plan view for explaining a conventional wafer test method for semiconductor integrated circuit chips. In the figure, +1
1 is a semiconductor integrated circuit chip, and 21 is a contact needle for chip testing that connects to an external connection terminal (hereinafter referred to as a bonding pad) 31 made on the semiconductor integrated circuit chip fil. . 14) is Pondaig Pad! The input circuit 1, 61 connected to the pad 1 is an output circuit connected to the bonding pad 12).
次に動作について説明する。Next, the operation will be explained.
測定丁べき半導体集積回路チップ+11上の人力−#8
F+41、出力回路11の特性は、チップテスト用の接
触針(31t−介して半導体集積回路検量装置(図示せ
ず>VCm続され測定が実施されていた0〔発明が解決
しようとする課題〕
従来の半導体集積回路チップテストは以上のように構成
されていたので、ボンディング/(ラドにチップテスト
用の接触針が必ず接触しないとテスト実施ができなかっ
た。Human power on semiconductor integrated circuit chip +11 to be measured - #8
The characteristics of F+41 and the output circuit 11 were measured by connecting them to a semiconductor integrated circuit calibration device (not shown) via a contact needle (31t) for chip testing. Since the semiconductor integrated circuit chip test was configured as described above, the test could not be carried out unless the contact needle for the chip test was always in contact with the bonding/rad.
一万、ポンディングパッドの間隔#′i従来に160μ
mのピッチが標準であったが、ボンデインク技術の改良
により、75〜50μmピンチ以下の倣iボンディング
が可能となシ、チップテスト用の接触針に75〜50μ
mピッチのように微細に製作し、75〜50μmピッチ
以下の倣細なポンディングパッドに接触することが困難
であるという問題点があった。10,000, the spacing between the bonding pads #'i was 160μ in the past.
m pitch was the standard, but improvements in bonding ink technology have made it possible to imitate i-bonding with a pinch of 75 to 50 μm or less.
There is a problem in that it is difficult to fabricate a fine bonding pad with a pitch of 75 to 50 μm or less and make contact with a fine bonding pad having a pitch of 75 to 50 μm or less.
この発明は上記のような問題点?解決するためになされ
たもので、ポンディングパッドにチップテスト用の接触
針が必ず接触しないとテスト実施ができなかった欠点を
解決し、75〜60μmピッチ以下の微細ポンディング
パッドピンチの半導体集積回路チップのウェハテストヲ
実施できる半導体集積回路を得るこのを目的とする。Does this invention have the above problems? This was done to solve the problem that testing could not be carried out unless the contact needle for chip testing made contact with the bonding pad, and it was developed to solve the problem of semiconductor integrated circuits with fine bonding pad pinches with a pitch of 75 to 60 μm or less. The purpose of this invention is to obtain a semiconductor integrated circuit that can perform chip wafer testing.
〔課題を解決する之めの手段および作用〕この発明に係
る半導体集積回路は、アナログスキャンテスト用の回路
とテスト用の少数のポンディングパッドをチップ上に内
蔵することによって、チップテスト用の接触針が必ず接
触しないとテスト実施ができなかった欠点を解決し。[Means and operations for solving the problem] The semiconductor integrated circuit according to the present invention has a circuit for analog scan testing and a small number of bonding pads for testing built into the chip, so that contact for chip testing can be improved. Solved the drawback that tests could not be performed unless the needles were in contact with each other.
どのような微細なポンディングパッドピッチの半導体集
積回路チップのウェハテストも実施可能とする。Wafer testing of semiconductor integrated circuit chips with any fine bonding pad pitch can be performed.
以下、この発明の一夫施−It図について説明する。@
1図において、1lr1半導体集積回路チップ、+!I
H半導体集積回路チップIII上に作られたポンディン
グパッド、t:11iチツプテスト用の接触針、(4)
はポンプイングツくラド121に接続された入力回路、
15)はポンディングパッド:2)に妥絖された出力回
路、161ハボンデイングパツド(2)に接続された半
導体スイッチ(以下アナログスイッチと呼ぶ) 、+7
1はアナログスツチ16)ヲコントロールする制御回路
、(8)は制御10回路(71への入力信号、(9)は
アナログスイッチ)61の共通接続された信号線、+1
01は半導体集積回路チップ田土に内蔵された演算増幅
器、dllは演算増幅器11Qlの帰還素子、U力は演
算増幅器+101の出力信号線、(131に演算増幅器
tillの入力信号線、a41は半導体集積回路チップ
田土に作られたテスト用パッドである。The Kazufu-It diagram of this invention will be explained below. @
In Figure 1, 1lr1 semiconductor integrated circuit chip, +! I
Bonding pad made on H semiconductor integrated circuit chip III, contact needle for t:11i chip test, (4)
is the input circuit connected to the pumping unit Rad 121,
15) is the bonding pad: 2) is the output circuit, 161 is the semiconductor switch (hereinafter referred to as analog switch) connected to the bonding pad (2), +7
1 is the control circuit that controls the analog switch 16), (8) is the control circuit 10 (input signal to 71, (9) is the analog switch) 61 commonly connected signal line, +1
01 is the operational amplifier built in the semiconductor integrated circuit chip Tadochi, dll is the feedback element of the operational amplifier 11Ql, U power is the output signal line of the operational amplifier +101, (131 is the input signal line of the operational amplifier till, and a41 is the semiconductor integrated circuit This is a test pad made from chip clay.
次に動作について説明する。チップテスト用の接触針1
3)とテスト用パッド04により、アナログスイッチ1
6)ヲコントロールする制御回路;7)への入力号信(
8)が送られる。1lla回路(7)はシフトレジスタ
の様な回路で構成されており、入力信号18)に応じて
、多数存在するアナログスイッチ16)の内1)を導通
させる。例えば、入力回路、4の入力リーク電流全測定
する時は、入力回路)4に接続されたアナログスイッチ
(6)を導通させる。Next, the operation will be explained. Contact needle 1 for chip test
3) and test pad 04, analog switch 1
6) Control circuit to control; input signal to 7) (
8) will be sent. The 1lla circuit (7) is composed of a circuit such as a shift register, and turns on one of the many analog switches 16) in response to the input signal 18). For example, when measuring the total input leakage current of the input circuit 4, the analog switch (6) connected to the input circuit 4 is turned on.
ついで演算増幅器1010入力信号融α濁に半導体集積
回路の外部から電圧を加える。入力信号線α4の電圧は
入力回路141に加わり、入力回路nuc’J−り電流
がある場合は、リーク電流は、アナログスイッチ(6)
を介して、演算増幅@ tlol 、帰還素子Lu1l
により、電流電圧変換され、演算項@器UO+の出力信
号線+121よや測定される。出力面1it!r +6
1にリーク電流がある場合も同様ic、IJ−り電流は
アナログスイッチ(6)ヲ介して、演算増幅器U〔、帰
還素子Uυにより、電流電圧変換され、演算増幅器dα
の出力信号線’J2+より、#I定される。Then, a voltage is applied to the operational amplifier 1010 input signal amplification from outside the semiconductor integrated circuit. The voltage of the input signal line α4 is applied to the input circuit 141, and if there is a current from the input circuit nuc'J-, the leakage current flows through the analog switch (6).
Through the operational amplifier @ tlol , the feedback element Lu1l
The current is converted into voltage and measured by the output signal line +121 of the operational term UO+. Output side 1it! r+6
Similarly, when there is a leakage current in 1, the IC and IJ currents are converted into voltage by the operational amplifier U[, feedback element Uυ] through the analog switch (6), and then converted into the operational amplifier dα.
#I is determined from the output signal line 'J2+.
また、半導体集積回路の機能試験はバクンダリスキャン
方式で実施する。バクンダリスキャン方式によれはチッ
プ上の各バンドに接触することなく、少数のテストパッ
ドのみで半導体集積回路の機能試験を実施することが可
能である。In addition, functional tests of semiconductor integrated circuits are conducted using the background scan method. By using the background scan method, it is possible to perform a functional test on a semiconductor integrated circuit using only a small number of test pads without contacting each band on the chip.
なお上記実施例では演算項@器(lO]の帰還素子ul
lをダイオードによって構成した場合を示したが、抵抗
であってもよい。また、上記実見的では演算項@器:1
01、帰還素子0會半導体集積回路チップに内蔵した場
合を示したが、外付であってもよく上記実見的と同様の
効果を奏する。Note that in the above embodiment, the feedback element ul of the operand @
Although the case where l is constituted by a diode is shown, it may be a resistor. Also, in the above practical case, the operand @ device: 1
01, Feedback element 0 Although the case where the feedback element is built into the semiconductor integrated circuit chip is shown, it may be attached externally and the same effect as the above-mentioned actual result can be obtained.
以上のようにこの発明によれば、amポンディングパッ
ドピッチの半導体集積回路チップのウエハテストヲ、ア
ナログスキャンテスト用半導体集積回路を作ることで実
施したので、どのような微細なポンディングパッドピン
チの半導体集積回路チップのウェハテストも実施可能な
テスト装置を安価VC製作でき、また精度の高い試験*
111が得られるなどの効果がめる。As described above, according to the present invention, a wafer test of a semiconductor integrated circuit chip with am bonding pad pitch is carried out by making a semiconductor integrated circuit for analog scan test. We can manufacture inexpensive VC test equipment that can perform wafer testing of circuit chips, and also provide highly accurate testing*
111 can be obtained.
第1図にこの発明の一実施列一でよるアナログス中ヤン
テスト用半導体集積回路の平面図、第2図に従来の半導
体集積回路チップのウェハテストの方法を説明するため
の平面図である。
区において、111は半導体集積回路チップ、(21は
ポンディングパッド、j3:はチップテスト用の接触針
、(41は入力回路、15)は出力回路、161はアナ
ログスイッチ、(7)は制御回路%(81は制御(ロ)
路の入力信号、(9)ニアナログスイッチの共通接続さ
れた信号線* tlQlは演算増幅器、 ULlは演算
増幅器の帰還素子、じは演算増幅器の出力信号線。
峙は演算増幅器の入力信号線、α4はテスト用パッドを
示す。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a plan view of a semiconductor integrated circuit for analog testing according to one embodiment of the present invention, and FIG. 2 is a plan view for explaining a conventional method of wafer testing of semiconductor integrated circuit chips. 111 is a semiconductor integrated circuit chip, (21 is a bonding pad, j3 is a contact needle for chip testing, (41 is an input circuit, 15) is an output circuit, 161 is an analog switch, (7) is a control circuit % (81 is control (b)
(9) Commonly connected signal line of the analog switch * tlQl is the operational amplifier, ULl is the feedback element of the operational amplifier, and the same is the output signal line of the operational amplifier. The opposite side shows the input signal line of the operational amplifier, and α4 shows the test pad. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
れた半導体スイッチと、この半導体スイッチをコントロ
ールする回路と、前記半導体スイッチに接続されたテス
ト用端子と、前記半導体スイッチをコントロールする回
路へ外部から信号を入力するためのテスト用端子とを備
えたことを特徴とするアナログスキャンテスト用半導体
集積回路。A semiconductor switch connected to an external connection terminal on a semiconductor integrated circuit chip, a circuit that controls this semiconductor switch, a test terminal connected to the semiconductor switch, and a circuit that controls the semiconductor switch from the outside. A semiconductor integrated circuit for analog scan testing, comprising a test terminal for inputting a signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10961490A JPH046846A (en) | 1990-04-24 | 1990-04-24 | Semiconductor integrated circuit for analog scanning test |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10961490A JPH046846A (en) | 1990-04-24 | 1990-04-24 | Semiconductor integrated circuit for analog scanning test |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH046846A true JPH046846A (en) | 1992-01-10 |
Family
ID=14514763
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10961490A Pending JPH046846A (en) | 1990-04-24 | 1990-04-24 | Semiconductor integrated circuit for analog scanning test |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH046846A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5940965A (en) * | 1995-02-03 | 1999-08-24 | Hewlett-Packard Company | Method of making multiple lead voltage probe |
-
1990
- 1990-04-24 JP JP10961490A patent/JPH046846A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5940965A (en) * | 1995-02-03 | 1999-08-24 | Hewlett-Packard Company | Method of making multiple lead voltage probe |
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