JPH0468447A - Stop circuit for microprocessor - Google Patents

Abstract

PURPOSE:To investigate the cause of malfunction and to improve efficiency for program debugging by stopping a microprocessor when plural specified addresses are executed in a prescribed order. CONSTITUTION:When the execution address of the microprocessor is coincident with the comparison addresses of registers 111-11n from the first step to an (n)-th step, flip-flops 161-16n are set in the order from the first step to the (n)-th step and a stop control signal is outputted from the flip-flop 16n in the final (n)-th step. Therefore, when the plural specified steps of a program are executed in the prescribed order, the microprocessor can be stopped. Thus, the cause of malfunction can be investigated and efficiency for program debugging can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a microprocessor stop circuit that stops a microprocessor when a specific address is executed, this invention stops the microprocessor when a plurality of specific addresses are executed in a predetermined order, and investigates the cause of malfunction. and n (n is an integer of 2 or more) that stores comparison addresses for the purpose of improving the efficiency of program debugging.
an n-stage comparator that is provided corresponding to each of the n-stage registers and outputs a match signal when an execution address output by the microprocessor matches a comparison address of each of the n-stage registers; , n-stage flip-flops are provided corresponding to the n-stage comparators and are set by supplying a coincidence signal, and when each of the 1st stage to n-1 stage flip-flops is set, the 2nd stage to n stage flip-flops are set. The microprocessor is configured to provide a control signal for stopping the microprocessor by a set of the n-stage flip-flops.

[Industrial application field]

The present invention relates to a microprocessor stop circuit, and more particularly, to a microprocessor stop circuit that stops the microprocessor when a specific address is executed.

[Conventional technology]

Conventionally, as described in Japanese Patent Application No. 54-169046,
The address bus of the microprocessor is monitored, and when the address set in the register as a parameter in advance matches the address on the address bus, the microprocessor is forcibly stopped, and the register contents or memory of the microprocessor at this time are The contents are analyzed and used for program debugging, etc.

[Problem to be solved by the invention]

Conventional halt circuits halt the microprocessor at a single specific address. For example, if the address of step S7 is set in the register as a parameter in the process shown in FIG.
, S2. S3. First route of S7, step 31. S
2. S4゜S5. The second route of S7, step Sl,
S2゜S4. S5. S6. In any case of the third route of S7, if step S7 is executed, the microprocessor will stop, and when the process is executed by any specific route among the first to third routes, However, it was not possible to stop the microprocessor, and it was not possible to efficiently investigate the cause of malfunctions in the microprocessor, resulting in poor program debugging efficiency.

The present invention has been made in view of the above points, and provides a microprocessor stop circuit that stops the microprocessor when a plurality of specific addresses are executed in a predetermined order, thereby improving the efficiency of investigating the causes of malfunctions and debugging programs. The purpose is to

[Means to solve the problem]

The stop circuit of the microprocessor of the present invention is provided corresponding to n stages of registers (n is an integer of 2 or more) each storing a comparison address, and an execution address output from the microprocessor. An n-stage comparator that outputs a match signal when it matches the comparison address of each of the n-stage registers, and an n-stage flip-flop that is provided corresponding to the n-stage comparator and is set by supplying the match signal. and a gate circuit that supplies a match signal from each of the second to n stages of comparators to each of the second to n stages of flip-flops when each of the first to n-1 stages of flip-flops is set, A control signal for stopping the microprocessor is obtained by a set of n-stage flip-flops.

[Effect]

In the present invention, when the execution address of the microprocessor matches the comparison address of the registers from the 1st stage to the nth stage, the flip-flops are set in the order of the 1st stage to the nth stage, and a stop control signal is output from the last n stage flip-flop. be done. Therefore, the microprocessor is stopped when a plurality of specific steps of the program are executed in a predetermined order, thereby improving the efficiency of investigating the cause of malfunction and debugging the program.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of the circuit of the present invention.

In the figure, 10 is a data bus of the microprocessor, and registers 1 to 11 . Comparison addresses are sequentially supplied to each of them. Register 11. ~
11. Each of the terminals 121 to 12° stores a comparison address from the data bus 10 when a set instruction signal is received, and compares each of the stored comparison addresses 14+ to 14. supply to each.

Comparator 14. An execution address is supplied from the address bus 15 of the microprocessor to each of the comparators 14, -14. Each is an execution address or register 11
1-I1. , H when it matches the comparison address from each
Generate level matching signals.

JK flip-flops 16+ to 16. correspond to the comparators 14□ to 14ゎ, respectively. , are provided, and the input terminals of these are supplied with a reset signal from the terminal 17 to be reset. Comparator 14. The coincidence signal output from flip-flop 16. J input terminal of this flip-flop 16. is set, and the Q terminal output of flip-flop 16+ becomes H level. This Q terminal output is supplied to the AND circuit 181, and the AND circuit 18
．． When supplied with an H-level match signal from the comparator 142 after the output of the flip-flop 161 becomes H level, this match signal is supplied to the J terminal of the flip-flop 162 and set.

Thereafter, similarly, the Q terminal output of the flip-flop is ANDed with the coincidence signal of the next-stage comparator in the AND circuit, and the AND circuit output is supplied to the J terminal of the next-stage flip-flop. When the Q terminal output of the final stage flip-flop 161 reaches H level, this is supplied as a stop control signal from the terminal 20 to the microprocessor main body (not shown).

Here, registers 111-11. Steps Sl and S2 in FIG. 3, respectively. S4. S5. S6. The case where the addresses of each S7 are set will be explained. When step S1 is executed, the comparator 141 outputs a coincidence signal as shown in FIG. outputs the Q terminal output as shown in FIG. 2(B). Thereafter, when step Sl is executed, the comparator 142 outputs a coincidence signal as shown in FIG. 2(C), thereby causing the flip-flop 16. The output from the Q terminal rises as shown in FIG. 2(D). After this, steps S4°S5. When step S6 is executed in order, the Q terminal output of the flip-flop in the previous stage, which is supplied to the AND circuit 18n, becomes H level, and when step S7 is executed, the output from the comparator 14. outputs a coincidence signal as shown in FIG.
The stop control signal shown in F) is output, and the microprocessor stops.

In this way, the execution address of the microprocessor is stored in registers 11 . ~11. When the address matches the comparison address of the flip-flops 16. to 16.
~16. is set and the last n-stage flip-flop 1
A stop control signal is output from 6. Therefore, the microprocessor can be stopped when a plurality of specific steps of the program are executed in a predetermined order, thereby improving the efficiency of investigating the cause of malfunction and debugging the program.

Note that registers 111 to 11. The comparison addresses stored in each do not need to be addresses of consecutive steps;
It is not limited to the above embodiments.

〔Effect of the invention〕

As described above, according to the microprocessor stop circuit of the present invention, it is possible to stop the microprocessor when a plurality of specific addresses are executed in a predetermined order, thereby improving the efficiency of investigating the causes of malfunctions and debugging programs. Above all, it is extremely useful.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of one embodiment of the circuit of the present invention, and Fig. 2 is a circuit diagram of an embodiment of the circuit of the present invention.
The signal waveform diagram of each part of the circuit shown in the figure and FIG. 3 are diagrams for explaining the circuit operation of the present invention. In the figure, 11-11. , are registers, 4□~14. 5 is a comparator, 5 is an address bus, 61 to 16A are flip-flops, and 8 to 18A are AND circuits. Figure 2: Signal waveform diagram for each part of the circuit in Figure 1

Claims (1)

[Claims] Comparison addresses are stored respectively n (n is an integer of 2 or more)
Provided corresponding to the stage registers (11_1 to 11_n) and the n stage registers (11_1 to 11_n), respectively,
an n-stage comparator (14_n) that outputs a match signal when the execution address output by the microprocessor matches the comparison address of each of the n-stage registers (11_1 to 11_n);
1 to 14_n), n-stage flip-flops (16_1 to 16_n) provided corresponding to the n-stage comparators (14_1 to 14_n) and set by supplying a match signal, and
Stage flip-flop (16_1 to 16_n_-_1)
When each is set, 2 to n stage comparators (14_
a set of n-stage flip-flops (16_n); A stop circuit for a microprocessor, characterized in that the circuit obtains a control signal for stopping the microprocessor.