JPH0467681A - Mis semiconductor device - Google Patents

Abstract

PURPOSE:To enable a MIS semiconductor device to be restrained from deteriorating in breakdown strength, improved in reliability, and applied to a wider range as a circuit element by a method wherein a metal layer isolated from a channel region is provided coming into contact with a source region. CONSTITUTION:A metal layer 28 isolated from a channel region 27 is provided inside a semiconductor layer 23 coming into contact with a source region 25. A distance WN between the metal layer 28 and the channel region 27 or the width of the source region 25 is set smaller than the diffusion length of minority carriers in the source region 25, whereby minority carriers are lessened in effective length of diffusion in the source region 25, and a minority carrier current induced by impact ionization inside the channel region 27 is made to flow out through the source region 25 and the metal layer 28. When a Schottky junction is formed between the metal layer 28 and the source region 25, a Hall current flowing through the metal layer 28 is enhanced by an electrical field applied to the interface concerned. Therefore, a MISFET is prevented from deteriorating in breakdown strength between a source and a drain keeping the merits of a MISFET provided with an SOI substrate.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a so-called SOI (silicon on 1n) in which a semiconductor thin layer is formed on a substrate with an insulating layer interposed therebetween.
M is applied to the semiconductor thin layer using a
The present invention relates to a MIS type semiconductor device formed by forming a semiconductor element with an IS structure.

[Summary of the invention]

The present invention relates to an MIS type semiconductor device in which a semiconductor layer is formed on an insulating substrate, and a gate electrode is formed on this semiconductor layer via a gate insulating film. By providing a layered structure, the reduction in breakdown voltage caused by impact ionization, which is a drawback of MIS semiconductor devices formed on a Sol substrate, is suppressed, and the reliability of this type of MIS semiconductor device is increased. It is something.

Further, the present invention provides a semiconductor layer formed on an insulating substrate,
In an MIS type semiconductor device in which a gate electrode is formed on this semiconductor layer via a gate insulating film, a high concentration region and a low concentration region are provided below the high concentration region as a source region, and the low concentration region and the high concentration region of the source region are provided. By providing a metal layer in contact with and separated from the channel region,
This is intended to further suppress the drop in breakdown voltage due to impact ionization, which is a drawback of MIS type semiconductor devices formed on Sol substrates, and to improve the performance of this type of MIS type semiconductor devices.

Further, the present invention provides a semiconductor layer formed on an insulating substrate,
In an MIS type semiconductor device in which a gate electrode is formed on this semiconductor layer via a gate insulating film, a Schottky junction is formed in contact with the drain region, and a metal layer is provided separated from the channel region. , Sol
It suppresses the drop in breakdown voltage due to impact ionization, which is a drawback of MIS type semiconductor devices formed on a substrate,
This is intended to improve the reliability of this type of MIS type semiconductor device.

[Conventional technology]

Recently, many advantages have been reported regarding so-called thin film SOI devices using SOI substrates. For example, it has a high degree of freedom in setting the impurity concentration in the channel region, has high alpha ray resistance, is latch-up free, and can achieve high speed by reducing the parasitic capacitance between the substrate and the silicon thin film that is the element formation region. It has advantages such as:

For this reason, research on thin film SOI devices is currently being actively conducted, and their development is progressing.

For example, an MIS field effect transistor (hereinafter abbreviated as MISFET) using a Sol substrate is manufactured by bonding a silicon substrate (
1) Using an SOT substrate (4) on which an island-shaped silicon thin film (so-called Sol film) (3) is formed via a SiO2 film (2), a source region of the first conductivity type is formed in the silicon thin film (3). (5) and drain region (6) are formed, and a polycrystalline polycrystalline film is formed on the silicon thin film (3) between the source region (5) and drain region (6) via a gate insulating film (7) such as SiO□. It is constructed by forming a gate electrode (8) made of silicon. (9) is a source electrode, and (10) is a drain electrode.

[Problem to be solved by the invention]

However, MISFE using Sol substrate (4)
T(11) has a drawback that the source-drain breakdown voltage, that is, the source-drain breakdown voltage is low. As shown in FIG. 15, in the MISFET (11), minority carriers (electrons) e injected from the source region (5) to the channel region (12) are transferred to the drain region (6).
) side, these electrons e cause impact ionization in the high electric field region (13) occurring at the drain end under the gate electrode (8), and electron-hole pairs are generated.
Of these, holes are caused by flowing into the channel region (12). That is, normal bulk type MTS
In the FET, holes h (so-called hole current 1p) flowing into the channel region escape as substrate current through the substrate, but
In this SOI substrate, the silicon thin film (3) is SiO
□ Since the hole is surrounded by the film (2) and is not structured to allow the holes to escape, the holes accumulate in the channel region (12) near the source region (5).

These accumulated holes lower the energy barrier between the source and the channel, and as a result, the source acts as an electron emitter, in addition to the normal flow of electrons (channel current c) flowing into the channel region (12). The bipolar-operated electron current I7 is generated. This electron current I7
again causes a positive feedback phenomenon that generates a hole current Ip in the high electric field region (13), and the drain current ■. sharply increases, resulting in the source −
Decreases drain-to-drain breakdown voltage.

Various methods have been proposed in the past to suppress the decrease in source-drain breakdown voltage caused by impact ionization.

For example, in the MISFET (14) shown in FIG. 16, the hole current caused by impact ionization is reduced by increasing the thickness of the silicon thin film (3) in the portion corresponding to the drain region (6) and weakening the electric field at the drain end. This is intended to reduce the occurrence and improve the source-drain breakdown voltage. However, this method has disadvantages in that the structure is complicated and difficult to manufacture, and the effect is insufficient. Also, MISFET (15) in Fig. 17
The source region (5) and the drain region (6) are formed to be shallower than the silicon thin film (3), and the source region (5)
A source region (5) and a channel region (12) are located outside of the source region (5).
) by forming a semiconductor region (16) of the same conductivity type and leading out an electrode (17) from it, holes generated by impact ionization can escape through the semiconductor region (16), An attempt is made to improve the source-drain breakdown voltage. In this method, in order to form the semiconductor region (16), the area of the silicon thin film (3) becomes large, and the parasitic capacitance between the region (12) and the region (12) becomes large, which eliminates the advantage of MISFET using an SOI substrate. Because the film thickness of the silicon thin film (3) is substantially thicker, the short channel effect is more likely to occur, and in order to prevent this, the channel concentration is inevitably increased, and as a result, the carrier movement is S0 that can increase the degree of
■There is a disadvantage that the advantages of MISFET using a substrate are lost.

On the other hand, a structure shown in FIG. 18 has been considered as one that is rational in terms of manufacturing method and structure. The MISFET (18) shown in FIG. 18 has a semiconductor region (16) of the same conductivity type as the channel region (12) formed in contact with the outside of a shallow source region (5), and a source electrode (9). By sharing the two terminals, it can be used as a normal three-terminal element. Also in the case of this old 5FET (18), holes generated by impact ionization can be released through the semiconductor region (16) and the source electrode (9), so that the drain breakdown voltage can be improved. However, as shown in FIG. 19, MISFET (18) has a drain region (6) that is
If a semiconductor region (19) of the same conductivity type as the semiconductor region (16) is formed outside of the semiconductor region (16), holes leaking from the semiconductor region (19) to the channel region (12) will flow into the source region (
5) side semiconductor region (16) (indicated as a hole current Ipp in FIG. 19), and for example, during non-operation, there arises the problem that the source and drain are short-circuited and conductive. Therefore, this structure cannot be applied to a switching element such as an access transistor of a static RAM cell in which the source and drain are alternately used, and there is a drawback that the range of application as a circuit element is limited.

In view of the above-mentioned points, the present invention is an MIS type semiconductor that can suppress the drop in breakdown voltage caused by impact ionization, increase the multiplier performance of the semiconductor device itself, and expand the range of application as a circuit element. It provides equipment.

[Means to solve the problem]

As shown in FIG. 1 (and others in FIG. 2, FIG. 3, FIG. 4, and FIG. 5), a semiconductor layer (23) is formed on an insulating substrate (22), and this semiconductor layer (23) In an MTS type semiconductor device on which a gate electrode (30) is formed via a gate insulating film (29), a metal layer (28) is in contact with a source region (25) and is separated from a channel region (27). )
It consists of:

Further, as shown in FIG. 6 (and other FIG. 7), the present invention also provides a semiconductor layer (23) formed on an insulating substrate (22), and a gate insulating film (29) on this semiconductor layer (23). ), the source region (25) has a high concentration region (25
a) and a low concentration region (25c) below it, and a low concentration region (25c) and a high concentration region (25c) of the source region (25).
25a) and a metal layer (28) separated from the channel region (27).

Further, as shown in FIG. 13, the present invention provides an insulating substrate (
22) In an MIS type semiconductor device in which a semiconductor layer (23) is formed on the semiconductor layer (23) and a gate electrode (30) is formed on the semiconductor layer (23) via a gate insulating film (29), the drain region (26) forms a Schottky junction in contact with
and a metal layer (28) separated from the channel region (27).
It consists of:

[Effect]

According to the first invention, for example, as shown in FIG. 1, a metal layer (28) is provided in the semiconductor layer (23) in contact with the source region (25) and separated from the channel region (27). By making the distance (width) W8 of the source region (25) between the metal layer (28) and the channel region (27) the diffusion length of the minority carriers in the source region, by making it smaller, the distance (width) W8 of the source region (25) can be made smaller. As the effective diffusion length of
25) and the metal layer (28). In this configuration, the metal layer (28) and the source region (2
5) When a Schottky junction is formed between the metal layers (28), the electric field applied to the interface further increases the hole current flowing through the metal layer (28).

Therefore, it is possible to maintain the advantages of the MISFET using the SO2 substrate and prevent a decrease in the breakdown voltage between the source and drain, and it is also possible to prevent short circuits and conduction phenomena when the device structure is made symmetrical. It is possible to improve the reliability of the semiconductor device itself and the range of usage as a circuit element.

Further, in the second invention, a high concentration region (25a) and a low concentration region (25c) are provided below the high concentration region (25a) as a source region, and a low concentration region (25c) of the source region is provided in the semiconductor layer (23).
5c) and the high concentration region (25a) and is separated from the channel region (27), a Schottky junction is formed between the metal layer (28) and the low concentration region (25c). , metal layer (28) and high concentration region (
25a) is an ohmink contact. In this case as well, the metal layer (28) connects the metal layer (28) and the channel region (2).
7) The distance (width) WN of the low concentration region (25c) between the metal layer (28) and the low concentration region (25c) is made smaller than the minority carrier diffusion length LP of the low concentration region (25c).
c) The minority carrier current generated in the channel region (27) by impact ionization is transferred to the low concentration region by the so-called bipolar transistor operation formed by the channel region (27) (that is, the drift electric field at the Schottky junction is added). (25c) and metal layer (28)
It is possible to prevent the breakdown voltage between the source and drain from decreasing. At the same time, it is possible to make the element structure symmetrical, which improves reliability and the range of application as a circuit element.

Further, in the third invention, a Schottky junction is formed with the drain region (26) in the drain region (26) near the source of electron-hole pairs generated by impact ionization, and the Schottky junction is separated from the channel region (27). By providing a metal layer (2B) with a metal layer (2B) and setting the potential of this metal layer (28) to the source potential or a potential near it, the minority carrier current generated by impact ionization is transferred from the drain region (26) to the metal layer (2B). 28). Therefore, it is possible to maintain the advantages of the MISFET using the SOI substrate and prevent the source-drain breakdown voltage from decreasing.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. Although each embodiment is applied to an n-channel old 5FET, it goes without saying that it can also be applied to a p-channel old 5FET.

FIG. 1 shows an example of the invention. In this example, an SOI substrate (24) is used in which, for example, a silicon thin film (23) is formed on a silicon base 1 (21) with a silicon thin film (23) insulated and isolated through a SiO□ film (22). This Sol substrate (2
In the silicon thin film (23) of 4), which is made of p-type, a source region (25) and a drain region (26) of the first conductivity type, that is, n-type, are formed so as to reach the bottom SiO□ film (23). The source region (25) is formed outside the source region (25) within the silicon thin film (23).
) and is separated from the channel region (27). In this case, the metal layer (28) uses a so-called ohmic metal that makes ohmic contact with the source region (25). Metal layer (28) and channel region (27)
The distance (radius) W, 4 between the source regions (25) is the diffusion length of minority carriers or holes in the source regions (25),
Selected as smaller. For example, on the channel region (27) between the source region (25) and the drain region (26),
A gate electrode (30) made of, for example, polycrystalline silicon is formed via a gate insulating film (29) made of i(h) or the like.

The metal layer (28) also serves as a source electrode, and a drain electrode (32) is formed in the drain region (26) to form an n-channel bMIsFET (34).

2 to 4 show modifications of FIG. 1. In Figure 2, n
In this case, a shaped source region (25) and a drain region (26) are formed to reach the bottom SiO□ film (22), and a metal N (28) is formed in the n-type source region (25). be. In Figure 3, an n-type source region (2
5) and drain region (26) with the bottom 5iOz film (2
2), and this n-type source region (2) is formed to a depth that does not reach 2).
5) In this case, a metal layer (28) is formed inside. Furthermore, in FIG. 4, an n-type source region (25
This is a case where a metal layer (28) is formed in a part of the inside (28). In both cases, the metal layer (28) is an ohmic metal, and the distance WN of the source region (25) is selected to be smaller than the hole diffusion length LP.

Here, the holes of the electron-hole pairs generated by impact ionization are located in the source region (25).
Once inside, it flows towards the metal layer (28) by diffusion. Figure 8 shows the Hall current 1p flowing through the metal layer (28).
The dependence of the source region (25) on the distance (width) WN is shown. The curve (If) is the hole diffusion current, the curve (DI
) is the recombination current, and curve (1) is the effective Hall current I obtained as the sum of the diffusion current and the recombination current. The diffusion current is proportional to 1/WN and ■ as WN increases beyond the diffusion length Lp of minority carriers (i.e. holes in this case).

becomes constant (ie, the recombination current).

According to the MISFET (34) according to this example, the metal layer (28) is in ohmic contact with the source region (25).
is formed in the silicon thin film (23) to form a metal layer (28).
By making the distance MWN of the source region (25) between the channel region (27) and the channel region (27) smaller than the diffusion length LP of holes, which are minority carriers, the holes generated by impact ionization are transferred to the metal Jl! The Hall current (2) flowing toward (28) increases, and as a result, it is possible to suppress a decrease in source-train breakdown voltage due to impact ionization.

In the configurations shown in FIGS. 1 to 4 on the upper side, the metal layer (28
) can be arranged symmetrically in contact with the source region (25) side and the drain region (26) side. Figure 5 is 3
Terminal structure and LDD (Lightly dop)
An example of a (edrain) structure is shown below. This M l5F
In ET (38), the high concentration region (25a) (26a
) and low concentration regions (25b) (26b) respectively corresponding to the outside of the source region (25) and drain region (26).
Metal layers (28A) and (28B) are formed which are in ohmic contact with and separated from the channel region (27). Again, symmetrical source region (25) and drain region (
The effective distance WH of 26) is selected to be smaller than the diffusion length LP of holes, which are minority carriers. Then, this metal layer (2
8A) and (28B) serve as the source electrode and drain electrode, respectively. Here, for example, the gate electrode (30
), boron-doped polycrystalline silicon is used, the thickness d of the silicon thin film (23) is 800 mm, and the channel region (2
7) with an impurity concentration of about 1014 cm-3, and the low concentration regions (25b) and (26b) of the source and drain regions.
), the impurity concentration in the high concentration region (
25a) and (26a) to 10"c+r'
It can be done to a certain extent.

In this way, MISFET (3
4).

According to (35), (36), and (37), it is possible to suppress a decrease in source-drain breakdown voltage due to in-bust ionization. Then, the metal layer (28) is placed on the source region (25) side and the drain region (25) side.
Since it can be formed symmetrically to the 6) side, it can be used as a switching element such as an access transistor of a static RAM cell, and the range of application in circuit elements can be expanded.

In addition, the structure is simple as it is only necessary to form the metal layer (28) outside the source region or outside the source and drain regions, and manufacturing is also facilitated.

Moreover, the advantages of elements using SOI substrates such as small parasitic capacitance, high degree of freedom in setting the impurity concentration in the channel region (27), resistance to alpha rays, and resistance to latch-up are not lost.

FIG. 6 shows yet another example of the invention. In this example,
For example, a P-type silicon thin film (
23), there is a low concentration region (2) below the high concentration region (25a) and (26a) that reaches the bottom 5in2 film (22).
n-type source region (25) with (5c) and (26c)
) and drain region (26), and a high concentration region (25a) and a low concentration region (25) of this source region (25).
c) a metal layer (
28). At this time, ohmic contact occurs between the metal layer (28) and the high concentration region (25a),
A Schottky junction is formed between the metal layer (28) and the low concentration region (25c). Furthermore, the low concentration region (2) of the source region between the metal layer (28) and the channel region (27) is
The distance MWN in 5c) is selected to be smaller than the hole diffusion length.

And a source region (25) and a drain region (26)
A gate electrode (30) made of, for example, polycrystalline silicon is formed on the channel region (27) between them via a gate insulating film (29) made of SiO□, etc., and the metal layer (28) serves as a source electrode and also as a drain. A drain electrode (32) is formed in the high concentration region (26a) of the region (26) and the MIS
A FET (51) is configured.

In such a configuration, a low concentration region (25c) is formed in the source region (25), and a metal layer (28) forming a Schottky junction with the low concentration region (25c) is provided to form a channel region (25c). 27), source area (25
c) and the metal layer (28) correspond to the emitter, base, and collector and operate as a so-called bipolar transistor, and the hole current 1p flowing toward the metal layer (28) is further increased compared to the previous embodiment, resulting in an impact A decrease in source-drain breakdown voltage due to ionization can be further suppressed. That is, by forming the low concentration region (25c), the potential barrier to holes formed between it and the channel region (27) is reduced, and L P =
J Ren<D.

is the minority carrier diffusion coefficient and τ is the minority carrier lifetime) increases. Furthermore, since there is the recombination current explained in FIG. 8, as a result, in this example, the Hall current I9 increases in the region where W14 is small, as shown by the curve (IV) in FIG. 9. Furthermore, since a Schottky junction is formed between the metal layer (28) and the low concentration region (25c), holes are further drawn into the metal layer (28) by the drift electric field at the Schottky junction.1. The curve will shift upward as shown in curve (V) in FIG. That is, IP increases as the sum of diffusion current and drift current,
A decrease in source-drain breakdown voltage is further suppressed.

The above analysis is shown below.

Now, if the channel current of a MISFET using an SOI substrate is IC1, and the hole current generated in a high electric field is 17, and the electron current when the IP channel potential rises above the source potential and bipolar operation is 17, then the drain current ID is l D"' I. +1., +1. ・・・・
(1) becomes.

The hole current 1p generated by the channel current IC and the electron current I7 is expressed as 1p=K(Vo)(I,+J,,)...(
2).

Also, I p= S (q Dpn ;”/NDWPi)
(e kTl )...(3) IPl=S ((IDnn;"/NA'L)(e"-
1)...(4) However, D:: Diffusion coefficient of hole S: Junction area nl: Intrinsic carrier concentration N1: Donor concentration WN of source low concentration region (25c): Source low concentration region (25c) Width Do of 25c): Electron diffusion coefficient NA: Acceptor concentration L of channel region (27): Length of channel region (27) ■: Potential difference between the source and channel The equations (]) to (4) above are obtained.

Therefore, the concentration N of the low concentration region (25C) of the source region,
The smaller the width W8 is, the smaller the drain current ID becomes and the higher the source-drain breakdown voltage becomes.

Also in this configuration, it is possible to make it symmetrical with respect to the source region side and the drain region side as in the eleventh example, and the various advantages mentioned above of the element using the SOI substrate are not lost. It never happens.

FIG. 7 shows an example in which the source region side and the drain region side are symmetrical. In this example, P-type silicon thin film (23)
An n-type source region (25) and drain region (26) having high concentration regions (25a) and (26a) and low concentration regions (25b) and (26b) of LDD are formed in the regions, respectively. Low concentration regions (25
c) and (26c) are formed. Then, the low concentration regions (25c) and (26c) are formed in metal layers (28A) and (28B) that are in contact with the high concentration regions (25a) and (26a) and are separated from the channel region (27). At this time, ohmic contact is made between the metal layers (28A) and (28B) and the corresponding high concentration regions (25a) and (26a), and the metal layers (28A) and (28B)
A Schottky junction is formed between and the corresponding low concentration regions (25c) and (26c). These metal layers (28A) and (28B) are also used as a source electrode and a drain electrode.

Here, for example, phosphorus-doped polycrystalline silicon is used as the gate electrode (30), the thickness d of the silicon thin film (23) is about 1500, the impurity concentration of the 1P channel region (27) is about 10''c+r3, the source region and The impurity concentration of the high concentration regions (25a) and (26a) of the drain region is set to about 10zocnI-i, and the low concentration region of the LDD (2
5b) and (26b) as l Q I a
About Cl11-3, low concentration region (25c) and (26c
) can be set to about 1015 to 10"cm-'.

Since the source and drain can be formed symmetrically in this way, it can be used as a switching element such as an access transistor of a static RAM cell.

FIG. 11 shows still another example of the present invention, which will be explained together with its manufacturing method. In this example, as shown in FIG. 11A, a gate insulating film (29) such as SiO□ and a gate electrode (3o) made of polycrystalline silicon are formed on the silicon thin film (23) of the SOI substrate (24). In addition, low concentration regions (25b), (26b) and high concentration regions (25a)
).

An n-type source region (25) and drain region (26) each having an LDD structure (26a) are formed. The source region (25) and drain region (26) are formed with shallow junctions. Furthermore, the surfaces of the high concentration regions (25a) and (26a) of the source region and the drain region,
A silicide layer (41) of a refractory metal such as titanium silicide (TiSi2) is formed on the surface of the gate electrode (30).

Next, as shown in FIG. 11B, a glabellar insulating film (42) is formed, a window hole (43) facing the gate contact portion is formed, and then a photoresist mask (44) is formed as shown in FIG. 11C. window holes (45) and (46) are formed in the portions corresponding to the source and drain contact portions through the window holes (45) and (46). Grooves (47) and (48) are formed by selective etching to a depth reaching (22).

Next, as shown in Figure 11, a low concentration n-type impurity (49) is ion-implanted at a predetermined implantation angle to continuously form the lower part of the high concentration regions (25a) and (26b) of the source and drain regions. and reaches the bottom 5in2 membrane (22)n
The lowest concentration regions (25c) and (26c) are formed.

In this case, the width W of the low concentration regions (25c) and (26c)
1 (corresponding to WN) is formed sufficiently smaller than the minority carrier diffusion length LP (WN<Lp), and this width W is controlled by the implantation angle during ion implantation, implantation energy, and subsequent annealing treatment. It is possible to do so.

Next, as shown in Figure 11, grooves (47) and (48)
) is coated with a Ti film (53), which is a high melting point metal, for example, and is annealed to form the inner walls of the grooves (47) and (48), that is, the source region (25) and drain region (26), respectively. A titanium silicide (TiSiz) film (54) is formed on the surfaces of the high concentration regions (25a), (26a) and the low concentration regions (25c), (26c). The titanium silicide film (54) is a high concentration region (25a).

(26a) is in ohmic contact with the low concentration region (
A Schottky junction is formed between 25c) and (26c).

After that, as shown in Figure 11F, each groove (47)
and (48) and on the gate electrode (10) through a barrier metal such as a TiON film (55).
) and patterned to form a source electrode (31), a drain electrode (32), and a gate lead-out electrode (57) to obtain the desired MISFET (58). Here, a titanium silicide film (54), a barrier metal film (55)
) and AI film (56) to form a metal layer (28A) and (
28B) is configured.

According to the old 5FET (5B) with such a configuration, the diffusion length of minority carriers is sufficiently narrower than the diffusion length LP (W N < L p
) Since the n lowest concentration regions (25c) and (26c) can be provided, the hole current (2) flowing to the metal layer (28A) increases. At the same time, by forming a Schottky junction between the metal layer (28A) and the low concentration region (25c), in addition to the diffusion current, a drift current based on the electric field at the Schottky junction is generated, increasing . As a result, it is possible to further improve the source-drain breakdown voltage than in each of the embodiments described above.

Also, in the manufacturing method, it is possible to make the low concentration region (25c) very narrow, and the manufacturing process is simple, with only one additional step for forming the grooves (47) and (48). I can do it. By the way, metal layer (28A)
, (28B), as shown in FIG. 14, a configuration in which P shadow regions (61A) and (61B) are formed can also be expected to similarly improve drain breakdown voltage. However, in this configuration, a phosphorography process is required to form the narrow low concentration region (25c).

Ion implantation of (26c), p shadow region (618), (61
B) ion implantation, etc., requires a large number of steps and is difficult to form with high precision, making it difficult to manufacture in reality. On the other hand, if the manufacturing method shown in FIG. 11 according to this example is adopted, the narrow low concentration regions (25c) and (26c) can be formed easily and with high precision.

FIG. 12 shows a modification of FIG. 11. In this example,
As shown in FIG. 12A, the silicon thin film (23) of the 301 substrate (24) has a gate insulating film (29), a gate electrode (30) made of polycrystalline silicon, high concentration regions (25a) and (26a), and low concentration regions (25a) and (26a). An n-type source region (25) and a drain region (
26), and further, for example, a titanium silicide film (41) is formed on the entire surface of the source region (25), the train region (26), and the gate electrode (30), respectively.

Next, as shown in FIG. 12B, a glabellar insulating film (42) is formed, and a window hole (43) is formed through which the gate, source, and drain contacts of the glabellar insulating film (42) are exposed. 45) and (46) are formed simultaneously.

Next, as shown in FIG. 12C, a low concentration n-type impurity (49) is ionized at a predetermined implantation angle through window holes (45) and (46) through an ion implantation mask, such as a photoresist mask (44). N lowest concentration regions (25c) and (26c) are formed continuously below the high concentration regions (25a) and (26a) of the source and drain regions, reaching the bottom SiO□ film (22). . In this case, the width d2 of the low concentration regions (25c) and (26c) is
5) and (46), and the difference wr (corresponding to WN) can be controlled by the implantation angle during ion implantation, implantation energy, and subsequent annealing treatment.

Next, as shown in the 12th diagram, window holes (45) and (4)
6), for example, a Ti film (53
) is deposited and annealed to cause the reaction between titanium and silicon to reach the depth of the bottom SiO□ film (22), forming high concentration regions (25a), (26a) and low concentration regions (22).
25c).

A titanium silicide (TiSiz) film (54) is formed in contact with (26c).

Next, as shown in FIG. 12E, an unreacted Ti film (53
) and the photoresist mask (44), a barrier metal TiON film (55) and an M film (56) are formed and patterned to form a source electrode (31), a drain electrode (32) and a gate lead electrode ( 57) to obtain the target old 5FET (59).

Even in the old 5FET (59) with such a configuration, the diffusion length of the minority carriers formed a sufficiently narrow (W, (Lp)) low concentration region (25c), and the Schottky junction was formed by the titanium silicide film (54). are formed, and the drain breakdown voltage can be improved as in FIG. 11. Moreover, in FIG. 12, window holes (45) and (46) for source and drain contacts are formed.
Since the window hole (43) for the gate contact can be formed at the same time and there is no need to form the grooves (47) and (48), manufacturing is easier than in FIG. 11.

FIG. 13 shows yet another aspect of the invention. In this example, a high concentration n-type source region (25) is formed in a p-type silicon thin film (23) of a Sol substrate (24), and a high concentration source region (26c) facing the surface is formed in a low concentration region (26c). Area (26
a), and further includes a metal layer (28) on the outside of and in contact with the low concentration region (26c) of the drain region (26) and separated from the channel region (27).
form. This metal layer (28) and the low concentration region (26c)
) forms a Schottky junction. In addition, the metal layer (
28) and the drain region (2) between the channel region (27)
The distance WN in 6c) is the diffusion length L of holes, which are minority carriers.
Select a value smaller than P. Then, S is placed on the channel region (27) between the source region (25) and the train region (26).
A gate electrode (30) made of, for example, polycrystalline silicon is formed through a gate insulating film (29) made of iO□ or the like, and a source electrode (31) and a train electrode (31) are formed in the source region (25) and drain region (26), respectively. 32) to form M
15FET (60) is formed. Here, the metal layer (2
The potential of 8) needs to be set to the source potential or a potential near it. That is, the potential of the metal layer (28) needs to be lower than the potential of the channel region.

According to the MrSFET (60) having such a configuration, the drain region (26) is located on the side of the drain region (26) that is close to the source of generation of electron-hole pairs due to impact ionization.
By forming the metal layer (28) that forms a Schottky junction with the
Holes generated by ionization can be released through the drain region (26) and the metal layer (28), making it possible to improve the source-drain breakdown voltage.

〔Effect of the invention〕

According to the present invention, MIS formed using a Sol substrate
without sacrificing the advantages of type semiconductor devices.
A decrease in breakdown voltage due to ionization can be suppressed, and the reliability of the MIS semiconductor device itself can be improved. In addition, it is possible to use the device as a normal three-terminal device, and it is also possible to form the source and drain sides symmetrically, thereby widening the range of applications as a circuit device.

[Brief explanation of drawings]

FIGS. 1 to 7 are configuration diagrams showing embodiments of the MTSFET according to the present invention, FIGS. 8 to 10 are characteristic diagrams for explaining the present invention, and FIGS. 11 and 12 are respectively according to the present invention. Cross-sectional views in the order of manufacturing steps showing other examples of MISFET,
FIG. 13 is a configuration diagram showing still another embodiment of the MISFET according to the present invention, and FIG. 14 is a MISFET for explaining the present invention.
FET configuration diagram, Figures 15 to 17 are the conventional old 5FET
18 and 19 are block diagrams of proposed examples. (21) is a silicon substrate, (22) is an insulating film, (23)
is a silicon thin film, (24) is a Sol substrate, (25) is a source region, (26) is a drain region, (28) C (2
8A) (28B) ) is a metal layer, and (30) is a gate electrode.

Claims (1)

[Claims] 1. An MI in which a semiconductor layer is formed on an insulating substrate, and a gate electrode is formed on the semiconductor layer with a gate insulating film interposed therebetween.
An MIS type semiconductor device, which is an S type semiconductor device, and has a metal layer in contact with a source region and separated from a channel region. 2. In an MIS type semiconductor device in which a semiconductor layer is formed on an insulating substrate and a gate electrode is formed on the semiconductor layer via a gate insulating film, the source region has a high concentration region and a low concentration region below it. A MIS type semiconductor device comprising: a metal layer that is in contact with a low concentration region and a high concentration region of the source region and is separated from a channel region. 3. MI in which a semiconductor layer is formed on an insulating substrate, and a gate electrode is formed on the semiconductor layer with a gate insulating film interposed therebetween.
An MIS type semiconductor device comprising a metal layer forming a shot junction in contact with a drain region and separated from a channel region in an S type semiconductor device.