JPH0467246A - Read/write system for semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten the access time by connecting a timer to a preference control part and ending forcibly an access when a timer has a time-up state. CONSTITUTION:When a timer 8 is set in a time-over state after a set time, the timer 8 outputs an access end signal to a preference control part 6 to instruct the forcible end of an access. The part 6 receives the access end signal and ends the access given from a 1st CPU 1, for example, and transfers the access right to a 2nd CPU 2 if an access signal Sb is outputted from the CPU 2. The timer 8 starts again its counting action after the access right is received by the CPU 2. However, the set time of the timer 8 is slightly longer than the time during which both data write/read operations of both CPU 1 and 2 are through to a semiconductor memory 7.

Description

[Detailed Description of the Invention] Overview Regarding a read/write method for a semiconductor memory, an object of the present invention is to provide a read/write method for a semiconductor memory that can read/write data quickly by shortening access time. , the priority control unit detects each access signal output from the first CPU and the second CPU via each bus line, and detects each access signal output from the first CPU and the second CPU to which the previously detected access signal was output.
In a semiconductor memory read/write method in which a CPU that has obtained the access right accesses the semiconductor memory, the priority control section is provided with a timer that times out at an arbitrary set time. connection, and when the timer times up, the access is forcibly terminated.

INDUSTRIAL APPLICATION FIELD The present invention relates to a system with multiple CPUs and multiple bus structures, which has been developed in response to demands for parallel processing and faster speed of semiconductor memory read/write computer systems. multiple C
Methods that are commonly used in PU are becoming more prominent.

Also, how can such a system process data at high speed? It is necessary to efficiently perform the read/write competition to the semiconductor memory, which is frequently performed by the Il number of CPUs, and it is desired to perform the read/write competition efficiently.

BACKGROUND OF THE INVENTION FIG. 6 is a diagram illustrating a conventional semiconductor memory glue read/write method.

In this figure, 1 is the first CPU, 2 is the 20th PU, 3 is the 20th PU,
, 4.5 is a bus line, 6 is a priority control unit, and 7 is a semiconductor memory (RAM: Random Access).
Mem.

ry). The priority control unit 6 gives access rights to the CPU 1 or 2 when each CPU 1 or 2 accesses the semiconductor memory 7 (read/write data).

This is because the access signal Sa is output from the first CPU 1 to the priority control unit 6 via the bus line 3, and the second
For example, when the access signal sb is output from the CPU 2 to the priority control unit 6 via the bus line 4, suppose that the first access signal Sal of the CPUI is output to the priority control unit 6 first, as shown in FIG. , the priority control unit 6 is a CPU
is granted access rights to the semiconductor memory 7. As a result, if the access signal Sal is a write command, the first C
Data is written from the PU 1 to the semiconductor memory 7, and if the access signal Sal is a read command, data is read from the semiconductor memory 7 to the first CPU 1.

Then, when the access signal Sal is avoided, the priority control unit 6 detects the first access signal Sbl from the CPU 2 and transfers the access right to the second CPU 2 i.

As a result, data is written from the second CPU 2 to the semiconductor memory 7, or from the semiconductor memory 7 to the second CPU 2.
Data is read out to CPU2. Thereafter, through similar operations, the access right is transferred to the CPUI or 2, and data writing/reading (reading/writing) is performed.

Problems to be Solved by the Invention By the way, in the read/write method of the semiconductor memory described above, the output time Ta or Tb (see FIG. 7) of the access signal S, a or sb output from the CPU I or 2 is actually If the data read/write time is longer than the access time, the next operation cannot be performed until the access signal is avoided. For example, if the CPU 1 has the access right, even if the writing of data from the CPU to the semiconductor memory 7 is completed, unless the access signal Sa is avoided, the CPU 2 will still have the access right. It will be in a waiting state and cannot be accessed.

In addition, in the case of such control, as shown in FIG. 7, for example, the data Dal, Dbl, Da2 (7) 7 access time T is the sum of the output times Ta, Tb, Ta of the access signals Sal, Sbl, Sa2 (Ta+Tb+Ta). This is a longer time than the time it takes to actually read/write data.

Therefore, in the above-described semiconductor memory read/write method, the access time becomes long, resulting in a problem that data reading/writing becomes slow.

The present invention has been made in view of these points,
It is an object of the present invention to provide a semiconductor memory read/write method that can read/write data quickly by shortening access time.

It's meant to be remembered.

Takoma's means of solving problems FIG. 1 is a diagram showing the principle of the present invention.

According to the present invention, each access signal Sa and sb output from the first CPUI and the second CPU 2 is manually inputted to the priority control unit 6 via each bus line 3.4, and the priority control unit 6
detects the previously input access signal Sa or sb, and also detects the detected access signal Sa or sb.
The CPU I or 2 that outputs b is given access rights to the semiconductor memory 7, and the CPU I or 2 that has obtained this access access accesses the semiconductor memory 7, but it is connected to the priority control unit 6 and the timer 8 is set to When the time-up occurs at time Tt, the access is forcibly terminated.

Further, an auxiliary buffer 9 for storing data in the semiconductor memory 7 is provided, and when the above-described access is forcibly terminated due to time-up of the timer 7, predetermined data in the semiconductor memory 7 is applied to the auxiliary buffer 9. The set time Tt of the timer 8 is set to a time slightly longer than the time during which data is written into the semiconductor memory 7 or the time during which data is read from the semiconductor memory 7. As shown in FIG. 2, for example, if the first access signal Sal from the first CPUI is first input to the priority control unit 6, the first CPUI is given access rights and data Dal is stored in the semiconductor memory 7.
or write data Da1 from the semiconductor memory 7.
At the same time, the timer 8 starts counting.

Then, when the timer 8 exceeds the set time Tt, the timer 8 times up and the access is forcibly terminated, but the writing or reading of data has already been completed.

Further, when the access is forcibly terminated, the priority control unit 6 detects the access signal Sb1 and transfers the access right to the second CP.
Transfer to tJ 2.

This gives access rights to the second CPU 2,
Data Dbl is written or read.

At this time, timer 8 starts counting. Similarly, when the timer 8 times up, the access ends and data Da2 is then written or read.

Therefore, the access time is approximately the same as the actual data writing or reading time, and is therefore shorter than the conventional access time depending on the access signals Sa and Sb. That is, data reading/writing can be made faster.

Additionally, when the timer 8 times up while reading data and the access ends, the data being read out is stored from the semiconductor memory 7 to the auxiliary buffer 9, and the readout of this stored data to the CPU is subject to transfer of access rights. This is done in parallel with reading by other CPUs 2. In other words, data can be read/written efficiently.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a diagram for explaining a read/write method of a semiconductor memory according to an embodiment of the present invention, and in this figure, parts corresponding to those of the conventional example shown in FIG. 6 are given the same reference numerals. However, the explanation thereof will be omitted.

In this figure, 1 is the first cPU, 2 is the second CPU, 3
．． 4, 5, 11 are bus lines, 6 is a priority control unit, 7 is a semiconductor memory, 8 is a timer, 9 is a first auxiliary buffer, 1
0 is the second auxiliary buffer.

The timer 8 outputs an access termination signal S1 instructing the priority control unit 6 to forcibly terminate the access when the set time elapses and the time is over. The priority control unit 6 to which this access end signal S1 is inputted, for example,
Access from the PUI is terminated, and at this time, the second CPU
If the access signal sb is output from the second CPU 2, the access right is transferred to the second CPU 2. When the access right is transferred, the timer 8 starts counting again. However, timer 8
The set time is set to a time slightly longer than the time required for data writing or data reading from each CPUI 2 to the semiconductor memory 7 to be completed.

The first and second auxiliary buffers 9.10 are the semiconductor memory 7.
This is to temporarily store the data read from the memory. For example, when data is being read from the semiconductor memory 7 to the CPUI, if the access is forcibly terminated by the timer 8 and the access right is transferred to the second CPU 2, the data being read is transferred to the first auxiliary buffer 9. Once it is memorized.

In such a configuration, first, each CPUI.

2, the case where data is written to the semiconductor memory 7 will be explained.

In this case, if the access signal Sal is first output from the first CPUI as shown in FIG.
The priority control unit 6 receives the data Dal and gives access rights to the first CPU 1, and the first CPU 1 stores the data Dal in the semiconductor memory 7.
Start writing. Furthermore, at this time, timer 8 starts counting.

Then, when the timer 8 finishes counting the set time Tt, time-up occurs, and the access end signal S1 is input to the priority control section 6. Priority control unit 6 to which signal S1 is input
will forcibly terminate access from the first CPUI and
The access right is transferred to the second CPU 2 by the access signal Sbl output from the CPU 2. As a result, the second CPU 2 starts writing the data Dbl into the semiconductor memory 7.

In the same way, access is forcibly terminated every time the data Da2. Writing of Db2 is performed.

According to such a data write method (write method), the access time is approximately the same time as the actual write time of the data Dal to Db2, that is, the set time Tt of the timer 8. As shown, the access time that conventionally took up to T1 can be reduced to the total time Ttl of each set time Tt. That is, unlike the conventional example, the access time does not depend on the access signals Sa and Sb, so data can be written faster than in the conventional example.

Next, the case where data is read from the semiconductor memory 7 to each CPU 1.2 will be explained.

In this case, first, as shown in FIG.
If an access signal Sal is output from the first CPU 1, the priority control unit 6 receives this signal Sal, gives the access right to the first CPU 1, starts reading the data Dal from the semiconductor memory 7 to the first CPU 1, and starts the timer. 8
counting starts.

When the timer 8 times out, an access end signal S1 is input to the priority control section 6.

The priority control unit 6 to which the signal S1 has been input forcibly terminates the access from the first CPU 1, and terminates the access from the second CPU 1. The access right is transferred to 12cPU2 by the access signal Sbl output from CPU2. This starts reading the data Dal from the semiconductor memory 7 to the first CPUI.

In the same way, access is forcibly terminated every time the data Da2. D, b2 is read.

By the way, for example, the data read from the semiconductor memory 7 has a longer data length than the data Dal to Db2 described above, and the access is forcibly terminated due to a time-up while the long data is being read. In this case, data that is being read from the semiconductor memory 7 is temporarily stored in the auxiliary buffer 9 or 10. and,
This stored data is read out in parallel with reading out other data.

For example, as shown in FIG.
If the access is forcibly terminated due to a time-up while the data Da 1' is being read into the PUI, the data Dala' that is being read from the semiconductor memory 7 is stored in the first auxiliary buffer 9 . And this first
Data Dala' stored in the auxiliary buffer 9 is continuously read out by the first CPUI. Also, in parallel with this reading, data Db is read from the semiconductor memory 7.
The reading of l' is performed by the second CPU 2.

Thereafter, data Dblb' is stored in the second auxiliary buffer 10 in the same manner, and data Da2' is read out in parallel with reading out the stored data Dblb', and furthermore, data Da2a' is read out. The data Db2' is stored in the first auxiliary buffer 9, and the data Db2' is read out in parallel with the readout of the data Da2a'.

According to the data reading method (reading method) as described above, the data Dal ~
Db2 can be read.

Further, even if the data Da1' to Db2' have a longer data length than the data Dal to Db2, the data that is being read out is temporarily stored in the auxiliary buffer 9 or 10.
This stored data and other data in the semiconductor memory 7 can be read out in parallel. That is, in either case, data can be read out more efficiently and faster than in the past.

As described in detail, according to the present invention, the access time can be shortened, and therefore data can be read/written quickly.

Furthermore, since each CPU can read different data from both the auxiliary buffer and the semiconductor memory in parallel, there is an effect that data can be read/written efficiently.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a diagram for explaining the access operation in the configuration shown in FIG. 1. FIG. 3 is a diagram explaining the read/write method of a semiconductor memory according to an embodiment of the present invention. Figure 4 is a diagram for explaining the write operation in the configuration shown in Figure 3, Figure 5 is a diagram for explaining the read operation in the configuration shown in Figure 3, and Figure 6 is a diagram for explaining the conventional FIG. 7 is a diagram for explaining the read/write method of the semiconductor memory of FIG. 7, and is a diagram for explaining the access operation in the configuration shown in FIG. 1... 1st CPU. 2...Second CPU. 3.4... Bus line, 6... Priority control unit, 7... Semiconductor memory, 8... Timer 9... Auxiliary buffer, Sa, Sb... Access signal.

Claims (1)

[Claims] 1. Each access signal (Sa and Sb) output by the priority control unit (6) from the first CPU (1) and the second CPU (2) via each bus line (3 and 4) At the same time as detecting the previously detected access signal (Sa or Sb)
is output to the CPU (1 or 2), and the semiconductor memory (7
), and the CPU that obtained the access right (
In the read/write method of the semiconductor memory (7) in which 1 or 2) accesses the semiconductor memory (7), a timer (8) that times out at an arbitrary set time is connected to the priority control section (6). A read/write method for a semiconductor memory, characterized in that the access is forcibly terminated when the timer (8) times out. 2. An auxiliary buffer (9) is provided for storing data in the semiconductor memory (7), and when the access is forcibly terminated by the time-up of the timer (8), predetermined data in the semiconductor memory (7) is stored in the corresponding memory. 2. A read/write method for a semiconductor memory according to claim 1, wherein the data is stored in an auxiliary buffer (9).