JPH0464977A - Efm modulator - Google Patents

Abstract

PURPOSE:To prevent an influence of fluctuation of DSV for reproducing of digital data recorded on a CD by generating such one-bit error in channel bits for detection based on a detection signal by an error generating circuit that the absolute value of the value of DSV most aproximates 0. CONSTITUTION:On condition that the frequency in continuous monotonous change of the value of DSV with a channel bit as the unit does not exceed a certain value and the value of DSV does not exceed a certain level value, one-bit error is generated per channel bit. Thus, reproducable data can be supplied to the CD though unreproducable data is inputted to this EFM modulator.

Description

[Detailed description of the invention] "Industrial field of application" This invention is an E F M used for modulating digital data recorded on a compact disc (CD).
(Eight to Fourteen Mod
ulation) modulator.

“Prior art” Digital data modulation methods include rεFM and NRZ.
There are various methods, such as N on Return to Z cro (N on Return to Z cro) and P E (Phase Encoding).

These modulation methods are basically: ■High-density recording possible ■Self-chloragging is possible ■DC component must be as small as possible It is necessary to satisfy the following conditions.

In addition to the above-mentioned conditions ■ to ■, ■ Since the clock can be extracted stably, the maximum inversion interval Tll1aX is small. ■ Since the frequency characteristics are limited, the minimum inversion interval T m
1 It is necessary to satisfy important conditions such as large n, large window width Tw, and short constraint length.

The EPM modulation method, which is a modulation method for digital data recorded on a CD, is a very clever modulation method that satisfies two conditions.

The EF'M modulation method will be explained below. The EFM modulation method converts 8-bit data into a pattern consisting of 14 channel bits. In this case, it is necessary to select 28 patterns out of 214 patterns. This is a ROM (Re
ad Only Memory). However, in order to satisfy the conditions of ■ and ■ mentioned above, "there are at least two 0s between any two 1s, and
It is necessary to satisfy the principle that 11 or more] - cannot continue.

By the way, even if you convert 8-bit data into a 14-bit pattern and make sure that there are at least two 0's between ■ and 1 in order to add the "double principle", even between each data In order to satisfy this principle, at least two margin hits are required for combining 14-bit patterns. This is to take into account the case where the previous 14-bit pattern ends with 1 and the next pattern begins with 1. Note that in the EPM modulation method, 3 bits are allocated to margin hits.

This is to satisfy the condition (2) mentioned above, that is, the condition to reduce the DC component of the data itself.

Additionally, in general, D S is used to evaluate the DC component of data.
A value of V (D 1g1tal S um V alue) is used. This DSV has a high level of +1
, the bits are summed with the low level set to -1.

In order to satisfy the condition (2) mentioned above, the three margin pitches (1) and (1) must be selected so as to make the value of I) SV as small as possible.

Here, a typical algorithm for pre-reading one channel bit of the EFM modulation method to determine margin bits will be explained with reference to FIGS. 12 to 14. As shown in FIG. 12, channel bit 1 is...00100100
and the DSV value dsvb in the last bit is 1.
3. Code sig representing increase/decrease in DSV in the final bit
nb is “10”, number of zeros at the end of channel bit 1 Z b
is 2, and the next channel bit 2 is 00001000
If it is 010010, first, channel
The value of DSV in the last bit of 2 is 0, as shown in FIG.

Next, among the margin bits that combine channel pit 1 and channel bit 2, there are four types of margin bits that satisfy the above-mentioned original condition.

iii) 010 iv) +00 And channel pick l-1 and 1) to iv) mentioned above
The value of DS■ at the final bit of each margin bit when the margin bits of 2 are combined is as shown in FIG.

Then, since the DSV value in the last bit of only channel bit 2 is 0, as shown in the double row, channel bit l-1 and channel bit bit 2 are
The DSV values at the final bit of channel bit 2 when combined by the margin bits of v) are as shown below.

iii) +2 iv) 10 Therefore, among the margin bits of 1) to iv) mentioned above,
The margin bit that minimizes the DSV value in the final bit of channel bit 2 when channel bit 1 and channel bit 2 are combined is 1v)100, so this is selected as the margin bit I. .

In this case, (
−) DSV value dsvn = IO, channel voltage
The code 5 represents the increase/decrease in DSV in the final bit of Soto 2.
1gnn-”+”, number Z of trailing 0s of channel bit 2
n=1.

Next, according to the procedure described above, the margin bit I. which connects channel bit 2 and the next channel bit is selected, and similarly, margin bits are selected one after another.

"Problems to be Solved by the Invention" By the way, in the conventional EFM modulation mentioned above, the EFM
When selecting the margin bit after M modulation, the margin pit cannot be selected between '000' and 2.16.
There are bits of special data.

For example, 16-bit data "F99A" 1, 6 . teeth,
When converted to a pattern consisting of 14 channel bits with 8 pins using the ROM described above, the 15th
As shown in the figure, due to the double principle, the margin pit can only be selected as ``ooo''.

In addition, the margin pick) is "000", 2. As shown in FIG. 16, the 16-bit data , including the 3 hits of the margin pitch I, cannot continue more than 0 or 5 times. Of the 16-bit data used for CDs, the first
The 16-bint data in which the pattern in Figure 6 appears is approximately 8
There are 00 types.

Therefore, when special data such as ``double'' is consecutive,
In the data portion within the frame composed of 32 channel bits, the DSV changes monotonically. Note that the DSV changes arbitrarily in the parity portion within the frame. Furthermore, if this special data continues beyond a certain level (for example, 600 data in 50 frames of 16-bit data), interleaving will occur (even if J is applied, I)
SV shakes. That is, as shown in FIG. 17, one peak changes in one frame, and this is the period of 7.
The spectrum of the signal at 35 kHz, I-1z (curve a) or 37 kHz (curve b) with twice the period becomes larger.

By the way, as shown in Fig. 18, the focus band of the CD player and the racking band are
The OdB gain is often set near kI-1z, and the frequency band below IOkI-fz is very important as a servo band and is easily affected by disturbances.

As a result, when a CD on which the above-mentioned EFM-modulated digital data is recorded is played back on a CD player, the tracking servo oscillates due to the above-mentioned 80SV fluctuation, causing the tracking servo to become disconnected. Track jumps occur, making it impossible to read data normally from the CD.

This invention was made in view of two consecutive circumstances.
An object of the present invention is to provide an EPM modulator that is less susceptible to DSV fluctuations even when a D player reproduces digital data recorded on a CD.

"Rounding Means to Solve the Problem" This invention provides an EPM modulator that modulates digital data recorded on a compact disc, in which the number of consecutive monotonous increases or monotonous decreases in the value of DSV in channel bit units. A monotonic change counting circuit or DS that counts
an absolute value counting circuit that counts the absolute value of the value of V; and a first detection signal indicating that the counted value of the monotonous change counting circuit exceeds a preset constant value or the counted value of the absolute value counting circuit. or a second value indicating that the preset value has been exceeded.
a detection circuit that outputs a detection signal, and a detection circuit that outputs a detection signal of 1 bit such that the absolute value of the DSV value approaches O most to the channel bit at the time of detection based on the first detection signal or the second detection signal. It is characterized by comprising an error generation circuit that generates an error.

"Operation" According to the present invention, when the first detection signal or the second detection signal is output from the detection circuit, the error generating circuit generates a detection signal based on the first detection signal or the second detection signal. If the absolute value of the DSV value is closest to 0 for the channel bit of
] will cause a one-hit error like this.

"Embodiment" Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an EFM modulator according to an embodiment of the present invention. In this figure, 1 is a data bit latch circuit that temporarily holds data bits that have been subjected to error correction processing, etc.; 14 data for 8 pits
an E FM conversion circuit for converting bits into channel bits;
Reference numeral 3 denotes an output data bit generation circuit that combines channel bits converted from pig pits using margin bits to generate output data bits.

Further, 4 is a monotonous change counting circuit that counts the number of monotonous increases and decreases (Signc), which is the number of consecutive monotonous increases or decreases in the DSV value in each channel pit, and 5 is an absolute value counter that counts the absolute value Idsvi of the DSV value. A circuit 6 detects that the count value of the monotonous change counting circuit 4 exceeds a certain value (for example, 7) or that the count value of the absolute value counting circuit 5 exceeds a certain value (for example, 40). a detection circuit that outputs a detection signal based on the detection signal;
This is an error generation circuit that generates a 1-bit error such that the absolute value 1dsvl of the DSV value is closest to 0 (=I).

In such a configuration, the operation of this EFM modulator will be explained based on flowchart 1 in FIG. 2.

First, as shown in FIG. 3, the case where the absolute value of I) SV is large will be explained. As a result of selecting the margin bit to be combined with the previous channel bit, channel pit 1 becomes...000000100 as shown in Figure 4.
Ends with 1, dsvb is 35, signb is --”, s
DSV with igncb 3, Zb 0, channel bit 1
After a certain data bit is temporarily held in the data bit latch circuit 1, when the sign s i z n f +) representing the magnitude between the value of In the EPM conversion circuit 2, +00
When converted into channel bit 2 of 10000000001, the EFM modulator proceeds to step S1, and in the output data bit generation circuit 3, margin pit 000 is generated based on the principle described above. At this time,
The monotone change counting circuit 4 counts signcn=4 when channel bits 1 and 2 are combined by the margin bit 1-000, and the absolute value counting circuit 5 counts the same <1dsvnl=44. In addition, 51gnn-"10" Zn=0 and signfn-"10' are found in the last bit of channel bit 2. Then, the EPM modulator performs step S2.
Proceed to.

In step S2, the detection circuit 6 determines whether 1dsvnl>40 or sign
It is determined whether cn>7. This judgment result is r
In the case of NOJ, the process returns to step S1.

On the other hand, if the determination result in step S2 is rYEsJ, the process advances to step S3. In this case, )dsvn44>4
Since it is 0, after the detection circuit 6 outputs the detection signal, the process advances to step S3.

In step S3, it is determined whether the data is a synchronization signal or a subcode, and the result of this determination is rYES.
In the case of j, the process returns to step S1.

On the other hand, if the determination result in step S3 is rNOJ, that is, if the data is neither a synchronization signal nor a subcode,
Proceed to step S4.

In step S4, the margin bit and channel bit 2 are
After assigning I to the variable {circle around (1)} which advances from the first bit to the lower bit of the 17 bits obtained by adding , the process advances to step S5.

In step S5, the corresponding person is changed. That is, if that bit is 1, change it to O, and that bit is 0.
If so, change it to 1. Specifically, the error generation circuit 7 changes the margin bit temporarily held in the output data bit generation circuit 3 and the corresponding bit of the channel pit 2 based on the detection signal. In this case, after changing the value 0 of the first bit ■ of the margin bits to 1, the process proceeds to step S6.

In step S6, it is determined whether the data violates the principles mentioned above. In this case, channel pit 1
The last bit of is 1, and the first bit of the margin bit is 1, so there are "at least two 0's"
This would violate the principle, and the judgment result would be rYES.
Becomes I. In this case, the process advances to step S7.

In step S7, the bits changed in the process of step S6 are restored. In this case, after returning the value l of the first hit ■ of the margin hits to O, the process advances to step S8.

In step S8, after adding I to the variable I, the process returns to step S5.

On the other hand, if the judgment result in step S6 is "NO", that is, if the data does not violate the principles stated in -,
Proceed to step S9.

In step S9, it is determined whether 1(]5Vnlk at the final bit O when combining the margin bits whose bits were changed in the process of step S5 and channel bits 1-2 is smaller than 1dSVnln++.

In this process, first, in the absolute value counting circuit 5, 1dsvnlh is counted when the combination of the margin bit and channel bit 2 whose bits were changed in the process of step S5 is combined with channel bit 1.

On the other hand, 1dsvnl, . . . +n are stored in a register (not shown). Then, add that value to 1-1dsvn1. ,
Compare with. In addition, in the case of K=1, 1d is stored in the register.
svn l m I. The value counted by the absolute value counting circuit 5 in the process of step S1, in this case, 1 dSv
Store n1□ and n44. And step S9
If the determination result is rNOJ, the process advances to step S7.

- On the other hand, if the determination result in step S9 is r\Esj, the process advances to step SIO.

In step Sho, after storing l dsvn l + in the register as IdS■n1□+In, the process advances to step S11.

In step Sl+, it is determined whether the variable 1 is equal to 17, that is, whether or not the last bit of channel hit 2 has been changed. If the result of this determination is rNOI, the process advances to step S7.

On the other hand, if the determination result in step S11 is rY E S J, the process advances to step SI2.

In step S+2, 1dSVn stored in the register
Change the bit corresponding to l+nln. in particular,
In the error generation circuit 7, the corresponding bits of the margin bit and the channel bit 2 temporarily held in the output data bit generation circuit 3 are changed. Then, the process advances to step SI3.

In step SI3, after setting signcn to 1, the process returns to step S1.

By performing the above-described processing on variables = I to I7, the bits from ■ to O in Figure 4 are changed one after another, and the combination of the changed margin bit and channel bit 2 is made into channel bit 1. Find the minimum value of 1dsvnlk when combined. However, cases in which the bit change violates the original 11J mentioned above must be excluded. Fourth
In the illustrated example, six types of bits, ■ and [phase] to ■, can be changed. Here, the values of 1dSvn1 in each case are shown below in FIG.

As can be seen from Figure 5, in the case of ■ and [phase]] dSv
Both nl are 32, which is the minimum, but we will adopt the [phase] in which the DSV value fluctuates in a short period of time.

As a result, the combination of the margin bit and channel pin l-2 is changed as shown in FIG. At this time, ds
vn=32.51gnn=”-” and sign
cnI.

Next, a case where the DSV value continues to monotonically change will be described. As a result of the selection of the margin hit that combines with the previous channel bit, channel bit 1 becomes... + 00 (l I (], ending with d
s v b is 20, signb is “10”, signcb
is 7, zb is I, and signfb is
When converted to channel bit 2 of 000001001, the EF'M modulator proceeds to step S+ in FIG. do. At this time, in the monotone change counting circuit 4, the channel bit 2
signcn=8, in the absolute value counting circuit 5,
Count 1dsvnl=25 of channel hit 2, respectively. Yota, channel hit □2's 51gnn-
"10" Find Zn=O and signfn-"10". The 81M modulator then proceeds to step S2.

In step S2, the detection circuit 6 determines that 1dsvnI>40 or sign
It is determined whether cn>7. This judgment result is r
In the case of NOJ, the process returns to step S1.

On the other hand, if the determination result in step S2 is rY E S J, the process advances to step S3. In this case, signcn
Since 8>7, after outputting the detection signal, step S
Proceed to step 3.

Incidentally, the processing in steps 83 to SI3 is performed using two consecutive DSVs.
Since the process is similar to the process when the absolute value of is large, the explanation thereof will be omitted.

By performing the processing described above for variables = I to I7, the bits from ■ to O in Figure 7 are changed one after another,
1dsvnL when the combination of the changed margin hit and channel bit 2 is combined with channel bit 1,
Find the minimum value of . However, this must be excluded in cases where the bit change violates the ``double principle''. In the example of Fig. 7, the 5 of ■, ■, [phase], ('f and
Type bits can be changed. Here, the values of 1dsvnl in each case are shown below in FIG.

As can be seen from Figure 8, in the case of ■, 1dsvnl is 15, which is the minimum, so we decided to adopt ■.
reactor. As a result, the margin bit and the channel hino l-2
The connection with . . . should be changed as shown in FIG. 9. At this time,
dsvn=15.51gnn=-” and Sg
ncn = ].

Here, an example will be explained in which an error is given three times within one frame. Before giving an error, the change in DSV is large, as shown by the broken line a in FIG. 10, and the change in DSV is large, as shown by the broken line a in FIG.
, a steep spectrum stands at 7 kHz.

However, by giving an error, as shown by the solid line in FIG. 10, there is a small change in SV, and as shown in the solid line l in FIG.
It is interesting that the DSV spectrum has shifted to the high frequency side of l-1z.

By the way, CDs have an error correction code called CIRC. Therefore, this error correction code can also correct the error signal given by this 81M modulator.

As explained above, the DSV value does not change monotonically for each channel pit for more than a number of times (for example, 7 times).
Alternatively, within the range where the two conditions that the DSV value does not exceed a certain level value (for example, 40) are met, ■
Since one bit error is generated per channel pit, even if unreproducible data is input to this El''M modulator, reproducible data can be supplied to the CD.

"Effects of the Invention" As explained above, the present invention has the effect of suppressing the low frequency spectrum of DSV.

Therefore, even if a CD player reproduces data from a CD on which data modulated by the 81M modulator is recorded, it is less likely to be affected by DSV fluctuation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an 81M modulator according to an embodiment of the invention, FIG. 2 is a flowchart showing the operation of the 81M modulator according to an embodiment of the invention, and FIG.
) A diagram showing temporal changes in SV, Figure 4 shows channel bit 1 and channel bit 2 when the absolute value of DSV is large.
5th hit is not shown in Figure 4; Figure 6 shows the value of 1dsvn when changing each bit of ■ and [phase] to ■. Figure 6 is the figure shown in Figure 4. Figure 7 shows an example of channel bit l-1, channel bit 2, and margin bit when the DSV value changes monotonically. Figure 8 is a diagram showing the value of l+1svn1 when changing the bits ■, ■, [phase] ■ and ■, which are not shown in Figure 7. Figure 9 shows the value of l+1svn1 when the bits ■ in Figure 7 are changed. FIG. 10, which is a diagram combining the margin bit and channel bit 2 when changed, shows an example of the frequency characteristics of the DSV before and after an error is added to the data by the EPM modulator according to an embodiment of the present invention. FIG. 11 shows an E FM modulator according to an embodiment of the present invention. Figure 12 shows an example of the DSV spectrum before and after adding an error to the data.
and channel bit 2.
Fig. 2 shows the DSV value of only the channel bit 2; Fig. 14 shows the DSV value when four margin hits are combined with the channel bit = 2 of Fig. 12; Fig. 15 The figure shows the case where special I6 bit data is converted to channel bits 1 and channel bits) and 2. Figure 16 shows the case where special data is converted to margin hill l□ooO+2+
Figure 17 is a diagram showing the frequency characteristics of DSV when special data is converted into channel bits, and Figure 18 is a diagram showing the servo band and DSV of a CD player.
FIG. 2 is a diagram showing the relationship between the SV frequency and the frequency band of the signal recorded on the CD.・Data bit latch circuit, 2. EFM conversion circuit, 3. Output data bisoto generation circuit, 4. Monotonous change counting circuit, 5. ・Absolute value counting circuit, 6. Detection circuit, 7. Error generation circuit.

Claims (1)

[Claims] In an EFM modulator that modulates digital data recorded on a compact disc, there is a monotonous change counting circuit or DSV that counts the number of consecutive monotonous increases or decreases in the DSV value in channel bit units. an absolute value counting circuit that counts the absolute value of a value; and a first detection signal indicating that the count value of the monotonous change counting circuit exceeds a preset constant value, or a count value of the absolute value counting circuit that is detected in advance. a detection circuit that outputs a second detection signal indicating that a predetermined value has been exceeded; and a detection circuit that outputs a second detection signal indicating that a predetermined value has been exceeded; An EFM modulator comprising: an error generation circuit that generates a 1-bit error whose absolute value approaches zero.