JPH0464229A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the variation of TFT characteristics by forming an intermediate film having film thickness of 50-100Angstrom and satisfying the conditions of specific formula between a protective film and both a TFT and an electrode wiring. CONSTITUTION:sigma is increased with the elevation of a temperature T in the relationship of sigma0 and 1/T in formula (II), and sigma is sigma0 when 1/T=0 holes. Consequently, sigma0 represents electric conductivity at the time of 1/T=0. sigma can be controlled as the result according to any determination of the constant sigma0 and Ea. Accordingly, an intermediate film having theta0 and Ea satisfying the relationship of formula (I) is selected. The intermediate film is formed of an amorphous material mainly comprising Si, to which a dopant selected from a group consisting of small qualitities of B, C and N is doped, and 0. The intermediate film is formed, thus preventing the variation of a threshold.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a semiconductor device with an improved structure.

[Prior art]

It is known that a TFT fabricated on an insulating substrate has a lower electrostatic capacity than an element such as an MO8 type transistor fabricated in a Si wafer. For this reason, in the process of manufacturing TFTs on insulating substrates, it is important to take measures against static electricity and prevent charge build-up. TFT and TF
After forming the electrode wiring that connects the T, generally plasma CVD
An insulating protective film of SiN, 5iON, etc. is formed on the entire surface by a method.

At this time, due to charge-up during plasma CVD,
This results in variations in the threshold voltage of the TFT.

As a countermeasure to these problems, each electrode of the TFT was short-circuited on the wiring pattern, and a protective film was formed.

There is a method of reducing damage caused by charge-up by removing the protective film on the short-circuited portion and further opening the short-circuited portion (Japanese Unexamined Patent Publication No. 2-18524).

However, this measure not only complicates the photolithography process but also adversely affects the weather resistance and reliability of the TFT substrate since a portion of the protective film is removed. In addition, in wiring patterns such as matrix wiring, wiring for short circuits can be easily done if there are few wirings in that area, but
It was practically impossible to implement this method with a pattern in which drains and gates were arranged in a complicated manner.

Furthermore, as another countermeasure, a method has been proposed in which ions on a substrate are neutralized by providing means for supplying electrons during plasma CVD (Japanese Unexamined Patent Publication No. 1-270320).

However, this method is considered to have low reproducibility of effects within a film forming apparatus and low applicability to large-area substrates.

〔the purpose〕

In the present invention, by adding a semi-insulating thin film with active electrical conductivity, the insulating protective film can be converted into a plasma CVD film.
An object of the present invention is to provide a semiconductor device that does not cause damage to a TFT substrate even when formed using D.

〔composition〕

The present invention relates to a semiconductor device comprising an insulating substrate, a film transistor (hereinafter referred to as TFT) provided on the insulating substrate, an electrode wiring connected to the TFT, and a protective film covering the TFT and the electrode wiring. The present invention relates to a semiconductor device characterized in that an intermediate film having a thickness of 50 to 100 mm and satisfying the conditions of the following formula is provided between a protective film, a TFT, and an electrode wiring.

22.2×Ea−18,4〈Qnσ. <37.0×E
a-27,6-(I) [In addition, σ0 and Ea correspond to those in the known formula, σ is the electrical conductivity σ of the intermediate film. is the Boltzmann constant, T is the absolute temperature, and Ea is the activation energy (eV). ] In addition, σ in the above-mentioned known formula (U). The relationship between and 1/T is shown in FIG. As temperature T increases, σ increases, and σ at 1/T20 is σ. It is closed. Therefore σ.

is the electrical conductivity when 1/T=O. σ is.

constant σ. The result can be controlled by how and Ea are determined. Therefore, in the present invention, σ satisfies the relationship of equation (1). It is important to select an interlayer film having Ea and Ea.

The intermediate film is formed of an amorphous material mainly composed of Si and O doped with a small amount of a dopant selected from the group consisting of B, C, and N.

Particularly preferred is a-5iO:H doped with B.

In FIG. 3, the range that satisfies the formula of the present invention is shown with diagonal lines.

The horizontal axis is the activation energy Ea, and the vertical axis is the electrical conductivity σ expressed by a known equation called the active type conduction equation. It is. FIG. 4 is a diagram showing the effect of the present invention on TFT characteristics, and the dotted line indicates the case where the present invention is not applied (no interlayer film 7).
This is the l1Va characteristic after forming the protective film 8, and a fluctuation in the threshold voltage can be seen. In comparison, when the interlayer film 7 was provided, no fluctuation in the threshold value was observed as shown by the solid line.

〔Example〕

FIG. 1 is a sectional view showing a specific example of the semiconductor device of the present invention.

This semiconductor device consists of an active layer 2 formed on a quartz glass plate 1.
, a gate insulating film 3, a gate electrode 4, an interlayer insulating layer 5, an electrode wiring 6, the intermediate film 7, and a protective film 8.

The active layer 2 is made of polycrystalline silicon and has a thickness of approximately 300 nm.
Gate insulating layer 3 is created by thermal oxidation of polycrystalline silicon. Thermal oxidation temperature is 1070℃, atmosphere is 02/HC
Q mixture, film thickness is approximately 900.

The gate electrode 4 is made of polycrystalline silicon and has a film thickness of about 3
000 people.

The resistance of both ends of the active layer is reduced by ion implantation.

The interlayer insulation N5 is a Sin film, and the film thickness is about 3000. After forming contact holes in the glabellar insulating layer 5, AQ is deposited to a thickness of about 1 μm by vacuum evaporation for electrode wiring. After forming the wiring pattern, about 100 people formed the intermediate film 7 according to the present invention. The production method is a parallel plate plasma CVD method.

This plasma CVD method was carried out under the following conditions with a sample set on the grounded substrate electrode side.

■S i H, gas flow rate 135CCM ■H2 gas flow rate 505CCM ■C○2 gas flow rate 605CCM ■B z H
s/H, (2000PPO1) Gas flow rate 0.3
SCCM■Pressure 0.8 Torr
■RF power 30 W ■Interelectrode distance 25■ After this, immediately apply a 5iON film or Si as a protective film.
A N film with a thickness of about 1 μm was formed by plasma CVD.

FIG. 2 is a plan view of the semiconductor device of FIG.
, the active layer 2, the gate insulating layer 3, the gate electrode 4, etc. cannot be seen. However, the presence of the interlayer film 7 is indicated by diagonal lines. The protective film 8 covers the entire surface.

The intermediate film 7 in the semiconductor device produced under the above conditions has the following characteristics: σ. = 1900 (Ω-7”) Ea = 0.92 (ev), so the electrical conductivity at 20°C is a = 2.9X10-” (Ω-
"Cat-") The electrical conductivity at 250℃ is σ=2.6X1
0-'(Ω-"m-1). 20°C is the standard operating temperature for TFTs, and 250°C is a typical temperature for producing intermediate films, protective films, etc.

For example, if the resistance value between the Afl wiring and the intermediate film is determined.

Assuming that the width (W) is 3 mm and the length (L) is 10 μm, the resistance R can be found as L R = σ WXd.

This value is a sufficient resistance value at room temperature and is an effective value for preventing static electricity during film formation.

[Effects] Due to the presence of the intermediate film, the present invention allows the substrate temperature to reach a temperature of 250 to 350° C. when forming a protective film such as SiN or SiON, and a semi-insulating thin film has a thickness of 10 m”. It has an electrical conductivity of (Ω-1 cm-”) or higher, and has the effect of preventing the substrate from being charged during plasma CVD, and as a result, it was possible to prevent variations in TFT characteristics.

■The normal operating environment of the fabricated TFT substrate is approximately 1
At this temperature, a semi-insulating thin film has an electrical conductivity of less than 10-"(Ω-7") and is thin, less than 100 Å, so it is difficult to protect between electrode wiring. The resistance of the membrane could be set to about 1015Ω.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a specific example of the semiconductor device of the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is the activation energy Ea and electric conductivity σ of the intermediate film of the present invention. FIG. 4 is a graph showing the TFT characteristics of the semiconductor device of the present invention, and FIG. 5 is a graph showing the relationship between σ and 17T in formula (II). 1... Quartz substrate 2... Active layer 3... Gate insulating layer 4... Gate electrode 5... Interlayer insulating layer 6... Electrode wiring 7... Intermediate film 8... Protective film Patent Roganjin Ricoh Co., Ltd.

Claims (1)

[Claims] 1. An insulating substrate, a thin film transistor provided thereon (
In a semiconductor device comprising a TFT (hereinafter referred to as a TFT), an electrode wiring connected to the TFT, and a protective film covering the TFT and the electrode wiring, a film thickness of 50 to A semiconductor device characterized by providing an intermediate film having a thickness of 100 Å and satisfying the conditions of the following formula. 22.2×Ea-18.4<lnσ_0<37.0×E
a-27.6 [In addition, σ_0 and Ea correspond to those in the known formula σ=σ_0exp(-[Ea/kT]), σ is the electrical conductivity of the interlayer film σ_0 is the constant k is the Boltzmann constant T is the absolute temperature, Ea is activation energy (ev). ]