JPH0464182B2 - - Google Patents

Info

Publication number
JPH0464182B2
JPH0464182B2 JP58107150A JP10715083A JPH0464182B2 JP H0464182 B2 JPH0464182 B2 JP H0464182B2 JP 58107150 A JP58107150 A JP 58107150A JP 10715083 A JP10715083 A JP 10715083A JP H0464182 B2 JPH0464182 B2 JP H0464182B2
Authority
JP
Japan
Prior art keywords
film
shaped groove
region
sio
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58107150A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59232439A (ja
Inventor
Juji Furumura
Takeshi Nishizawa
Masayuki Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58107150A priority Critical patent/JPS59232439A/ja
Publication of JPS59232439A publication Critical patent/JPS59232439A/ja
Publication of JPH0464182B2 publication Critical patent/JPH0464182B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials

Landscapes

  • Element Separation (AREA)
JP58107150A 1983-06-15 1983-06-15 半導体装置の製造方法 Granted JPS59232439A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58107150A JPS59232439A (ja) 1983-06-15 1983-06-15 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58107150A JPS59232439A (ja) 1983-06-15 1983-06-15 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS59232439A JPS59232439A (ja) 1984-12-27
JPH0464182B2 true JPH0464182B2 (show.php) 1992-10-14

Family

ID=14451771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58107150A Granted JPS59232439A (ja) 1983-06-15 1983-06-15 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS59232439A (show.php)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6406982B2 (en) * 2000-06-05 2002-06-18 Denso Corporation Method of improving epitaxially-filled trench by smoothing trench prior to filling
JP2009277851A (ja) 2008-05-14 2009-11-26 Nec Electronics Corp 半導体装置、半導体装置の製造方法及びパワーアンプ素子

Also Published As

Publication number Publication date
JPS59232439A (ja) 1984-12-27

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