JPH0464116A - Input / output circuit - Google Patents

Input / output circuit

Info

Publication number
JPH0464116A
JPH0464116A JP17701190A JP17701190A JPH0464116A JP H0464116 A JPH0464116 A JP H0464116A JP 17701190 A JP17701190 A JP 17701190A JP 17701190 A JP17701190 A JP 17701190A JP H0464116 A JPH0464116 A JP H0464116A
Authority
JP
Japan
Prior art keywords
input
output
data
switch
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17701190A
Other languages
Japanese (ja)
Inventor
Yasuhiko Okasaka
岡阪　康彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17701190A priority Critical patent/JPH0464116A/en
Publication of JPH0464116A publication Critical patent/JPH0464116A/en
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To multiplex plural data by one input / output pin and to reduce the number of input / output pins by providing a switch, which state is changed after the lapse of certain prescribed time, in one input / output pin and switching input / output circuits to be transmitted to respectively different internal circuits. CONSTITUTION:Input / output circuits 6 and 7 are changed over by a switch 2 which state is changed after the lapse of certain fixed time. Namely, when a signal announcing the input of a data is inputted to input / output circuits A6 and B7 and the input / output circuit A6 is turned to an operational state according to the signal of a multiplex generation circuit 5, the data is transmitted to an I/O A by the multiplex switch 2. Next, the signal is inputted from the multiplex generation circuit 5, the state of the switch 2 is changed, the input / output circuit A6 is turned to an unoperational state, the input / output circuit B7 is turned to the operational state, and the data is transmitted to an I/O B. Thus, the plural data are multiplexed and inputted / outputted, and the number of input / output pins 1 can be decreased.

Description

【発明の詳細な説明】 〔産業上の利用分野］ この発明は半導体装置に関し、特にその入出力回路を提
供するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to an input/output circuit thereof.

〔従来の技術〕[Conventional technology]

第３図は従来の入出力回路のブロックを示す。 FIG. 3 shows a block diagram of a conventional input/output circuit.

図において、（１）は入出力ピン（又はパッド’）　、
（３）は入力回路、（４）は出力回路、ＩｌｏはＩ１０
線を示している。In the figure, (1) is the input/output pin (or pad'),
(3) is the input circuit, (4) is the output circuit, Ilo is I10
It shows the line.

次に動作について説明する。Next, the operation will be explained.

初めにデータを入力する場合、データの入力を知らせる
信号により、入力回路（３）を動作状態にして入出力ピ
ン（１）のデータをＩ１０線に伝える。次にデータを出
力する場合は、データの出力を知らせる信号により、出
力回路（４）を動作状態にしてＩ１０線のデータを入出
力ピン（１）に出力する、［発明が解決しようとする課
題］ 従来の入出力回路は以上のように構成されていたので、
１つのピンに１つの入出力回路しか接続されておらず、
このため入出力ピンの数が多くなると、ＩＣが極めて大
きくなるという問題点があった。When inputting data for the first time, the input circuit (3) is activated by a signal indicating data input, and the data at the input/output pin (1) is transmitted to the I10 line. Next, when data is to be output, the output circuit (4) is activated by a signal indicating data output, and the data on the I10 line is output to the input/output pin (1). ] Since the conventional input/output circuit was configured as above,
Only one input/output circuit is connected to one pin,
Therefore, when the number of input/output pins increases, there is a problem that the IC becomes extremely large.

この発明は上記のような問題点を解消するためなされた
もので、複数のデータをマルチブレクスして入出力し入
出力ピンの数を減らすことができる入出力回路を得るこ
とを目的とする。The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an input/output circuit that can multiplex a plurality of data to input/output and reduce the number of input/output pins.

［課題を解決するための手段］ この発明に係る入出力回路は、入出力ピンにある一定時
間経過するとその状態が変わるスイッチを設け、このス
イッチによって入出力回路を切換えるようＫしたもので
ある。[Means for Solving the Problems] The input/output circuit according to the present invention is such that an input/output pin is provided with a switch whose state changes after a certain period of time has elapsed, and the input/output circuit is switched by this switch.

〔作用１ この発明における入出力回路は、ある一定時間経過する
と状態が変わるスイッチにより、入出力回路を切換える
ことができるので、１つの入出力ピンで複数の入出力デ
ータをマルチプレクスできる。[Function 1] The input/output circuit according to the present invention can be switched by a switch whose state changes after a certain period of time has elapsed, so a plurality of input/output data can be multiplexed with one input/output pin.

〔実施例］ 以下、この発明の一実施例を図について説明する。第１
図において、（１）は入出力ピン（又はパッド）、（２
）はスイッチ、（３）は入力回路、（４）は出力四次に
動作について説明するっ まず、データの入力の場合について説明する。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
In the figure, (1) is an input/output pin (or pad), (2
) is a switch, (3) is an input circuit, and (4) is an output circuit. First, the case of data input will be explained.

データの入力を知らせる信号を入出力回路Ａ（６）、入
出力回路Ｂ（７）に入力し、またはマルチブレクヌ発生
回路（５）の信号により、入出力回路Ａ（６）を動作状
態にする。この時マルチブレクススイッチ（２）ニより
入出力回路Ａ（６）の入力回路（３）を通ってＩｌｏ　
Ａにデータが伝わる。次に、マルチプレクス発生回絡（
５）から信号が出てスイッチ（２）の状態が変化し、ま
た入出力回路Ａ（６）が非動作状態となり入出力回路Ｂ
（７）が動作状態となって工１０　Ｂにデータが伝わる
。A signal informing input of data is input to input/output circuit A (6) and input/output circuit B (7), or the input/output circuit A (6) is put into an operating state by a signal from the multi-breech generating circuit (5). At this time, Ilo is passed through the input circuit (3) of the input/output circuit A (6) from the multiplex switch (2)
Data is transmitted to A. Next, the multiplex generation circuit (
A signal is output from 5), the state of switch (2) changes, and input/output circuit A (6) becomes inactive, and input/output circuit B
(7) becomes operational and data is transmitted to the workpiece 10B.

データの出力状態について説明するっ データの出力を知らせる信号が入出力回路Ａ（６）、入
出力回路Ｂ（７）の出力回路に入力され、マルチプレク
ヌ発生信号により入出力回路Ａ（６）が動作状態となり
、データが出力される。The data output state will be explained. A signal indicating data output is input to the output circuits of input/output circuit A (6) and input/output circuit B (7), and input/output circuit A (6) is operated by the multiplex generation signal. state and data is output.

次に、マルチプレクス発生回路（５）から信号が出てス
イッチ（２）の状態が変化し、また入出力回路Ａ（６）
が非動作状態になり、入出力回路Ｂ（７）が動作状態と
なってデータが出力される。Next, a signal is output from the multiplex generation circuit (5) to change the state of the switch (2), and the input/output circuit A (6)
becomes inactive, input/output circuit B (7) becomes active, and data is output.

第２図は１６個のテ゛−夕を入出力回路を８個用いた場
合の動作状態を示す波形図である。FIG. 2 is a waveform diagram showing the operating state when 16 devices are used with 8 input/output circuits.

例えばマルチブレクヌ信号が１Ｌ“の時ＫＤＱ、０〜Ｄ
Ｑ７のデータを入出力回路Ａ（６）で入出力を行い、マ
ルチブレクス信号が′Ｈ“の時にＤＱ４〜ＤＱＩ５のデ
ータを入出力回路Ｂ（７）で入出力を行うことを示して
いる。For example, when the multi-brecnu signal is 1L, KDQ, 0~D
It is shown that the data of Q7 is input/output by the input/output circuit A (6), and the data of DQ4 to DQI5 is input/output by the input/output circuit B (7) when the multiplex signal is 'H''.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、１つの入出力ピンにあ
る一定時間経過すると状態が変化するスイッチを設け、
このスイッチにそれぞれ異なる内部回路に伝わる入出力
回路を切換えるようにしたので、１つの入出力ピンで複
数のデータをマルチデレクスすることができ、入出力ピ
ンの本数を減らすことができるという効果がある。As described above, according to the present invention, one input/output pin is provided with a switch whose state changes after a certain period of time,
Since this switch is used to switch the input/output circuits that are transmitted to different internal circuits, multiple data can be multidirected with one input/output pin, which has the effect of reducing the number of input/output pins. be.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例である入出力回路の回路図
、第２図は第１図の各部信号の波形図、第３図は従来の
入出力回路の回路図である。 図において、（１）は入出力ピン、（２）はスイッチ、
（３）は入力回路、（４）は出力回路、（５）はマルチ
ブレクス発生回路、（６）は入出力口Ｋ　Ａ　、　（７
）は入出力回路Ｂを示す。 なお、図中、同一符号は同一、または相当部分を示す。 第１＠ １゛Ｘエカピン ２：スイッチ ３人力回給 ４：エカＱ給 ５：マルチブレク又発庄−田経 ２：入瓜ｆＪ回給Ａ ７入ふ力回給ＢFIG. 1 is a circuit diagram of an input/output circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of various signals of FIG. 1, and FIG. 3 is a circuit diagram of a conventional input/output circuit. In the figure, (1) is an input/output pin, (2) is a switch,
(3) is the input circuit, (4) is the output circuit, (5) is the multiplex generation circuit, (6) is the input/output port K A, (7
) indicates input/output circuit B. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. 1st @ 1゛

Claims (1)

【特許請求の範囲】[Claims] １つの入出力ピンにある一定時間が経過するとその状態
が変化するスイッチを設け、このスイッチにはそれぞれ
異なる内部回路に伝わる入出力回路を切換えるようにし
たことを特徴とする入出力回路。An input/output circuit characterized in that one input/output pin is provided with a switch whose state changes after a certain period of time has elapsed, and each switch is configured to switch input/output circuits transmitted to different internal circuits.
JP17701190A 1990-07-02 1990-07-02 Input / output circuit Pending JPH0464116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17701190A JPH0464116A (en) 1990-07-02 1990-07-02 Input / output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17701190A JPH0464116A (en) 1990-07-02 1990-07-02 Input / output circuit

Publications (1)

Publication Number Publication Date
JPH0464116A true JPH0464116A (en) 1992-02-28

Family

ID=16023604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17701190A Pending JPH0464116A (en) 1990-07-02 1990-07-02 Input / output circuit

Country Status (1)

Country Link
JP (1) JPH0464116A (en)

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