JPH0463479B2 - - Google Patents

Abstract

PURPOSE:To improve the defect relieving factor of an entire element by inactivating a column decoder or all related bit lines if the column decoder itself is defective or a related bit line has a defective bit and replacing the decoder with a spare column decoder by an inactivated column selecting signal. CONSTITUTION:If a defective bit exists in a cell relating to a bit line BLn' or this normal column decoder is defective, links L1 and L2 are blown by a laser so as to make the sets of the two bit lines BLn, BLn', BLn+1, BLn+1' nonselective. Thus, the column decoder or all bit lines BLn-BLn+1' are made inactivated. Then, the replacement to spare bit lines SBL1-SBL2 is attained by blowing one of the sets of links L1, L12, L13, L14,-L21, L22 by a laser, an address signal and its complementary signal selecting a normal column decoder are combined to activate the spare column decoder.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device with so-called redundancy, which has built-in spare bits for relieving defective bits.

[Prior art]

FIGS. 1a and 1b are circuit diagrams showing conventional semiconductor memory devices, and a laser program type redundant dynamic MOS semiconductor memory device will be described as an example. First, in the regular column decoder, sense amplifier circuit, input/output control circuit, and bit line precharge circuit shown in FIG. 1a,
Q ₁ to Q ₁₆ are insulated gate field effect transistors (hereinafter referred to as MOST) that constitute the column decoder;
Q ₁₇ to _{Q 32} are MOSTs that constitute the input/output control circuit,
S ₀ to _{S 3} are sense amplifier circuits, Q ₃₃ to Q ₄₀ are MOSTs that select the sense amplifier circuits S ₀ to _{S 3} ,
Q ₄₁ and Q ₄₂ are MOSTs forming the sense amplifier circuit S ₀ , Q ₄₃ to _{Q 50} are MOSTs forming the bit line precharge circuit, L ₁ to _{L 8} are links that can be fused with a laser, and I/O ₀ ,/O ₀ ~I/O ₃ ,/
_O3 is the input/output line connected to one end of each link _L1 to _L8 ,
BL ₀ , ₀ , ~ BL ₃ , ₃ are bit lines, SA ₀ , ₀
~SA ₃ , ₃ is a sense node, CA ₂ , ₂ , ~
CA ₇ and ₇ are column selection address signal lines, N ₁ is the output node of the column decoder, and CS is this output node.
N ₁ and the MOSTQ ₁₇ , Q ₁₉ , Q ₂₁ , Q ₂₃ , Q ₂₅ ,
Separation signal for separating the gates of Q ₂₇ , Q ₂₉ and Q ₃₁ , PCD is the column decoder precharge signal, S
is the activation signal of the sense amplifier circuit, SI is the bit line
A separation signal for separating BL ₀ to ₃ and sense nodes SA ₀ to ₃ , CP is a bit line precharge signal, Vcc is a power supply voltage, and Vss is a ground potential.
Furthermore, in the spare column decoder, spare sense amplifier circuit, spare input/output control circuit, and spare bit precharge circuit shown in _FIG .
Q ₇₂ constitutes the spare column decoder MOST, Q ₇₃
~Q ₈₈ constitutes a spare input/output control circuit
MOST, SS are spare sense amplifiers, Q ₈₉ to _{Q 92} are MOST, Q ₉₃ that constitute the spare sense amplifier circuit SS
and Q ₉₄ are MOST for precharging the spare bit line SBL, and L ₁₁ to _{L 30} are links that can be cut by laser.

Next, the operation of the semiconductor memory device with the above configuration will be explained. First, if there is no defective bit in the memory (not shown) connected to the bit line, the links _L1 to _L8 will not be fused. In this state, when address signals CA ₂ to CA ₇ such that the gate voltages of MOSTQ ₁ to _{Q 5} become 0V are input, the output node N ₁ of the column decoder is held at a high potential.
On the other hand, nodes connected to the outputs of other row decoders (not shown) are always discharged to the ground potential Vss. next,
When the separation signal CS with a high potential is input,
MOSTQ ₇ and Q ₈ , MOSTQ ₁₂ and Q ₁₃ are turned on. Therefore, the high potential at node N ₁ passes through this on-state MOSTQ ₇ and Q ₈ .
It is transmitted to the gates of MOSTQ ₁₇ to Q ₂₄ , respectively, and to the gates of MOSTQ ₂₅ to Q ₃₂ , respectively, through the on-state MOSTQ ₁₂ and Q ₁₃ , thereby connecting the I/O line, the sense node, and the bit line. At this time, the voltages on the bit line and sense node read from the memory cell (not shown) by a row selection signal (not shown) and a sense amplifier are transmitted to the I/O line and taken into the output circuit (not shown). It will be done. On the other hand, since there are no defective bits _at the _{node N2} connected to the output of the spare column decoder shown in FIG. ,
Reserve bit lines SBL and are never selected.

Next, for example, if there is a defective memory cell (not shown) connected to bit line ₁ , links L ₂ and L ₆ are connected to prevent data from being read/written from the defective bit. Cut by laser. Therefore, bit line ₁ ,
The signals of BL ₁ and sense nodes ₁ and SA ₁ are not transmitted to input/output lines /O ₁ and I/O ₁ .
In this case, for example, not only the defective bit line ₁ is replaced, but also the bit line _BL1 is replaced at the same time. That is, replacement with the normal spare bit line SBL, shown in _FIG .
L ₁₂ ), (L ₁₃ , L ₁₄ ) to (L ₂₁ , L ₂₂ ) are fused with a laser, and the regular column decoder shown in Figure 1a is used to select the signal. In combination,
This spare column decoder is activated and blows out links L ₂₃ , L ₂₅ , L ₂₆ , L ₂₇ , L ₂₉ and L ₃₀ .

However, in conventional semiconductor memory devices, defects related to memory cells or bit lines can be repaired, but if the regular column decoder itself becomes defective, for example, if MOSTQ ₃ is destroyed, four sets of bit lines ( BL ₀ , ₀ ), (BL ₁ , ₁ ) ~
(BL ₃ , ₃ ) cannot be driven. For this reason, if the decoder occupies a large area with respect to the entire memory element, the defect rate of this type will also be large, so there is a drawback that the defect repair rate cannot be increased.

[Summary of the invention]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that can improve the defect repair rate of the entire memory element even if a regular column decoder and its associated bit line are defective.

In order to achieve this object, the present invention makes it possible to replace the decoder with a spare bit line even if there is a defective bit in the bit line or if the decoder itself becomes defective.

[Embodiments of the invention]

FIGS. 2a and 2b are circuit diagrams showing an embodiment of a semiconductor memory device according to the present invention. Second
In the folded bit linear column decoder shown in Figure a, Q ₁₀₁ to _{Q 111} constitute the column decoder.
MOST, Q ₁₁₂ and Q ₁₁₃ are MOSTs with column subdecode signals CS ₁ and CS ₂ applied to their respective drains,
Q ₁₁₄ and Q ₁₁₅ are MOSTs to which the column quiescent signal CQ is input to each gate, Q ₁₁₆ to _{Q 119} are MOSTs that form input/output control circuits connected to memory cell groups for each pair, and C ₁ and C ₂ is the capacitor, BLn,
BLn, BL _o+1 and _o+1 are bit lines and I/Os to which memory cells and sense amplifiers (not shown) are connected.
and /O are input/output signal lines, CA ₁ , ₁ , ~
CA _{6 6} is a column selection address signal, CAS and column decoder activation signals, and PCD are column decoder precharge signals. In the spare column decoder shown in FIG. 2b, Q ₁₂₁ to _{Q 156} are MOST indicating spare column decoders, C ₃ and C ₄ are capacitors,
_{Q 137} and Q ₁₃₈ are MOST, Q _{139 and
Q140} is a MOST whose gate is inputted with a column quiescent signal CQ and made to have a high resistance, _Q141 to _Q144 are MOSTs forming a spare input/output control circuit, and _SBL1 to _SBL2 are spare bit lines.

Next, the operation of the semiconductor memory device with the above configuration will be explained. First, if there is no defective bit in the memory (not shown) connected to the bit line, links _L1 and _L2 will not be fused. In this state, when address signals CA ₁ , ₁ , to ₆ such that the gate voltages of MOSTQ ₁₀₁ to Q ₁₀₆ become 0V are input, the output node N ₃ of the column decoder is held at a high potential. The high quality of this output node N ₃ then charges the capacitor C ₁ to a high potential through MOSTQ ₁₁₀ . On the other hand, the output nodes of other column decoders (not shown) are always discharged to the ground potential Vss.
Similarly, the output node _N4 of the spare column decoder shown in FIG. 2b is always discharged to the ground potential Vss. Then, for example, when the sub-decode signal CS ₁ goes to a high potential, MOSTQ ₁₁₂ turns on and the capacitor
The high potential charged on C ₁ is passed through link L ₁
Input to the gates of MOSTQ ₁₁₆ and Q ₁₁₇ . Therefore, by selecting input/output signal line I/O or /O, bit line BLn or n
Data can be read/written from. At this time, since MOSTQ ₁₁₄ and Q ₁₁₅ have high resistance, the highest potential of the low impedance sub-decode signal CS ₁ does not attenuate.
Note that the high potential of the sub-decode signal is MOSTQ ₁₁₃
When supplied to MOST, the circuit connected to that MOST is activated.

Next, if there is a defective bit in the bit cell associated with bit line n, or if this regular column decoder becomes defective, for example,
If MOSTQ ₁₀₃ is destroyed, both links L ₁ and L ₂ are fused with a laser, and both bit line sets (BLn, n) and (BL _o+1 , _o+1 ) are deselected. do. Therefore, this column decoder or all bit lines BLn~ _o+1 become inactive.
Therefore, replacement with the spare bit lines SBL ₁ to ₂ consists of links (L ₁₁ , L ₁₂ ), (L ₁₃ , L ₁₄ ), ~(L ₂₁ ,
Either one of each set of _L22 ) is fused with a laser, and this spare column decoder is activated by the combination of the address signal and its complementary signal that selects the regular column decoder shown in Figure 2a. can be converted into At this time, a high-resistance FET is connected to the rear side of the disconnected link and clamps the high-impedance memory selection line potential, so that the potential level does not become unstable.

Note that in the above embodiment, the sub decode signal CS ₁
and CS ₂ , but the present invention is not limited to this, and it goes without saying that the same thing can be done using more sub-decode signals. It goes without saying that the same effect can be achieved by simultaneously disposing sub-decode signals, input/output control circuits, and bit lines on the left side of the column decoder and the spare column decoder. It goes without saying that the present invention can also be similarly applied to other memories having sub-decoded signals, such as static MOS memories and bipolar memories.

〔Effect of the invention〕

As is clear from the above explanation, even if a defective bit exists in the bit line or a defect occurs in the decoder itself, this invention is configured so that it can be replaced with a spare bit line and decoder, thereby ensuring stable operation. This has the effect of increasing the defect recovery rate.

[Brief explanation of drawings]

1A and 1B are circuit diagrams showing a conventional semiconductor memory device, and FIGS. 2A and 2B are circuit diagrams showing an embodiment of the semiconductor memory device according to the present invention. Q ₁ to Q ₁₄₄ ... Insulated gate field effect transistor, S ₀ to S ₂ ... Sense amplifier circuit, L ₁ to _{L 30} ...
Link, I/00~03...Input/output line, BL ₀ ~
BL ₃ ...Bit line, SA ₀ to ₃ ...Sense node,
CA ₂ to ₇ ... Column selection address signal line, CS...
Separation signal, PCD...Precharge signal, S...
Activation signal, SI...Separation signal, CP...Precharge signal, Vcc...Power supply voltage, Vss...Ground potential, SS...Spare sense amplifier, _C1 to _C4 ...Capacitor, BLn to _o+1 ...bit lines, I/O and /O ...input/output signal lines, CA ₁ to ₆ ... selected address signal lines, CAS and ... activation signals, SBL ₁ to ₂ ... spare bit lines. In addition,
In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1 A memory is provided with a regular decoder and a spare decoder, and the regular decoder has a source or a drain connected to an output node for the regular decoder, the other to a ground potential node, and a plurality of gates receiving an address signal. 1 MOS transistor, one of the source or drain is connected to the output node for the regular decoder, the other is connected to the power supply potential node, and a second MOS transistor receives a precharge signal at the gate, and one of the source or drain is connected to the output node for the regular decoder. a plurality of nodes connected to the normal decoder output node and having a power supply potential applied to their gates to transmit the potential of the normal decoder output node.
3 MOS transistors, and for each of the same number of third MOS transistors, the gate is connected to the other of the source or drain of the corresponding third MOS transistor, and one of the sources or drains is connected to the gate of the MOS transistor. A plurality of transistors connected to the selection line of the regular memory cell via a fusible link and receiving a selection line drive signal of the memory cell at the other of the source or drain.
The preliminary decoder includes four MOS transistors, and a fifth MOS transistor whose source and drain are connected between the selection line of the regular memory cell and a predetermined potential node, and whose gate receives a signal and is brought into a high resistance state. , a plurality of MOS transistors each consisting of a pair of MOS transistors, one of whose sources and drains are connected to the preliminary decoder output node via a fusible link and the other to a ground potential node, and whose gates receive complementary address signals. 6 MOS transistors, one of whose source or drain is connected to the output node for the preliminary decoder, and the other is connected to the power supply potential node, and a seventh MOS transistor whose gate receives a precharge signal, and one of the source or drain is connected to the output node for the preliminary decoder. a plurality of eighth MOS transistors that are connected to the node, have a power supply potential applied to their gates, and transmit the potential of the preliminary decoder output node, and the eighth MOS transistors have the same number of eighth MOS transistors and have gates corresponding to each of the eighth MOS transistors. is connected to the other of the source or drain of the transistor, one of the source or drain is connected via a fusible link to the selection line of the spare memory cell to which the gate of the MOS transistor is connected, and one of the source or drain is connected to the other of the source or drain. A plurality of ninth MOS transistors that receive memory cell selection line drive signals, their sources and drains are connected between the selection line of the spare memory cell and a predetermined potential node, and are set in a high resistance state by receiving the signal at their gates. A semiconductor memory device comprising a tenth MOS transistor.